99void SelectionDAG::DAGNodeDeletedListener::anchor() {}
100void SelectionDAG::DAGNodeInsertedListener::anchor() {}
102#define DEBUG_TYPE "selectiondag"
106 cl::desc(
"Gang up loads and stores generated by inlining of memcpy"));
109 cl::desc(
"Number limit for gluing ld/st of memcpy."),
125 return getValueAPF().bitwiseIsEqual(V);
148 N->getValueType(0).getVectorElementType().getSizeInBits();
149 if (
auto *Op0 = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
150 SplatVal = Op0->getAPIntValue().
trunc(EltSize);
153 if (
auto *Op0 = dyn_cast<ConstantFPSDNode>(
N->getOperand(0))) {
154 SplatVal = Op0->getValueAPF().bitcastToAPInt().
trunc(EltSize);
159 auto *BV = dyn_cast<BuildVectorSDNode>(
N);
164 unsigned SplatBitSize;
166 unsigned EltSize =
N->getValueType(0).getVectorElementType().getSizeInBits();
171 const bool IsBigEndian =
false;
172 return BV->isConstantSplat(SplatVal, SplatUndef, SplatBitSize, HasUndefs,
173 EltSize, IsBigEndian) &&
174 EltSize == SplatBitSize;
183 N =
N->getOperand(0).getNode();
192 unsigned i = 0, e =
N->getNumOperands();
195 while (i != e &&
N->getOperand(i).isUndef())
199 if (i == e)
return false;
210 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
212 if (CN->getAPIntValue().countr_one() < EltSize)
215 if (CFPN->getValueAPF().bitcastToAPInt().countr_one() < EltSize)
223 for (++i; i != e; ++i)
224 if (
N->getOperand(i) != NotZero && !
N->getOperand(i).isUndef())
232 N =
N->getOperand(0).getNode();
241 bool IsAllUndef =
true;
254 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
256 if (CN->getAPIntValue().countr_zero() < EltSize)
259 if (CFPN->getValueAPF().bitcastToAPInt().countr_zero() < EltSize)
286 if (!isa<ConstantSDNode>(
Op))
299 if (!isa<ConstantFPSDNode>(
Op))
307 assert(
N->getValueType(0).isVector() &&
"Expected a vector!");
309 unsigned EltSize =
N->getValueType(0).getScalarSizeInBits();
310 if (EltSize <= NewEltSize)
314 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
319 return (
N->getOperand(0).getValueType().getScalarSizeInBits() <=
329 if (!isa<ConstantSDNode>(
Op))
332 APInt C =
Op->getAsAPIntVal().trunc(EltSize);
333 if (
Signed &&
C.trunc(NewEltSize).sext(EltSize) !=
C)
335 if (!
Signed &&
C.trunc(NewEltSize).zext(EltSize) !=
C)
346 if (
N->getNumOperands() == 0)
352 return N->getOpcode() ==
ISD::FREEZE &&
N->getOperand(0).isUndef();
355template <
typename ConstNodeType>
357 std::function<
bool(ConstNodeType *)>
Match,
360 if (
auto *
C = dyn_cast<ConstNodeType>(
Op))
368 EVT SVT =
Op.getValueType().getScalarType();
370 if (AllowUndefs &&
Op.getOperand(i).isUndef()) {
376 auto *Cst = dyn_cast<ConstNodeType>(
Op.getOperand(i));
377 if (!Cst || Cst->getValueType(0) != SVT || !
Match(Cst))
383template bool ISD::matchUnaryPredicateImpl<ConstantSDNode>(
385template bool ISD::matchUnaryPredicateImpl<ConstantFPSDNode>(
391 bool AllowUndefs,
bool AllowTypeMismatch) {
392 if (!AllowTypeMismatch &&
LHS.getValueType() !=
RHS.getValueType())
396 if (
auto *LHSCst = dyn_cast<ConstantSDNode>(
LHS))
397 if (
auto *RHSCst = dyn_cast<ConstantSDNode>(
RHS))
398 return Match(LHSCst, RHSCst);
401 if (
LHS.getOpcode() !=
RHS.getOpcode() ||
406 EVT SVT =
LHS.getValueType().getScalarType();
407 for (
unsigned i = 0, e =
LHS.getNumOperands(); i != e; ++i) {
410 bool LHSUndef = AllowUndefs && LHSOp.
isUndef();
411 bool RHSUndef = AllowUndefs && RHSOp.
isUndef();
412 auto *LHSCst = dyn_cast<ConstantSDNode>(LHSOp);
413 auto *RHSCst = dyn_cast<ConstantSDNode>(RHSOp);
414 if ((!LHSCst && !LHSUndef) || (!RHSCst && !RHSUndef))
416 if (!AllowTypeMismatch && (LHSOp.
getValueType() != SVT ||
419 if (!
Match(LHSCst, RHSCst))
426 switch (VecReduceOpcode) {
431 case ISD::VP_REDUCE_FADD:
432 case ISD::VP_REDUCE_SEQ_FADD:
436 case ISD::VP_REDUCE_FMUL:
437 case ISD::VP_REDUCE_SEQ_FMUL:
440 case ISD::VP_REDUCE_ADD:
443 case ISD::VP_REDUCE_MUL:
446 case ISD::VP_REDUCE_AND:
449 case ISD::VP_REDUCE_OR:
452 case ISD::VP_REDUCE_XOR:
455 case ISD::VP_REDUCE_SMAX:
458 case ISD::VP_REDUCE_SMIN:
461 case ISD::VP_REDUCE_UMAX:
464 case ISD::VP_REDUCE_UMIN:
467 case ISD::VP_REDUCE_FMAX:
470 case ISD::VP_REDUCE_FMIN:
473 case ISD::VP_REDUCE_FMAXIMUM:
476 case ISD::VP_REDUCE_FMINIMUM:
485#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) \
488#include "llvm/IR/VPIntrinsics.def"
496#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
497#define VP_PROPERTY_BINARYOP return true;
498#define END_REGISTER_VP_SDNODE(VPSD) break;
499#include "llvm/IR/VPIntrinsics.def"
508#define BEGIN_REGISTER_VP_SDNODE(VPSD, ...) case ISD::VPSD:
509#define VP_PROPERTY_REDUCTION(STARTPOS, ...) return true;
510#define END_REGISTER_VP_SDNODE(VPSD) break;
511#include "llvm/IR/VPIntrinsics.def"
521#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, ...) \
524#include "llvm/IR/VPIntrinsics.def"
533#define BEGIN_REGISTER_VP_SDNODE(VPSD, LEGALPOS, TDNAME, MASKPOS, EVLPOS) \
536#include "llvm/IR/VPIntrinsics.def"
546#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) case ISD::VPOPC:
547#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) return ISD::SDOPC;
548#define END_REGISTER_VP_SDNODE(VPOPC) break;
549#include "llvm/IR/VPIntrinsics.def"
558#define BEGIN_REGISTER_VP_SDNODE(VPOPC, ...) break;
559#define VP_PROPERTY_FUNCTIONAL_SDOPC(SDOPC) case ISD::SDOPC:
560#define END_REGISTER_VP_SDNODE(VPOPC) return ISD::VPOPC;
561#include "llvm/IR/VPIntrinsics.def"
608 bool isIntegerLike) {
633 bool IsInteger =
Type.isInteger();
638 unsigned Op = Op1 | Op2;
654 bool IsInteger =
Type.isInteger();
689 ID.AddPointer(VTList.
VTs);
695 for (
const auto &
Op : Ops) {
696 ID.AddPointer(
Op.getNode());
697 ID.AddInteger(
Op.getResNo());
704 for (
const auto &
Op : Ops) {
705 ID.AddPointer(
Op.getNode());
706 ID.AddInteger(
Op.getResNo());
719 switch (
N->getOpcode()) {
728 ID.AddPointer(
C->getConstantIntValue());
729 ID.AddBoolean(
C->isOpaque());
734 ID.AddPointer(cast<ConstantFPSDNode>(
N)->getConstantFPValue());
750 ID.AddInteger(cast<RegisterSDNode>(
N)->
getReg());
753 ID.AddPointer(cast<RegisterMaskSDNode>(
N)->getRegMask());
756 ID.AddPointer(cast<SrcValueSDNode>(
N)->getValue());
760 ID.AddInteger(cast<FrameIndexSDNode>(
N)->getIndex());
764 if (cast<LifetimeSDNode>(
N)->hasOffset()) {
765 ID.AddInteger(cast<LifetimeSDNode>(
N)->
getSize());
770 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getGuid());
771 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getIndex());
772 ID.AddInteger(cast<PseudoProbeSDNode>(
N)->getAttributes());
776 ID.AddInteger(cast<JumpTableSDNode>(
N)->getIndex());
777 ID.AddInteger(cast<JumpTableSDNode>(
N)->getTargetFlags());
782 ID.AddInteger(CP->getAlign().value());
783 ID.AddInteger(CP->getOffset());
784 if (CP->isMachineConstantPoolEntry())
785 CP->getMachineCPVal()->addSelectionDAGCSEId(
ID);
787 ID.AddPointer(CP->getConstVal());
788 ID.AddInteger(CP->getTargetFlags());
800 ID.AddInteger(LD->getMemoryVT().getRawBits());
801 ID.AddInteger(LD->getRawSubclassData());
802 ID.AddInteger(LD->getPointerInfo().getAddrSpace());
803 ID.AddInteger(LD->getMemOperand()->getFlags());
808 ID.AddInteger(ST->getMemoryVT().getRawBits());
809 ID.AddInteger(ST->getRawSubclassData());
810 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
811 ID.AddInteger(ST->getMemOperand()->getFlags());
822 case ISD::VP_STORE: {
830 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD: {
837 case ISD::EXPERIMENTAL_VP_STRIDED_STORE: {
844 case ISD::VP_GATHER: {
852 case ISD::VP_SCATTER: {
941 if (
auto *MN = dyn_cast<MemIntrinsicSDNode>(
N)) {
942 ID.AddInteger(MN->getRawSubclassData());
943 ID.AddInteger(MN->getPointerInfo().getAddrSpace());
944 ID.AddInteger(MN->getMemOperand()->getFlags());
945 ID.AddInteger(MN->getMemoryVT().getRawBits());
968 if (
N->getValueType(0) == MVT::Glue)
971 switch (
N->getOpcode()) {
979 for (
unsigned i = 1, e =
N->getNumValues(); i != e; ++i)
980 if (
N->getValueType(i) == MVT::Glue)
997 if (Node.use_empty())
1012 while (!DeadNodes.
empty()) {
1021 DUL->NodeDeleted(
N,
nullptr);
1024 RemoveNodeFromCSEMaps(
N);
1055 RemoveNodeFromCSEMaps(
N);
1059 DeleteNodeNotInCSEMaps(
N);
1062void SelectionDAG::DeleteNodeNotInCSEMaps(
SDNode *
N) {
1063 assert(
N->getIterator() != AllNodes.begin() &&
1064 "Cannot delete the entry node!");
1065 assert(
N->use_empty() &&
"Cannot delete a node that is not dead!");
1074 assert(!(V->isVariadic() && isParameter));
1076 ByvalParmDbgValues.push_back(V);
1078 DbgValues.push_back(V);
1079 for (
const SDNode *Node : V->getSDNodes())
1081 DbgValMap[Node].push_back(V);
1086 if (
I == DbgValMap.end())
1088 for (
auto &Val:
I->second)
1089 Val->setIsInvalidated();
1093void SelectionDAG::DeallocateNode(
SDNode *
N) {
1117 switch (
N->getOpcode()) {
1123 EVT VT =
N->getValueType(0);
1124 assert(
N->getNumValues() == 1 &&
"Too many results!");
1126 "Wrong return type!");
1127 assert(
N->getNumOperands() == 2 &&
"Wrong number of operands!");
1128 assert(
N->getOperand(0).getValueType() ==
N->getOperand(1).getValueType() &&
1129 "Mismatched operand types!");
1131 "Wrong operand type!");
1133 "Wrong return type size");
1137 assert(
N->getNumValues() == 1 &&
"Too many results!");
1138 assert(
N->getValueType(0).isVector() &&
"Wrong return type!");
1139 assert(
N->getNumOperands() ==
N->getValueType(0).getVectorNumElements() &&
1140 "Wrong number of operands!");
1141 EVT EltVT =
N->getValueType(0).getVectorElementType();
1143 assert((
Op.getValueType() == EltVT ||
1144 (EltVT.
isInteger() &&
Op.getValueType().isInteger() &&
1145 EltVT.
bitsLE(
Op.getValueType()))) &&
1146 "Wrong operand type!");
1147 assert(
Op.getValueType() ==
N->getOperand(0).getValueType() &&
1148 "Operands must all have the same type");
1160void SelectionDAG::InsertNode(
SDNode *
N) {
1161 AllNodes.push_back(
N);
1163 N->PersistentId = NextPersistentId++;
1166 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1167 DUL->NodeInserted(
N);
1174bool SelectionDAG::RemoveNodeFromCSEMaps(
SDNode *
N) {
1175 bool Erased =
false;
1176 switch (
N->getOpcode()) {
1179 assert(CondCodeNodes[cast<CondCodeSDNode>(
N)->
get()] &&
1180 "Cond code doesn't exist!");
1181 Erased = CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] !=
nullptr;
1182 CondCodeNodes[cast<CondCodeSDNode>(
N)->get()] =
nullptr;
1185 Erased = ExternalSymbols.erase(cast<ExternalSymbolSDNode>(
N)->getSymbol());
1189 Erased = TargetExternalSymbols.erase(std::pair<std::string, unsigned>(
1194 auto *MCSN = cast<MCSymbolSDNode>(
N);
1195 Erased = MCSymbols.erase(MCSN->getMCSymbol());
1199 EVT VT = cast<VTSDNode>(
N)->getVT();
1201 Erased = ExtendedValueTypeNodes.erase(VT);
1212 Erased = CSEMap.RemoveNode(
N);
1219 if (!Erased &&
N->getValueType(
N->getNumValues()-1) != MVT::Glue &&
1234SelectionDAG::AddModifiedNodeToCSEMaps(
SDNode *
N) {
1238 SDNode *Existing = CSEMap.GetOrInsertNode(
N);
1239 if (Existing !=
N) {
1246 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1247 DUL->NodeDeleted(
N, Existing);
1248 DeleteNodeNotInCSEMaps(
N);
1254 for (DAGUpdateListener *DUL = UpdateListeners; DUL; DUL = DUL->Next)
1255 DUL->NodeUpdated(
N);
1273 Node->intersectFlagsWith(
N->getFlags());
1293 Node->intersectFlagsWith(
N->getFlags());
1311 Node->intersectFlagsWith(
N->getFlags());
1324 : TM(tm), OptLevel(OL), EntryNode(ISD::EntryToken, 0,
DebugLoc(),
1327 InsertNode(&EntryNode);
1338 SDAGISelPass = PassPtr;
1342 LibInfo = LibraryInfo;
1347 FnVarLocs = VarLocs;
1351 assert(!UpdateListeners &&
"Dangling registered DAGUpdateListeners");
1353 OperandRecycler.clear(OperandAllocator);
1362void SelectionDAG::allnodes_clear() {
1363 assert(&*AllNodes.begin() == &EntryNode);
1364 AllNodes.remove(AllNodes.begin());
1365 while (!AllNodes.empty())
1366 DeallocateNode(&AllNodes.front());
1368 NextPersistentId = 0;
1374 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1376 switch (
N->getOpcode()) {
1381 "debug location. Use another overload.");
1388 const SDLoc &
DL,
void *&InsertPos) {
1389 SDNode *
N = CSEMap.FindNodeOrInsertPos(
ID, InsertPos);
1391 switch (
N->getOpcode()) {
1397 if (
N->getDebugLoc() !=
DL.getDebugLoc())
1404 if (
DL.getIROrder() &&
DL.getIROrder() <
N->getIROrder())
1405 N->setDebugLoc(
DL.getDebugLoc());
1414 OperandRecycler.clear(OperandAllocator);
1415 OperandAllocator.
Reset();
1418 ExtendedValueTypeNodes.clear();
1419 ExternalSymbols.clear();
1420 TargetExternalSymbols.clear();
1423 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
nullptr);
1424 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
nullptr);
1426 EntryNode.UseList =
nullptr;
1427 InsertNode(&EntryNode);
1433 return VT.
bitsGT(
Op.getValueType())
1439std::pair<SDValue, SDValue>
1443 "Strict no-op FP extend/round not allowed.");
1450 return std::pair<SDValue, SDValue>(Res,
SDValue(Res.
getNode(), 1));
1454 return VT.
bitsGT(
Op.getValueType()) ?
1460 return VT.
bitsGT(
Op.getValueType()) ?
1466 return VT.
bitsGT(
Op.getValueType()) ?
1474 auto Type =
Op.getValueType();
1478 auto Size =
Op.getValueSizeInBits();
1489 auto Type =
Op.getValueType();
1493 auto Size =
Op.getValueSizeInBits();
1504 auto Type =
Op.getValueType();
1508 auto Size =
Op.getValueSizeInBits();
1526 EVT OpVT =
Op.getValueType();
1528 "Cannot getZeroExtendInReg FP types");
1530 "getZeroExtendInReg type should be vector iff the operand "
1534 "Vector element counts must match in getZeroExtendInReg");
1572 return getNode(ISD::VP_XOR,
DL, VT, Val, TrueValue, Mask, EVL);
1583 return getNode(ISD::VP_ZERO_EXTEND,
DL, VT,
Op, Mask, EVL);
1585 return getNode(ISD::VP_TRUNCATE,
DL, VT,
Op, Mask, EVL);
1605 bool isT,
bool isO) {
1609 "getConstant with a uint64_t value that doesn't fit in the type!");
1614 bool isT,
bool isO) {
1615 return getConstant(*ConstantInt::get(*Context, Val),
DL, VT, isT, isO);
1619 EVT VT,
bool isT,
bool isO) {
1637 Elt = ConstantInt::get(*
getContext(), NewVal);
1656 "Can only handle an even split!");
1660 for (
unsigned i = 0; i != Parts; ++i)
1662 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1663 ViaEltVT, isT, isO));
1668 unsigned ViaVecNumElts = VT.
getSizeInBits() / ViaEltSizeInBits;
1679 NewVal.
extractBits(ViaEltSizeInBits, i * ViaEltSizeInBits),
DL,
1680 ViaEltVT, isT, isO));
1685 std::reverse(EltParts.
begin(), EltParts.
end());
1704 "APInt size does not match type size!");
1713 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1718 N = newSDNode<ConstantSDNode>(isT, isO, Elt, VTs);
1719 CSEMap.InsertNode(
N, IP);
1736 const SDLoc &
DL,
bool LegalTypes) {
1743 const SDLoc &
DL,
bool LegalTypes) {
1759 EVT VT,
bool isTarget) {
1774 if ((
N = FindNodeOrInsertPos(
ID,
DL, IP)))
1779 N = newSDNode<ConstantFPSDNode>(isTarget, &V, VTs);
1780 CSEMap.InsertNode(
N, IP);
1794 if (EltVT == MVT::f32)
1796 if (EltVT == MVT::f64)
1798 if (EltVT == MVT::f80 || EltVT == MVT::f128 || EltVT == MVT::ppcf128 ||
1799 EltVT == MVT::f16 || EltVT == MVT::bf16) {
1810 EVT VT, int64_t
Offset,
bool isTargetGA,
1811 unsigned TargetFlags) {
1812 assert((TargetFlags == 0 || isTargetGA) &&
1813 "Cannot set target flags on target-independent globals");
1831 ID.AddInteger(TargetFlags);
1833 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
1836 auto *
N = newSDNode<GlobalAddressSDNode>(
1837 Opc,
DL.getIROrder(),
DL.getDebugLoc(), GV, VTs,
Offset, TargetFlags);
1838 CSEMap.InsertNode(
N, IP);
1850 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1853 auto *
N = newSDNode<FrameIndexSDNode>(FI, VTs, isTarget);
1854 CSEMap.InsertNode(
N, IP);
1860 unsigned TargetFlags) {
1861 assert((TargetFlags == 0 || isTarget) &&
1862 "Cannot set target flags on target-independent jump tables");
1868 ID.AddInteger(TargetFlags);
1870 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1873 auto *
N = newSDNode<JumpTableSDNode>(JTI, VTs, isTarget, TargetFlags);
1874 CSEMap.InsertNode(
N, IP);
1888 bool isTarget,
unsigned TargetFlags) {
1889 assert((TargetFlags == 0 || isTarget) &&
1890 "Cannot set target flags on target-independent globals");
1899 ID.AddInteger(Alignment->value());
1902 ID.AddInteger(TargetFlags);
1904 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1907 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
1909 CSEMap.InsertNode(
N, IP);
1918 bool isTarget,
unsigned TargetFlags) {
1919 assert((TargetFlags == 0 || isTarget) &&
1920 "Cannot set target flags on target-independent globals");
1927 ID.AddInteger(Alignment->value());
1929 C->addSelectionDAGCSEId(
ID);
1930 ID.AddInteger(TargetFlags);
1932 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1935 auto *
N = newSDNode<ConstantPoolSDNode>(isTarget,
C, VTs,
Offset, *Alignment,
1937 CSEMap.InsertNode(
N, IP);
1947 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
1950 auto *
N = newSDNode<BasicBlockSDNode>(
MBB);
1951 CSEMap.InsertNode(
N, IP);
1958 ValueTypeNodes.size())
1965 N = newSDNode<VTSDNode>(VT);
1973 N = newSDNode<ExternalSymbolSDNode>(
false,
Sym, 0,
getVTList(VT));
1988 unsigned TargetFlags) {
1990 TargetExternalSymbols[std::pair<std::string, unsigned>(
Sym, TargetFlags)];
1992 N = newSDNode<ExternalSymbolSDNode>(
true,
Sym, TargetFlags,
getVTList(VT));
1998 if ((
unsigned)
Cond >= CondCodeNodes.size())
1999 CondCodeNodes.resize(
Cond+1);
2001 if (!CondCodeNodes[
Cond]) {
2002 auto *
N = newSDNode<CondCodeSDNode>(
Cond);
2003 CondCodeNodes[
Cond] =
N;
2013 "APInt size does not match type size!");
2031 if (EC.isScalable())
2044 const APInt &StepVal) {
2068 "Must have the same number of vector elements as mask elements!");
2070 "Invalid VECTOR_SHUFFLE");
2078 int NElts = Mask.size();
2080 [&](
int M) {
return M < (NElts * 2) && M >= -1; }) &&
2081 "Index out of range");
2089 for (
int i = 0; i != NElts; ++i)
2090 if (MaskVec[i] >= NElts) MaskVec[i] -= NElts;
2106 for (
int i = 0; i < NElts; ++i) {
2107 if (MaskVec[i] <
Offset || MaskVec[i] >= (
Offset + NElts))
2111 if (UndefElements[MaskVec[i] -
Offset]) {
2117 if (!UndefElements[i])
2121 if (
auto *N1BV = dyn_cast<BuildVectorSDNode>(N1))
2122 BlendSplat(N1BV, 0);
2123 if (
auto *N2BV = dyn_cast<BuildVectorSDNode>(N2))
2124 BlendSplat(N2BV, NElts);
2129 bool AllLHS =
true, AllRHS =
true;
2131 for (
int i = 0; i != NElts; ++i) {
2132 if (MaskVec[i] >= NElts) {
2137 }
else if (MaskVec[i] >= 0) {
2141 if (AllLHS && AllRHS)
2143 if (AllLHS && !N2Undef)
2156 bool Identity =
true, AllSame =
true;
2157 for (
int i = 0; i != NElts; ++i) {
2158 if (MaskVec[i] >= 0 && MaskVec[i] != i) Identity =
false;
2159 if (MaskVec[i] != MaskVec[0]) AllSame =
false;
2161 if (Identity && NElts)
2171 V = V->getOperand(0);
2174 if (
auto *BV = dyn_cast<BuildVectorSDNode>(V)) {
2194 if (AllSame && SameNumElts) {
2195 EVT BuildVT = BV->getValueType(0);
2212 for (
int i = 0; i != NElts; ++i)
2213 ID.AddInteger(MaskVec[i]);
2216 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2222 int *MaskAlloc = OperandAllocator.
Allocate<
int>(NElts);
2225 auto *
N = newSDNode<ShuffleVectorSDNode>(VTs, dl.
getIROrder(),
2227 createOperands(
N, Ops);
2229 CSEMap.InsertNode(
N, IP);
2250 ID.AddInteger(RegNo);
2252 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2255 auto *
N = newSDNode<RegisterSDNode>(RegNo, VTs);
2257 CSEMap.InsertNode(
N, IP);
2265 ID.AddPointer(RegMask);
2267 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2270 auto *
N = newSDNode<RegisterMaskSDNode>(RegMask);
2271 CSEMap.InsertNode(
N, IP);
2286 ID.AddPointer(Label);
2288 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2293 createOperands(
N, Ops);
2295 CSEMap.InsertNode(
N, IP);
2301 int64_t
Offset,
bool isTarget,
2302 unsigned TargetFlags) {
2310 ID.AddInteger(TargetFlags);
2312 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2315 auto *
N = newSDNode<BlockAddressSDNode>(Opc, VTs, BA,
Offset, TargetFlags);
2316 CSEMap.InsertNode(
N, IP);
2327 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2330 auto *
N = newSDNode<SrcValueSDNode>(V);
2331 CSEMap.InsertNode(
N, IP);
2342 if (
SDNode *E = FindNodeOrInsertPos(
ID, IP))
2345 auto *
N = newSDNode<MDNodeSDNode>(MD);
2346 CSEMap.InsertNode(
N, IP);
2352 if (VT == V.getValueType())
2359 unsigned SrcAS,
unsigned DestAS) {
2364 ID.AddInteger(SrcAS);
2365 ID.AddInteger(DestAS);
2368 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
2372 VTs, SrcAS, DestAS);
2373 createOperands(
N, Ops);
2375 CSEMap.InsertNode(
N, IP);
2387 EVT OpTy =
Op.getValueType();
2389 if (OpTy == ShTy || OpTy.
isVector())
return Op;
2397 const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
2398 EVT VT = Node->getValueType(0);
2399 SDValue Tmp1 = Node->getOperand(0);
2400 SDValue Tmp2 = Node->getOperand(1);
2401 const MaybeAlign MA(Node->getConstantOperandVal(3));
2433 const Value *VD = cast<SrcValueSDNode>(Node->getOperand(3))->getValue();
2434 const Value *VS = cast<SrcValueSDNode>(Node->getOperand(4))->getValue();
2445 Align RedAlign = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2455 if (RedAlign > StackAlign) {
2458 unsigned NumIntermediates;
2460 NumIntermediates, RegisterVT);
2462 Align RedAlign2 = UseABI ?
DL.getABITypeAlign(Ty) :
DL.getPrefTypeAlign(Ty);
2463 if (RedAlign2 < RedAlign)
2464 RedAlign = RedAlign2;
2479 false,
nullptr, StackID);
2494 "Don't know how to choose the maximum size when creating a stack "
2503 Align Align = std::max(
DL.getPrefTypeAlign(Ty1),
DL.getPrefTypeAlign(Ty2));
2511 auto GetUndefBooleanConstant = [&]() {
2550 return GetUndefBooleanConstant();
2555 return GetUndefBooleanConstant();
2564 const APInt &C2 = N2C->getAPIntValue();
2566 const APInt &C1 = N1C->getAPIntValue();
2573 auto *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
2574 auto *N2CFP = dyn_cast<ConstantFPSDNode>(N2);
2576 if (N1CFP && N2CFP) {
2581 return GetUndefBooleanConstant();
2586 return GetUndefBooleanConstant();
2592 return GetUndefBooleanConstant();
2597 return GetUndefBooleanConstant();
2602 return GetUndefBooleanConstant();
2608 return GetUndefBooleanConstant();
2637 return getSetCC(dl, VT, N2, N1, SwappedCond);
2638 }
else if ((N2CFP && N2CFP->getValueAPF().isNaN()) ||
2653 return GetUndefBooleanConstant();
2664 unsigned BitWidth =
Op.getScalarValueSizeInBits();
2672 unsigned Depth)
const {
2680 const APInt &DemandedElts,
2681 unsigned Depth)
const {
2688 unsigned Depth )
const {
2694 unsigned Depth)
const {
2699 const APInt &DemandedElts,
2700 unsigned Depth)
const {
2701 EVT VT =
Op.getValueType();
2708 for (
unsigned EltIdx = 0; EltIdx != NumElts; ++EltIdx) {
2709 if (!DemandedElts[EltIdx])
2713 KnownZeroElements.
setBit(EltIdx);
2715 return KnownZeroElements;
2725 unsigned Opcode = V.getOpcode();
2726 EVT VT = V.getValueType();
2729 "scalable demanded bits are ignored");
2741 UndefElts = V.getOperand(0).isUndef()
2750 APInt UndefLHS, UndefRHS;
2755 UndefElts = UndefLHS | UndefRHS;
2785 for (
unsigned i = 0; i != NumElts; ++i) {
2791 if (!DemandedElts[i])
2793 if (Scl && Scl !=
Op)
2803 ArrayRef<int> Mask = cast<ShuffleVectorSDNode>(V)->getMask();
2804 for (
int i = 0; i != (int)NumElts; ++i) {
2810 if (!DemandedElts[i])
2812 if (M < (
int)NumElts)
2815 DemandedRHS.
setBit(M - NumElts);
2827 auto CheckSplatSrc = [&](
SDValue Src,
const APInt &SrcElts) {
2829 return (SrcElts.popcount() == 1) ||
2831 (SrcElts & SrcUndefs).
isZero());
2833 if (!DemandedLHS.
isZero())
2834 return CheckSplatSrc(V.getOperand(0), DemandedLHS);
2835 return CheckSplatSrc(V.getOperand(1), DemandedRHS);
2839 SDValue Src = V.getOperand(0);
2841 if (Src.getValueType().isScalableVector())
2844 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2857 SDValue Src = V.getOperand(0);
2859 if (Src.getValueType().isScalableVector())
2861 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
2863 APInt DemandedSrcElts = DemandedElts.
zext(NumSrcElts);
2865 UndefElts = UndefSrcElts.
trunc(NumElts);
2871 SDValue Src = V.getOperand(0);
2872 EVT SrcVT = Src.getValueType();
2882 if ((
BitWidth % SrcBitWidth) == 0) {
2884 unsigned Scale =
BitWidth / SrcBitWidth;
2886 APInt ScaledDemandedElts =
2888 for (
unsigned I = 0;
I != Scale; ++
I) {
2892 SubDemandedElts &= ScaledDemandedElts;
2896 if (!SubUndefElts.
isZero())
2910 EVT VT = V.getValueType();
2920 (AllowUndefs || !UndefElts);
2926 EVT VT = V.getValueType();
2927 unsigned Opcode = V.getOpcode();
2948 SplatIdx = (UndefElts & DemandedElts).
countr_one();
2962 auto *SVN = cast<ShuffleVectorSDNode>(V);
2963 if (!SVN->isSplat())
2965 int Idx = SVN->getSplatIndex();
2966 int NumElts = V.getValueType().getVectorNumElements();
2967 SplatIdx =
Idx % NumElts;
2968 return V.getOperand(
Idx / NumElts);
2984 if (LegalSVT.
bitsLT(SVT))
2995 const APInt &DemandedElts)
const {
2998 "Unknown shift node");
2999 unsigned BitWidth = V.getScalarValueSizeInBits();
3002 const APInt &ShAmt = SA->getAPIntValue();
3010 EVT VT = V.getValueType();
3021 "Unknown shift node");
3024 unsigned BitWidth = V.getScalarValueSizeInBits();
3025 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3028 const APInt *MinShAmt =
nullptr;
3029 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3030 if (!DemandedElts[i])
3032 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3036 const APInt &ShAmt = SA->getAPIntValue();
3039 if (MinShAmt && MinShAmt->
ule(ShAmt))
3047 EVT VT = V.getValueType();
3058 "Unknown shift node");
3061 unsigned BitWidth = V.getScalarValueSizeInBits();
3062 auto *BV = dyn_cast<BuildVectorSDNode>(V.getOperand(1));
3065 const APInt *MaxShAmt =
nullptr;
3066 for (
unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
3067 if (!DemandedElts[i])
3069 auto *SA = dyn_cast<ConstantSDNode>(BV->getOperand(i));
3073 const APInt &ShAmt = SA->getAPIntValue();
3076 if (MaxShAmt && MaxShAmt->
uge(ShAmt))
3084 EVT VT = V.getValueType();
3095 EVT VT =
Op.getValueType();
3110 unsigned Depth)
const {
3111 unsigned BitWidth =
Op.getScalarValueSizeInBits();
3115 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
3119 if (
auto *
C = dyn_cast<ConstantFPSDNode>(
Op)) {
3129 assert((!
Op.getValueType().isFixedLengthVector() ||
3130 NumElts ==
Op.getValueType().getVectorNumElements()) &&
3131 "Unexpected vector size");
3136 unsigned Opcode =
Op.getOpcode();
3144 "Expected SPLAT_VECTOR implicit truncation");
3151 unsigned ScalarSize =
Op.getOperand(0).getScalarValueSizeInBits();
3153 "Expected SPLAT_VECTOR_PARTS scalars to cover element width");
3160 const APInt &Step =
Op.getConstantOperandAPInt(0);
3169 const APInt MinNumElts =
3175 .
umul_ov(MinNumElts, Overflow);
3179 const APInt MaxValue = (MaxNumElts - 1).
umul_ov(Step, Overflow);
3187 assert(!
Op.getValueType().isScalableVector());
3191 if (!DemandedElts[i])
3200 "Expected BUILD_VECTOR implicit truncation");
3213 assert(!
Op.getValueType().isScalableVector());
3216 APInt DemandedLHS, DemandedRHS;
3220 DemandedLHS, DemandedRHS))
3225 if (!!DemandedLHS) {
3233 if (!!DemandedRHS) {
3242 const APInt &Multiplier =
Op.getConstantOperandAPInt(0);
3247 if (
Op.getValueType().isScalableVector())
3251 EVT SubVectorVT =
Op.getOperand(0).getValueType();
3254 for (
unsigned i = 0; i != NumSubVectors; ++i) {
3256 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
3257 if (!!DemandedSub) {
3269 if (
Op.getValueType().isScalableVector())
3278 APInt DemandedSrcElts = DemandedElts;
3283 if (!!DemandedSubElts) {
3288 if (!!DemandedSrcElts) {
3298 if (
Op.getValueType().isScalableVector() || Src.getValueType().isScalableVector())
3301 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
3307 if (
Op.getValueType().isScalableVector())
3311 if (DemandedElts != 1)
3322 if (
Op.getValueType().isScalableVector())
3342 if ((
BitWidth % SubBitWidth) == 0) {
3349 unsigned SubScale =
BitWidth / SubBitWidth;
3350 APInt SubDemandedElts(NumElts * SubScale, 0);
3351 for (
unsigned i = 0; i != NumElts; ++i)
3352 if (DemandedElts[i])
3353 SubDemandedElts.
setBit(i * SubScale);
3355 for (
unsigned i = 0; i != SubScale; ++i) {
3358 unsigned Shifts = IsLE ? i : SubScale - 1 - i;
3359 Known.
insertBits(Known2, SubBitWidth * Shifts);
3364 if ((SubBitWidth %
BitWidth) == 0) {
3365 assert(
Op.getValueType().isVector() &&
"Expected bitcast to vector");
3370 unsigned SubScale = SubBitWidth /
BitWidth;
3371 APInt SubDemandedElts =
3376 for (
unsigned i = 0; i != NumElts; ++i)
3377 if (DemandedElts[i]) {
3378 unsigned Shifts = IsLE ? i : NumElts - 1 - i;
3409 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3413 Op.getOperand(0), DemandedElts,
false,
Depth + 1);
3419 if (
Op->getFlags().hasNoSignedWrap() &&
3420 Op.getOperand(0) ==
Op.getOperand(1) &&
3450 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3453 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3454 if (
Op.getResNo() == 0)
3461 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3464 bool SelfMultiply =
Op.getOperand(0) ==
Op.getOperand(1);
3465 if (
Op.getResNo() == 0)
3509 if (
Op.getResNo() != 1)
3524 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
3536 bool NUW =
Op->getFlags().hasNoUnsignedWrap();
3537 bool NSW =
Op->getFlags().hasNoSignedWrap();
3544 if (
const APInt *ShMinAmt =
3553 Op->getFlags().hasExact());
3556 if (
const APInt *ShMinAmt =
3564 Op->getFlags().hasExact());
3569 unsigned Amt =
C->getAPIntValue().urem(
BitWidth);
3575 DemandedElts,
Depth + 1);
3600 assert((
Op.getResNo() == 0 ||
Op.getResNo() == 1) &&
"Unknown result");
3603 unsigned LoBits =
Op.getOperand(0).getScalarValueSizeInBits();
3604 unsigned HiBits =
Op.getOperand(1).getScalarValueSizeInBits();
3607 Known = Known2.
concat(Known);
3621 if (
Op.getResNo() == 0)
3629 EVT EVT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3670 !
Op.getValueType().isScalableVector()) {
3684 for (
unsigned i = 0; i != NumElts; ++i) {
3685 if (!DemandedElts[i])
3688 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
3694 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
3695 APInt Value = CFP->getValueAPF().bitcastToAPInt();
3706 if (
auto *CInt = dyn_cast<ConstantInt>(Cst)) {
3708 }
else if (
auto *CFP = dyn_cast<ConstantFP>(Cst)) {
3714 }
else if (
Op.getResNo() == 0) {
3715 KnownBits Known0(!LD->getMemoryVT().isScalableVT()
3716 ? LD->getMemoryVT().getFixedSizeInBits()
3718 EVT VT =
Op.getValueType();
3725 if (
const MDNode *MD = LD->getRanges()) {
3736 if (LD->getMemoryVT().isVector())
3737 Known0 = Known0.
trunc(LD->getMemoryVT().getScalarSizeInBits());
3754 if (
Op.getValueType().isScalableVector())
3756 EVT InVT =
Op.getOperand(0).getValueType();
3768 if (
Op.getValueType().isScalableVector())
3770 EVT InVT =
Op.getOperand(0).getValueType();
3786 if (
Op.getValueType().isScalableVector())
3788 EVT InVT =
Op.getOperand(0).getValueType();
3805 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
3808 Known.
Zero |= (~InMask);
3809 Known.
One &= (~Known.Zero);
3813 unsigned LogOfAlign =
Log2(cast<AssertAlignSDNode>(
Op)->
getAlign());
3833 Op.getOpcode() ==
ISD::ADD, Flags.hasNoSignedWrap(),
3834 Flags.hasNoUnsignedWrap(), Known, Known2);
3841 if (
Op.getResNo() == 1) {
3852 "We only compute knownbits for the difference here.");
3859 Borrow = Borrow.
trunc(1);
3873 if (
Op.getResNo() == 1) {
3884 assert(
Op.getResNo() == 0 &&
"We only compute knownbits for the sum here.");
3894 Carry = Carry.
trunc(1);
3930 const unsigned Index =
Op.getConstantOperandVal(1);
3931 const unsigned EltBitWidth =
Op.getValueSizeInBits();
3938 Known = Known.
trunc(EltBitWidth);
3954 Known = Known.
trunc(EltBitWidth);
3959 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
3960 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
3970 if (
Op.getValueType().isScalableVector())
3979 bool DemandedVal =
true;
3980 APInt DemandedVecElts = DemandedElts;
3981 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
3982 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
3983 unsigned EltIdx = CEltNo->getZExtValue();
3984 DemandedVal = !!DemandedElts[EltIdx];
3993 if (!!DemandedVecElts) {
4011 Known = Known2.
abs();
4042 if (CstLow && CstHigh) {
4047 const APInt &ValueHigh = CstHigh->getAPIntValue();
4048 if (ValueLow.
sle(ValueHigh)) {
4051 unsigned MinSignBits = std::min(LowSignBits, HighSignBits);
4074 if (IsMax && CstLow) {
4098 EVT VT = cast<VTSDNode>(
Op.getOperand(1))->getVT();
4103 if (
Op.getResNo() == 1) {
4130 cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4132 if (
Op.getResNo() == 0) {
4156 if (
Op.getValueType().isScalableVector())
4303 return C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2();
4311 if (
C &&
C->getAPIntValue() == 1)
4321 if (
C &&
C->getAPIntValue().isSignMask())
4333 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(E))
4334 return C->getAPIntValue().zextOrTrunc(BitWidth).isPowerOf2();
4342 if (
C->getAPIntValue().zextOrTrunc(
BitWidth).isPowerOf2())
4380 return C1->getValueAPF().getExactLog2Abs() >= 0;
4389 EVT VT =
Op.getValueType();
4401 unsigned Depth)
const {
4402 EVT VT =
Op.getValueType();
4407 unsigned FirstAnswer = 1;
4409 if (
auto *
C = dyn_cast<ConstantSDNode>(
Op)) {
4410 const APInt &Val =
C->getAPIntValue();
4420 unsigned Opcode =
Op.getOpcode();
4424 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4425 return VTBits-Tmp+1;
4427 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getSizeInBits();
4434 unsigned NumSrcBits =
Op.getOperand(0).getValueSizeInBits();
4436 if (NumSrcSignBits > (NumSrcBits - VTBits))
4437 return NumSrcSignBits - (NumSrcBits - VTBits);
4444 if (!DemandedElts[i])
4451 APInt T =
C->getAPIntValue().trunc(VTBits);
4452 Tmp2 =
T.getNumSignBits();
4456 if (
SrcOp.getValueSizeInBits() != VTBits) {
4458 "Expected BUILD_VECTOR implicit truncation");
4459 unsigned ExtraBits =
SrcOp.getValueSizeInBits() - VTBits;
4460 Tmp2 = (Tmp2 > ExtraBits ? Tmp2 - ExtraBits : 1);
4463 Tmp = std::min(Tmp, Tmp2);
4470 APInt DemandedLHS, DemandedRHS;
4474 DemandedLHS, DemandedRHS))
4477 Tmp = std::numeric_limits<unsigned>::max();
4480 if (!!DemandedRHS) {
4482 Tmp = std::min(Tmp, Tmp2);
4487 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4503 if (VTBits == SrcBits)
4509 if ((SrcBits % VTBits) == 0) {
4512 unsigned Scale = SrcBits / VTBits;
4513 APInt SrcDemandedElts =
4523 for (
unsigned i = 0; i != NumElts; ++i)
4524 if (DemandedElts[i]) {
4525 unsigned SubOffset = i % Scale;
4526 SubOffset = (IsLE ? ((Scale - 1) - SubOffset) : SubOffset);
4527 SubOffset = SubOffset * VTBits;
4528 if (Tmp <= SubOffset)
4530 Tmp2 = std::min(Tmp2, Tmp - SubOffset);
4539 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4540 return VTBits - Tmp + 1;
4542 Tmp = VTBits -
Op.getOperand(0).getScalarValueSizeInBits();
4546 Tmp = cast<VTSDNode>(
Op.getOperand(1))->getVT().getScalarSizeInBits();
4549 return std::max(Tmp, Tmp2);
4554 EVT SrcVT = Src.getValueType();
4562 if (
const APInt *ShAmt =
4564 Tmp = std::min<uint64_t>(Tmp + ShAmt->getZExtValue(), VTBits);
4567 if (
const APInt *ShAmt =
4571 if (ShAmt->ult(Tmp))
4572 return Tmp - ShAmt->getZExtValue();
4582 FirstAnswer = std::min(Tmp, Tmp2);
4592 if (Tmp == 1)
return 1;
4594 return std::min(Tmp, Tmp2);
4597 if (Tmp == 1)
return 1;
4599 return std::min(Tmp, Tmp2);
4611 if (CstLow && CstHigh) {
4616 Tmp2 = CstHigh->getAPIntValue().getNumSignBits();
4617 return std::min(Tmp, Tmp2);
4626 return std::min(Tmp, Tmp2);
4634 return std::min(Tmp, Tmp2);
4645 if (
Op.getResNo() != 1)
4659 unsigned OpNo =
Op->isStrictFPOpcode() ? 1 : 0;
4676 unsigned RotAmt =
C->getAPIntValue().urem(VTBits);
4680 RotAmt = (VTBits - RotAmt) % VTBits;
4684 if (Tmp > (RotAmt + 1))
return (Tmp - RotAmt);
4692 if (Tmp == 1)
return 1;
4697 if (CRHS->isAllOnes()) {
4703 if ((Known.
Zero | 1).isAllOnes())
4713 if (Tmp2 == 1)
return 1;
4714 return std::min(Tmp, Tmp2) - 1;
4717 if (Tmp2 == 1)
return 1;
4722 if (CLHS->isZero()) {
4727 if ((Known.
Zero | 1).isAllOnes())
4741 if (Tmp == 1)
return 1;
4742 return std::min(Tmp, Tmp2) - 1;
4746 if (SignBitsOp0 == 1)
4749 if (SignBitsOp1 == 1)
4751 unsigned OutValidBits =
4752 (VTBits - SignBitsOp0 + 1) + (VTBits - SignBitsOp1 + 1);
4753 return OutValidBits > VTBits ? 1 : VTBits - OutValidBits + 1;
4763 unsigned NumSrcBits =
Op.getOperand(0).getScalarValueSizeInBits();
4765 if (NumSrcSignBits > (NumSrcBits - VTBits))
4766 return NumSrcSignBits - (NumSrcBits - VTBits);
4773 const int BitWidth =
Op.getValueSizeInBits();
4774 const int Items =
Op.getOperand(0).getValueSizeInBits() /
BitWidth;
4778 const int rIndex = Items - 1 -
Op.getConstantOperandVal(1);
4793 bool DemandedVal =
true;
4794 APInt DemandedVecElts = DemandedElts;
4795 auto *CEltNo = dyn_cast<ConstantSDNode>(EltNo);
4796 if (CEltNo && CEltNo->getAPIntValue().ult(NumElts)) {
4797 unsigned EltIdx = CEltNo->getZExtValue();
4798 DemandedVal = !!DemandedElts[EltIdx];
4801 Tmp = std::numeric_limits<unsigned>::max();
4807 Tmp = std::min(Tmp, Tmp2);
4809 if (!!DemandedVecElts) {
4811 Tmp = std::min(Tmp, Tmp2);
4813 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4824 const unsigned BitWidth =
Op.getValueSizeInBits();
4825 const unsigned EltBitWidth =
Op.getOperand(0).getScalarValueSizeInBits();
4837 auto *ConstEltNo = dyn_cast<ConstantSDNode>(EltNo);
4838 if (ConstEltNo && ConstEltNo->getAPIntValue().ult(NumSrcElts))
4848 if (Src.getValueType().isScalableVector())
4851 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
4860 Tmp = std::numeric_limits<unsigned>::max();
4861 EVT SubVectorVT =
Op.getOperand(0).getValueType();
4864 for (
unsigned i = 0; (i < NumSubVectors) && (Tmp > 1); ++i) {
4866 DemandedElts.
extractBits(NumSubVectorElts, i * NumSubVectorElts);
4870 Tmp = std::min(Tmp, Tmp2);
4872 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4885 APInt DemandedSrcElts = DemandedElts;
4888 Tmp = std::numeric_limits<unsigned>::max();
4889 if (!!DemandedSubElts) {
4894 if (!!DemandedSrcElts) {
4896 Tmp = std::min(Tmp, Tmp2);
4898 assert(Tmp <= VTBits &&
"Failed to determine minimum sign bits");
4903 if (
const MDNode *Ranges = LD->getRanges()) {
4904 if (DemandedElts != 1)
4909 switch (LD->getExtensionType()) {
4944 Tmp = cast<AtomicSDNode>(
Op)->getMemoryVT().getScalarSizeInBits();
4946 if (
Op.getResNo() == 0) {
4950 return VTBits - Tmp + 1;
4952 return VTBits - Tmp;
4956 return VTBits - Tmp + 1;
4958 return VTBits - Tmp;
4966 if (
Op.getResNo() == 0) {
4969 unsigned ExtType = LD->getExtensionType();
4973 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4974 return VTBits - Tmp + 1;
4976 Tmp = LD->getMemoryVT().getScalarSizeInBits();
4977 return VTBits - Tmp;
4982 Type *CstTy = Cst->getType();
4987 for (
unsigned i = 0; i != NumElts; ++i) {
4988 if (!DemandedElts[i])
4991 if (
auto *CInt = dyn_cast<ConstantInt>(Elt)) {
4993 Tmp = std::min(Tmp,
Value.getNumSignBits());
4996 if (
auto *CFP = dyn_cast<ConstantFP>(Elt)) {
4997 APInt Value = CFP->getValueAPF().bitcastToAPInt();
4998 Tmp = std::min(Tmp,
Value.getNumSignBits());
5024 FirstAnswer = std::max(FirstAnswer, NumBits);
5035 unsigned Depth)
const {
5037 return Op.getScalarValueSizeInBits() - SignBits + 1;
5041 const APInt &DemandedElts,
5042 unsigned Depth)
const {
5044 return Op.getScalarValueSizeInBits() - SignBits + 1;
5048 unsigned Depth)
const {
5054 EVT VT =
Op.getValueType();
5065 const APInt &DemandedElts,
5067 unsigned Depth)
const {
5068 unsigned Opcode =
Op.getOpcode();
5095 if (!DemandedElts[i])
5104 APInt DemandedLHS, DemandedRHS;
5105 auto *SVN = cast<ShuffleVectorSDNode>(
Op);
5107 DemandedElts, DemandedLHS, DemandedRHS,
5110 if (!DemandedLHS.
isZero() &&
5114 if (!DemandedRHS.
isZero() &&
5142 return isGuaranteedNotToBeUndefOrPoison(V, PoisonOnly, Depth + 1);
5148 unsigned Depth)
const {
5150 EVT VT =
Op.getValueType();
5163 unsigned Depth)
const {
5165 EVT VT =
Op.getValueType();
5169 if (ConsiderFlags &&
Op->hasPoisonGeneratingFlags())
5172 unsigned Opcode =
Op.getOpcode();
5210 if (
Op.getOperand(0).getValueType().isInteger())
5217 unsigned CCOp = Opcode ==
ISD::SETCC ? 2 : 4;
5218 ISD::CondCode CCCode = cast<CondCodeSDNode>(
Op.getOperand(CCOp))->get();
5219 if (((
unsigned)CCCode & 0x10U))
5246 EVT VecVT =
Op.getOperand(0).getValueType();
5253 EVT VecVT =
Op.getOperand(0).getValueType();
5260 auto *SVN = cast<ShuffleVectorSDNode>(
Op);
5262 if (Elt < 0 && DemandedElts[
Idx])
5281 unsigned Opcode =
Op.getOpcode();
5283 return Op->getFlags().hasDisjoint() ||
5305 return !
C->getValueAPF().isNaN() ||
5306 (SNaN && !
C->getValueAPF().isSignaling());
5309 unsigned Opcode =
Op.getOpcode();
5417 assert(
Op.getValueType().isFloatingPoint() &&
5418 "Floating point type expected");
5429 assert(!
Op.getValueType().isFloatingPoint() &&
5430 "Floating point types unsupported - use isKnownNeverZeroFloat");
5439 switch (
Op.getOpcode()) {
5453 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5457 if (ValKnown.
One[0])
5517 if (
Op->getFlags().hasExact())
5533 if (
Op->getFlags().hasExact())
5538 if (
Op->getFlags().hasNoUnsignedWrap())
5549 std::optional<bool> ne =
5556 if (
Op->getFlags().hasNoSignedWrap() ||
Op->getFlags().hasNoUnsignedWrap())
5572 return !C1->isNegative();
5579 if (
A ==
B)
return true;
5584 if (CA->isZero() && CB->isZero())
return true;
5593 return V.getOperand(0);
5600 SDValue ExtArg = V.getOperand(0);
5619 NotOperand = NotOperand->getOperand(0);
5621 if (
Other == NotOperand)
5624 return NotOperand ==
Other->getOperand(0) ||
5625 NotOperand ==
Other->getOperand(1);
5631 A =
A->getOperand(0);
5634 B =
B->getOperand(0);
5637 return MatchNoCommonBitsPattern(
A->getOperand(0),
A->getOperand(1),
B) ||
5638 MatchNoCommonBitsPattern(
A->getOperand(1),
A->getOperand(0),
B);
5644 assert(
A.getValueType() ==
B.getValueType() &&
5645 "Values must have the same type");
5655 if (cast<ConstantSDNode>(Step)->
isZero())
5664 int NumOps = Ops.
size();
5665 assert(NumOps != 0 &&
"Can't build an empty vector!");
5667 "BUILD_VECTOR cannot be used with scalable types");
5669 "Incorrect element count in BUILD_VECTOR!");
5677 bool IsIdentity =
true;
5678 for (
int i = 0; i != NumOps; ++i) {
5680 Ops[i].getOperand(0).getValueType() != VT ||
5681 (IdentitySrc && Ops[i].getOperand(0) != IdentitySrc) ||
5682 !isa<ConstantSDNode>(Ops[i].getOperand(1)) ||
5683 Ops[i].getConstantOperandAPInt(1) != i) {
5687 IdentitySrc = Ops[i].getOperand(0);
5700 assert(!Ops.
empty() &&
"Can't concatenate an empty list of vectors!");
5703 return Ops[0].getValueType() ==
Op.getValueType();
5705 "Concatenation of vectors with inconsistent value types!");
5706 assert((Ops[0].getValueType().getVectorElementCount() * Ops.
size()) ==
5708 "Incorrect element count in vector concatenation!");
5710 if (Ops.
size() == 1)
5721 bool IsIdentity =
true;
5722 for (
unsigned i = 0, e = Ops.
size(); i != e; ++i) {
5724 unsigned IdentityIndex = i *
Op.getValueType().getVectorMinNumElements();
5726 Op.getOperand(0).getValueType() != VT ||
5727 (IdentitySrc &&
Op.getOperand(0) != IdentitySrc) ||
5728 Op.getConstantOperandVal(1) != IdentityIndex) {
5732 assert((!IdentitySrc || IdentitySrc ==
Op.getOperand(0)) &&
5733 "Unexpected identity source vector for concat of extracts");
5734 IdentitySrc =
Op.getOperand(0);
5737 assert(IdentitySrc &&
"Failed to set source vector of extracts");
5752 EVT OpVT =
Op.getValueType();
5764 SVT = (SVT.
bitsLT(
Op.getValueType()) ?
Op.getValueType() : SVT);
5788 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
5791 auto *
N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
5792 CSEMap.InsertNode(
N, IP);
5805 return getNode(Opcode,
DL, VT, N1, Flags);
5856 "STEP_VECTOR can only be used with scalable types");
5859 "Unexpected step operand");
5881 "Invalid FP cast!");
5885 "Vector element count mismatch!");
5903 "Invalid SIGN_EXTEND!");
5905 "SIGN_EXTEND result type type should be vector iff the operand "
5910 "Vector element count mismatch!");
5924 "Invalid ZERO_EXTEND!");
5926 "ZERO_EXTEND result type type should be vector iff the operand "
5931 "Vector element count mismatch!");
5962 "Invalid ANY_EXTEND!");
5964 "ANY_EXTEND result type type should be vector iff the operand "
5969 "Vector element count mismatch!");
5994 "Invalid TRUNCATE!");
5996 "TRUNCATE result type type should be vector iff the operand "
6001 "Vector element count mismatch!");
6024 assert(VT.
isVector() &&
"This DAG node is restricted to vector types.");
6026 "The input must be the same size or smaller than the result.");
6029 "The destination vector type must have fewer lanes than the input.");
6039 "BSWAP types must be a multiple of 16 bits!");
6053 "Cannot BITCAST between types of different sizes!");
6066 "Illegal SCALAR_TO_VECTOR node!");
6123 "Wrong operand type!");
6130 if (VT != MVT::Glue) {
6134 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
6135 E->intersectFlagsWith(Flags);
6139 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6141 createOperands(
N, Ops);
6142 CSEMap.InsertNode(
N, IP);
6144 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
6145 createOperands(
N, Ops);
6179 if (!C2.getBoolValue())
6183 if (!C2.getBoolValue())
6187 if (!C2.getBoolValue())
6191 if (!C2.getBoolValue())
6211 return std::nullopt;
6216 bool IsUndef1,
const APInt &C2,
6218 if (!(IsUndef1 || IsUndef2))
6226 return std::nullopt;
6236 auto *C2 = dyn_cast<ConstantSDNode>(N2);
6239 int64_t
Offset = C2->getSExtValue();
6257 assert(Ops.
size() == 2 &&
"Div/rem should have 2 operands");
6264 [](
SDValue V) { return V.isUndef() ||
6265 isNullConstant(V); });
6285 unsigned NumOps = Ops.
size();
6301 if (
auto *
C = dyn_cast<ConstantSDNode>(N1)) {
6302 const APInt &Val =
C->getAPIntValue();
6306 C->isTargetOpcode(),
C->isOpaque());
6313 C->isTargetOpcode(),
C->isOpaque());
6318 C->isTargetOpcode(),
C->isOpaque());
6320 C->isTargetOpcode(),
C->isOpaque());
6367 if (VT == MVT::f16 &&
C->getValueType(0) == MVT::i16)
6369 if (VT == MVT::f32 &&
C->getValueType(0) == MVT::i32)
6371 if (VT == MVT::f64 &&
C->getValueType(0) == MVT::i64)
6373 if (VT == MVT::f128 &&
C->getValueType(0) == MVT::i128)
6380 if (
auto *
C = dyn_cast<ConstantFPSDNode>(N1)) {
6434 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6437 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::f16)
6440 if (VT == MVT::i16 &&
C->getValueType(0) == MVT::bf16)
6443 if (VT == MVT::i32 &&
C->getValueType(0) == MVT::f32)
6446 if (VT == MVT::i64 &&
C->getValueType(0) == MVT::f64)
6447 return getConstant(V.bitcastToAPInt().getZExtValue(),
DL, VT);
6462 if (
auto *C1 = dyn_cast<ConstantSDNode>(Ops[0])) {
6463 if (
auto *C2 = dyn_cast<ConstantSDNode>(Ops[1])) {
6464 if (C1->isOpaque() || C2->isOpaque())
6467 std::optional<APInt> FoldAttempt =
6468 FoldValue(Opcode, C1->getAPIntValue(), C2->getAPIntValue());
6474 "Can't fold vectors ops with scalar operands");
6495 Ops[0].getValueType() == VT && Ops[1].getValueType() == VT &&
6500 auto *BV1 = dyn_cast<BuildVectorSDNode>(N1);
6501 auto *BV2 = dyn_cast<BuildVectorSDNode>(N2);
6508 if (BV1->getConstantRawBits(IsLE, EltBits, RawBits1, UndefElts1) &&
6509 BV2->getConstantRawBits(IsLE, EltBits, RawBits2, UndefElts2)) {
6513 Opcode, RawBits1[
I], UndefElts1[
I], RawBits2[
I], UndefElts2[
I]);
6524 DstBits, RawBits, DstUndefs,
6526 EVT BVEltVT = BV1->getOperand(0).getValueType();
6529 for (
unsigned I = 0, E = DstBits.
size();
I != E; ++
I) {
6547 ? Ops[0].getConstantOperandAPInt(0) * RHSVal
6548 : Ops[0].getConstantOperandAPInt(0) << RHSVal;
6553 auto IsScalarOrSameVectorSize = [NumElts](
const SDValue &
Op) {
6554 return !
Op.getValueType().isVector() ||
6555 Op.getValueType().getVectorElementCount() == NumElts;
6558 auto IsBuildVectorSplatVectorOrUndef = [](
const SDValue &
Op) {
6567 if (!
llvm::all_of(Ops, IsBuildVectorSplatVectorOrUndef) ||
6596 for (
unsigned I = 0;
I != NumVectorElts;
I++) {
6599 EVT InSVT =
Op.getValueType().getScalarType();
6621 !isa<ConstantSDNode>(ScalarOp) &&
6635 if (LegalSVT != SVT)
6636 ScalarResult =
getNode(ExtendCode,
DL, LegalSVT, ScalarResult);
6654 if (Ops.
size() != 2)
6665 if (N1CFP && N2CFP) {
6712 if (N1C && N1C->getValueAPF().isNegZero() && N2.
isUndef())
6741 ID.AddInteger(
A.value());
6744 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
6748 newSDNode<AssertAlignSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs,
A);
6749 createOperands(
N, {Val});
6751 CSEMap.InsertNode(
N, IP);
6764 return getNode(Opcode,
DL, VT, N1, N2, Flags);
6778 if ((N1C && !N2C) || (N1CFP && !N2CFP))
6792 "Operand is DELETED_NODE!");
6796 auto *N1C = dyn_cast<ConstantSDNode>(N1);
6797 auto *N2C = dyn_cast<ConstantSDNode>(N2);
6808 N2.
getValueType() == MVT::Other &&
"Invalid token factor!");
6812 if (N1 == N2)
return N1;
6828 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6830 N1.
getValueType() == VT &&
"Binary operator types must match!");
6833 if (N2CV && N2CV->
isZero())
6842 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6844 N1.
getValueType() == VT &&
"Binary operator types must match!");
6847 if (N2CV && N2CV->
isZero())
6854 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6856 N1.
getValueType() == VT &&
"Binary operator types must match!");
6861 const APInt &N2CImm = N2C->getAPIntValue();
6875 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6877 N1.
getValueType() == VT &&
"Binary operator types must match!");
6889 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6891 N1.
getValueType() == VT &&
"Binary operator types must match!");
6895 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6897 N1.
getValueType() == VT &&
"Binary operator types must match!");
6903 assert(VT.
isInteger() &&
"This operator does not apply to FP types!");
6905 N1.
getValueType() == VT &&
"Binary operator types must match!");
6916 N1.
getValueType() == VT &&
"Binary operator types must match!");
6924 "Invalid FCOPYSIGN!");
6929 const APInt &ShiftImm = N2C->getAPIntValue();
6941 "Shift operators return type must be the same as their first arg");
6943 "Shifts only work on integers");
6945 "Vector shift amounts must be in the same as their first arg");
6952 "Invalid use of small shift amount with oversized value!");
6959 if (N2CV && N2CV->
isZero())
6966 N2C && (N2C->getZExtValue() == 0 || N2C->getZExtValue() == 1) &&
6967 "Invalid FP_ROUND!");
6972 EVT EVT = cast<VTSDNode>(N2)->getVT();
6975 "Cannot *_EXTEND_INREG FP types");
6977 "AssertSExt/AssertZExt type should be the vector element type "
6978 "rather than the vector type!");
6984 EVT EVT = cast<VTSDNode>(N2)->getVT();
6987 "Cannot *_EXTEND_INREG FP types");
6989 "SIGN_EXTEND_INREG type should be vector iff the operand "
6993 "Vector element counts must match in SIGN_EXTEND_INREG");
6995 if (
EVT == VT)
return N1;
7005 const APInt &Val = N1C->getAPIntValue();
7006 return SignExtendInReg(Val, VT);
7019 APInt Val =
C->getAPIntValue();
7020 Ops.
push_back(SignExtendInReg(Val, OpVT));
7038 "FP_TO_*INT_SAT type should be vector iff the operand type is "
7042 "Vector element counts must match in FP_TO_*INT_SAT");
7043 assert(!cast<VTSDNode>(N2)->getVT().isVector() &&
7044 "Type to saturate to must be a scalar.");
7051 "The result of EXTRACT_VECTOR_ELT must be at least as wide as the \
7052 element type of the vector.");
7084 "BUILD_VECTOR used for scalable vectors");
7107 if (N1Op2C && N2C) {
7137 assert(N2C && (
unsigned)N2C->getZExtValue() < 2 &&
"Bad EXTRACT_ELEMENT!");
7141 "Wrong types for EXTRACT_ELEMENT!");
7152 unsigned Shift = ElementSize * N2C->getZExtValue();
7153 const APInt &Val = N1C->getAPIntValue();
7160 "Extract subvector VTs must be vectors!");
7162 "Extract subvector VTs must have the same element type!");
7164 "Cannot extract a scalable vector from a fixed length vector!");
7167 "Extract subvector must be from larger vector to smaller vector!");
7168 assert(N2C &&
"Extract subvector index must be a constant");
7172 "Extract subvector overflow!");
7173 assert(N2C->getAPIntValue().getBitWidth() ==
7175 "Constant index for EXTRACT_SUBVECTOR has an invalid size");
7190 return N1.
getOperand(N2C->getZExtValue() / Factor);
7258 if (VT != MVT::Glue) {
7262 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7263 E->intersectFlagsWith(Flags);
7267 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7269 createOperands(
N, Ops);
7270 CSEMap.InsertNode(
N, IP);
7272 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7273 createOperands(
N, Ops);
7287 return getNode(Opcode,
DL, VT, N1, N2, N3, Flags);
7296 "Operand is DELETED_NODE!");
7307 if (N1CFP && N2CFP && N3CFP) {
7336 "SETCC operands must have the same type!");
7338 "SETCC type should be vector iff the operand type is vector!");
7341 "SETCC vector element counts must match!");
7361 if (cast<ConstantSDNode>(N3)->
isZero())
7391 "Dest and insert subvector source types must match!");
7393 "Insert subvector VTs must be vectors!");
7395 "Insert subvector VTs must have the same element type!");
7397 "Cannot insert a scalable vector into a fixed length vector!");
7400 "Insert subvector must be from smaller vector to larger vector!");
7401 assert(isa<ConstantSDNode>(N3) &&
7402 "Insert subvector index must be constant");
7406 "Insert subvector overflow!");
7409 "Constant index for INSERT_SUBVECTOR has an invalid size");
7427 case ISD::VP_TRUNCATE:
7428 case ISD::VP_SIGN_EXTEND:
7429 case ISD::VP_ZERO_EXTEND:
7440 if (VT != MVT::Glue) {
7444 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
7445 E->intersectFlagsWith(Flags);
7449 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7451 createOperands(
N, Ops);
7452 CSEMap.InsertNode(
N, IP);
7454 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
7455 createOperands(
N, Ops);
7466 SDValue Ops[] = { N1, N2, N3, N4 };
7473 SDValue Ops[] = { N1, N2, N3, N4, N5 };
7491 if (FI->getIndex() < 0)
7506 assert(
C->getAPIntValue().getBitWidth() == 8);
7511 return DAG.
getConstant(Val, dl, VT,
false, IsOpaque);
7517 assert(
Value.getValueType() == MVT::i8 &&
"memset with non-byte fill value?");
7533 if (VT !=
Value.getValueType())
7546 if (Slice.
Array ==
nullptr) {
7549 if (VT == MVT::f32 || VT == MVT::f64 || VT == MVT::f128)
7564 unsigned NumVTBytes = NumVTBits / 8;
7565 unsigned NumBytes = std::min(NumVTBytes,
unsigned(Slice.
Length));
7567 APInt Val(NumVTBits, 0);
7569 for (
unsigned i = 0; i != NumBytes; ++i)
7572 for (
unsigned i = 0; i != NumBytes; ++i)
7573 Val |= (
uint64_t)(
unsigned char)Slice[i] << (NumVTBytes-i-1)*8;
7592 APInt(
Base.getValueSizeInBits().getFixedValue(),
7593 Offset.getKnownMinValue()));
7604 EVT BasePtrVT =
Ptr.getValueType();
7613 G = cast<GlobalAddressSDNode>(Src);
7614 else if (Src.getOpcode() ==
ISD::ADD &&
7617 G = cast<GlobalAddressSDNode>(Src.getOperand(0));
7618 SrcDelta = Src.getConstantOperandVal(1);
7624 SrcDelta +
G->getOffset());
7640 assert(OutLoadChains.
size() &&
"Missing loads in memcpy inlining");
7641 assert(OutStoreChains.
size() &&
"Missing stores in memcpy inlining");
7643 for (
unsigned i =
From; i < To; ++i) {
7645 GluedLoadChains.
push_back(OutLoadChains[i]);
7652 for (
unsigned i =
From; i < To; ++i) {
7653 StoreSDNode *ST = dyn_cast<StoreSDNode>(OutStoreChains[i]);
7655 ST->getBasePtr(), ST->getMemoryVT(),
7656 ST->getMemOperand());
7664 bool isVol,
bool AlwaysInline,
7680 std::vector<EVT> MemOps;
7681 bool DstAlignCanChange =
false;
7687 DstAlignCanChange =
true;
7689 if (!SrcAlign || Alignment > *SrcAlign)
7690 SrcAlign = Alignment;
7691 assert(SrcAlign &&
"SrcAlign must be set");
7695 bool isZeroConstant = CopyFromConstant && Slice.
Array ==
nullptr;
7697 const MemOp Op = isZeroConstant
7701 *SrcAlign, isVol, CopyFromConstant);
7707 if (DstAlignCanChange) {
7708 Type *Ty = MemOps[0].getTypeForEVT(
C);
7709 Align NewAlign =
DL.getABITypeAlign(Ty);
7715 if (!
TRI->hasStackRealignment(MF))
7716 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7719 if (NewAlign > Alignment) {
7723 Alignment = NewAlign;
7731 const Value *SrcVal = dyn_cast_if_present<const Value *>(SrcPtrInfo.
V);
7741 unsigned NumMemOps = MemOps.
size();
7743 for (
unsigned i = 0; i != NumMemOps; ++i) {
7748 if (VTSize >
Size) {
7751 assert(i == NumMemOps-1 && i != 0);
7752 SrcOff -= VTSize -
Size;
7753 DstOff -= VTSize -
Size;
7756 if (CopyFromConstant &&
7764 if (SrcOff < Slice.
Length) {
7766 SubSlice.
move(SrcOff);
7769 SubSlice.
Array =
nullptr;
7771 SubSlice.
Length = VTSize;
7774 if (
Value.getNode()) {
7778 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
7783 if (!Store.getNode()) {
7792 bool isDereferenceable =
7795 if (isDereferenceable)
7810 DstPtrInfo.
getWithOffset(DstOff), VT, Alignment, MMOFlags, NewAAInfo);
7820 unsigned NumLdStInMemcpy = OutStoreChains.
size();
7822 if (NumLdStInMemcpy) {
7828 for (
unsigned i = 0; i < NumLdStInMemcpy; ++i) {
7834 if (NumLdStInMemcpy <= GluedLdStLimit) {
7836 NumLdStInMemcpy, OutLoadChains,
7839 unsigned NumberLdChain = NumLdStInMemcpy / GluedLdStLimit;
7840 unsigned RemainingLdStInMemcpy = NumLdStInMemcpy % GluedLdStLimit;
7841 unsigned GlueIter = 0;
7843 for (
unsigned cnt = 0; cnt < NumberLdChain; ++cnt) {
7844 unsigned IndexFrom = NumLdStInMemcpy - GlueIter - GluedLdStLimit;
7845 unsigned IndexTo = NumLdStInMemcpy - GlueIter;
7848 OutLoadChains, OutStoreChains);
7849 GlueIter += GluedLdStLimit;
7853 if (RemainingLdStInMemcpy) {
7855 RemainingLdStInMemcpy, OutLoadChains,
7867 bool isVol,
bool AlwaysInline,
7881 std::vector<EVT> MemOps;
7882 bool DstAlignCanChange =
false;
7888 DstAlignCanChange =
true;
7890 if (!SrcAlign || Alignment > *SrcAlign)
7891 SrcAlign = Alignment;
7892 assert(SrcAlign &&
"SrcAlign must be set");
7902 if (DstAlignCanChange) {
7903 Type *Ty = MemOps[0].getTypeForEVT(
C);
7904 Align NewAlign =
DL.getABITypeAlign(Ty);
7910 if (!
TRI->hasStackRealignment(MF))
7911 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
7914 if (NewAlign > Alignment) {
7918 Alignment = NewAlign;
7932 unsigned NumMemOps = MemOps.
size();
7933 for (
unsigned i = 0; i < NumMemOps; i++) {
7938 bool isDereferenceable =
7941 if (isDereferenceable)
7947 SrcPtrInfo.
getWithOffset(SrcOff), *SrcAlign, SrcMMOFlags, NewAAInfo);
7954 for (
unsigned i = 0; i < NumMemOps; i++) {
7960 Chain, dl, LoadValues[i],
7962 DstPtrInfo.
getWithOffset(DstOff), Alignment, MMOFlags, NewAAInfo);
8002 std::vector<EVT> MemOps;
8003 bool DstAlignCanChange =
false;
8009 DstAlignCanChange =
true;
8015 MemOp::Set(
Size, DstAlignCanChange, Alignment, IsZeroVal, isVol),
8019 if (DstAlignCanChange) {
8022 Align NewAlign =
DL.getABITypeAlign(Ty);
8028 if (!
TRI->hasStackRealignment(MF))
8029 while (NewAlign > Alignment &&
DL.exceedsNaturalStackAlignment(NewAlign))
8032 if (NewAlign > Alignment) {
8036 Alignment = NewAlign;
8042 unsigned NumMemOps = MemOps.size();
8045 EVT LargestVT = MemOps[0];
8046 for (
unsigned i = 1; i < NumMemOps; i++)
8047 if (MemOps[i].bitsGT(LargestVT))
8048 LargestVT = MemOps[i];
8055 for (
unsigned i = 0; i < NumMemOps; i++) {
8058 if (VTSize >
Size) {
8061 assert(i == NumMemOps-1 && i != 0);
8062 DstOff -= VTSize -
Size;
8069 if (VT.
bitsLT(LargestVT)) {
8090 assert(
Value.getValueType() == VT &&
"Value with wrong type.");
8117 bool isVol,
bool AlwaysInline,
bool isTailCall,
8126 if (ConstantSize->
isZero())
8130 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8131 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8132 if (Result.getNode())
8140 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline,
8141 DstPtrInfo, SrcPtrInfo);
8142 if (Result.getNode())
8149 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8151 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8152 isVol,
true, DstPtrInfo, SrcPtrInfo, AAInfo, AA);
8168 Entry.Node = Dst; Args.push_back(Entry);
8169 Entry.Node = Src; Args.push_back(Entry);
8172 Entry.Node =
Size; Args.push_back(Entry);
8178 Dst.getValueType().getTypeForEVT(*
getContext()),
8185 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8186 return CallResult.second;
8191 Type *SizeTy,
unsigned ElemSz,
8200 Args.push_back(Entry);
8203 Args.push_back(Entry);
8207 Args.push_back(Entry);
8211 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8225 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8226 return CallResult.second;
8231 bool isVol,
bool isTailCall,
8240 if (ConstantSize->
isZero())
8244 *
this, dl, Chain, Dst, Src, ConstantSize->
getZExtValue(), Alignment,
8245 isVol,
false, DstPtrInfo, SrcPtrInfo, AAInfo);
8246 if (Result.getNode())
8255 Alignment, isVol, DstPtrInfo, SrcPtrInfo);
8256 if (Result.getNode())
8270 Entry.Node = Dst; Args.push_back(Entry);
8271 Entry.Node = Src; Args.push_back(Entry);
8274 Entry.Node =
Size; Args.push_back(Entry);
8280 Dst.getValueType().getTypeForEVT(*
getContext()),
8287 std::pair<SDValue,SDValue> CallResult = TLI->
LowerCallTo(CLI);
8288 return CallResult.second;
8293 Type *SizeTy,
unsigned ElemSz,
8302 Args.push_back(Entry);
8305 Args.push_back(Entry);
8309 Args.push_back(Entry);
8313 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8327 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8328 return CallResult.second;
8333 bool isVol,
bool AlwaysInline,
bool isTailCall,
8341 if (ConstantSize->
isZero())
8346 isVol,
false, DstPtrInfo, AAInfo);
8348 if (Result.getNode())
8356 *
this, dl, Chain, Dst, Src,
Size, Alignment, isVol, AlwaysInline, DstPtrInfo);
8357 if (Result.getNode())
8364 assert(ConstantSize &&
"AlwaysInline requires a constant size!");
8367 isVol,
true, DstPtrInfo, AAInfo);
8369 "getMemsetStores must return a valid sequence when AlwaysInline");
8386 const auto CreateEntry = [](
SDValue Node,
Type *Ty) {
8397 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8404 Args.push_back(CreateEntry(Src, Src.getValueType().getTypeForEVT(Ctx)));
8405 Args.push_back(CreateEntry(
Size,
DL.getIntPtrType(Ctx)));
8407 Dst.getValueType().getTypeForEVT(Ctx),
8415 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8416 return CallResult.second;
8421 Type *SizeTy,
unsigned ElemSz,
8429 Args.push_back(Entry);
8433 Args.push_back(Entry);
8437 Args.push_back(Entry);
8441 if (LibraryCall == RTLIB::UNKNOWN_LIBCALL)
8455 std::pair<SDValue, SDValue> CallResult = TLI->
LowerCallTo(CLI);
8456 return CallResult.second;
8468 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8469 cast<AtomicSDNode>(E)->refineAlignment(MMO);
8474 VTList, MemVT, MMO);
8475 createOperands(
N, Ops);
8477 CSEMap.InsertNode(
N, IP);
8491 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8516 "Invalid Atomic Op");
8523 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8533 return getAtomic(Opcode, dl, MemVT, VTs, Ops, MMO);
8538 if (Ops.
size() == 1)
8553 if (
Size.hasValue() && !
Size.getValue())
8570 (Opcode <= (
unsigned)std::numeric_limits<int>::max() &&
8572 "Opcode is not a memory-accessing opcode!");
8576 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
8579 ID.AddInteger(getSyntheticNodeSubclassData<MemIntrinsicSDNode>(
8580 Opcode, dl.
getIROrder(), VTList, MemVT, MMO));
8585 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8586 cast<MemIntrinsicSDNode>(E)->refineAlignment(MMO);
8591 VTList, MemVT, MMO);
8592 createOperands(
N, Ops);
8594 CSEMap.InsertNode(
N, IP);
8597 VTList, MemVT, MMO);
8598 createOperands(
N, Ops);
8607 SDValue Chain,
int FrameIndex,
8619 ID.AddInteger(FrameIndex);
8623 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8628 createOperands(
N, Ops);
8629 CSEMap.InsertNode(
N, IP);
8644 ID.AddInteger(Guid);
8647 if (
SDNode *E = FindNodeOrInsertPos(
ID, Dl, IP))
8650 auto *
N = newSDNode<PseudoProbeSDNode>(
8652 createOperands(
N, Ops);
8653 CSEMap.InsertNode(
N, IP);
8674 !isa<ConstantSDNode>(
Ptr.getOperand(1)) ||
8675 !isa<FrameIndexSDNode>(
Ptr.getOperand(0)))
8678 int FI = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
8681 Offset + cast<ConstantSDNode>(
Ptr.getOperand(1))->getSExtValue());
8692 if (
ConstantSDNode *OffsetNode = dyn_cast<ConstantSDNode>(OffsetOp))
8707 "Invalid chain type");
8719 Alignment, AAInfo, Ranges);
8730 assert(VT == MemVT &&
"Non-extending load from different memory type!");
8734 "Should only be an extending load, not truncating!");
8736 "Cannot convert from FP to Int or Int -> FP!");
8738 "Cannot use an ext load to convert to or from a vector!");
8741 "Cannot use an ext load to change the number of vector elements!");
8753 ID.AddInteger(getSyntheticNodeSubclassData<LoadSDNode>(
8754 dl.
getIROrder(), VTs, AM, ExtType, MemVT, MMO));
8758 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8759 cast<LoadSDNode>(E)->refineAlignment(MMO);
8763 ExtType, MemVT, MMO);
8764 createOperands(
N, Ops);
8766 CSEMap.InsertNode(
N, IP);
8780 PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges);
8798 MemVT, Alignment, MMOFlags, AAInfo);
8813 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
8816 LD->getMemOperand()->getFlags() &
8819 LD->getChain(),
Base,
Offset, LD->getPointerInfo(),
8820 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo());
8846 "Invalid chain type");
8854 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8859 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8860 cast<StoreSDNode>(E)->refineAlignment(MMO);
8865 createOperands(
N, Ops);
8867 CSEMap.InsertNode(
N, IP);
8880 "Invalid chain type");
8901 "Invalid chain type");
8906 "Should only be a truncating store, not extending!");
8908 "Can't do FP-INT conversion!");
8910 "Cannot use trunc store to convert to or from a vector!");
8913 "Cannot use trunc store to change the number of vector elements!");
8921 ID.AddInteger(getSyntheticNodeSubclassData<StoreSDNode>(
8926 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
8927 cast<StoreSDNode>(E)->refineAlignment(MMO);
8932 createOperands(
N, Ops);
8934 CSEMap.InsertNode(
N, IP);
8945 assert(ST->getOffset().isUndef() &&
"Store is already a indexed store!");
8950 ID.AddInteger(ST->getMemoryVT().getRawBits());
8951 ID.AddInteger(ST->getRawSubclassData());
8952 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
8953 ID.AddInteger(ST->getMemOperand()->getFlags());
8955 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
8959 ST->isTruncatingStore(), ST->getMemoryVT(),
8960 ST->getMemOperand());
8961 createOperands(
N, Ops);
8963 CSEMap.InsertNode(
N, IP);
8975 const MDNode *Ranges,
bool IsExpanding) {
8988 Alignment, AAInfo, Ranges);
8989 return getLoadVP(AM, ExtType, VT, dl, Chain,
Ptr,
Offset, Mask, EVL, MemVT,
9008 ID.AddInteger(getSyntheticNodeSubclassData<VPLoadSDNode>(
9009 dl.
getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9013 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9014 cast<VPLoadSDNode>(E)->refineAlignment(MMO);
9018 ExtType, IsExpanding, MemVT, MMO);
9019 createOperands(
N, Ops);
9021 CSEMap.InsertNode(
N, IP);
9037 Mask, EVL, PtrInfo, VT, Alignment, MMOFlags, AAInfo, Ranges,
9046 Mask, EVL, VT, MMO, IsExpanding);
9055 const AAMDNodes &AAInfo,
bool IsExpanding) {
9058 EVL, PtrInfo, MemVT, Alignment, MMOFlags, AAInfo,
nullptr,
9068 EVL, MemVT, MMO, IsExpanding);
9074 auto *LD = cast<VPLoadSDNode>(OrigLoad);
9075 assert(LD->getOffset().isUndef() &&
"Load is already a indexed load!");
9078 LD->getMemOperand()->getFlags() &
9082 LD->getVectorLength(), LD->getPointerInfo(),
9083 LD->getMemoryVT(), LD->getAlign(), MMOFlags, LD->getAAInfo(),
9084 nullptr, LD->isExpandingLoad());
9091 bool IsCompressing) {
9101 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9102 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9106 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9107 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9111 IsTruncating, IsCompressing, MemVT, MMO);
9112 createOperands(
N, Ops);
9114 CSEMap.InsertNode(
N, IP);
9127 bool IsCompressing) {
9148 bool IsCompressing) {
9155 false, IsCompressing);
9158 "Should only be a truncating store, not extending!");
9161 "Cannot use trunc store to convert to or from a vector!");
9164 "Cannot use trunc store to change the number of vector elements!");
9168 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Mask, EVL};
9172 ID.AddInteger(getSyntheticNodeSubclassData<VPStoreSDNode>(
9177 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9178 cast<VPStoreSDNode>(E)->refineAlignment(MMO);
9184 createOperands(
N, Ops);
9186 CSEMap.InsertNode(
N, IP);
9196 auto *ST = cast<VPStoreSDNode>(OrigStore);
9197 assert(ST->getOffset().isUndef() &&
"Store is already an indexed store!");
9199 SDValue Ops[] = {ST->getChain(), ST->getValue(),
Base,
9200 Offset, ST->getMask(), ST->getVectorLength()};
9203 ID.AddInteger(ST->getMemoryVT().getRawBits());
9204 ID.AddInteger(ST->getRawSubclassData());
9205 ID.AddInteger(ST->getPointerInfo().getAddrSpace());
9206 ID.AddInteger(ST->getMemOperand()->getFlags());
9208 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9211 auto *
N = newSDNode<VPStoreSDNode>(
9213 ST->isCompressingStore(), ST->getMemoryVT(), ST->getMemOperand());
9214 createOperands(
N, Ops);
9216 CSEMap.InsertNode(
N, IP);
9236 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedLoadSDNode>(
9237 DL.getIROrder(), VTs, AM, ExtType, IsExpanding, MemVT, MMO));
9241 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9242 cast<VPStridedLoadSDNode>(E)->refineAlignment(MMO);
9247 newSDNode<VPStridedLoadSDNode>(
DL.getIROrder(),
DL.getDebugLoc(), VTs, AM,
9248 ExtType, IsExpanding, MemVT, MMO);
9249 createOperands(
N, Ops);
9250 CSEMap.InsertNode(
N, IP);
9264 Undef, Stride, Mask, EVL, VT, MMO, IsExpanding);
9273 Stride, Mask, EVL, MemVT, MMO, IsExpanding);
9282 bool IsTruncating,
bool IsCompressing) {
9292 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9293 DL.getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9296 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9297 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9300 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9301 VTs, AM, IsTruncating,
9302 IsCompressing, MemVT, MMO);
9303 createOperands(
N, Ops);
9305 CSEMap.InsertNode(
N, IP);
9317 bool IsCompressing) {
9324 false, IsCompressing);
9327 "Should only be a truncating store, not extending!");
9330 "Cannot use trunc store to convert to or from a vector!");
9333 "Cannot use trunc store to change the number of vector elements!");
9337 SDValue Ops[] = {Chain, Val,
Ptr, Undef, Stride, Mask, EVL};
9341 ID.AddInteger(getSyntheticNodeSubclassData<VPStridedStoreSDNode>(
9345 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
9346 cast<VPStridedStoreSDNode>(E)->refineAlignment(MMO);
9349 auto *
N = newSDNode<VPStridedStoreSDNode>(
DL.getIROrder(),
DL.getDebugLoc(),
9351 IsCompressing, SVT, MMO);
9352 createOperands(
N, Ops);
9354 CSEMap.InsertNode(
N, IP);
9364 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9369 ID.AddInteger(getSyntheticNodeSubclassData<VPGatherSDNode>(
9374 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9375 cast<VPGatherSDNode>(E)->refineAlignment(MMO);
9380 VT, MMO, IndexType);
9381 createOperands(
N, Ops);
9383 assert(
N->getMask().getValueType().getVectorElementCount() ==
9384 N->getValueType(0).getVectorElementCount() &&
9385 "Vector width mismatch between mask and data");
9386 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9387 N->getValueType(0).getVectorElementCount().isScalable() &&
9388 "Scalable flags of index and data do not match");
9390 N->getIndex().getValueType().getVectorElementCount(),
9391 N->getValueType(0).getVectorElementCount()) &&
9392 "Vector width mismatch between index and data");
9393 assert(isa<ConstantSDNode>(
N->getScale()) &&
9394 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9395 "Scale should be a constant power of 2");
9397 CSEMap.InsertNode(
N, IP);
9408 assert(Ops.
size() == 7 &&
"Incompatible number of operands");
9413 ID.AddInteger(getSyntheticNodeSubclassData<VPScatterSDNode>(
9418 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9419 cast<VPScatterSDNode>(E)->refineAlignment(MMO);
9423 VT, MMO, IndexType);
9424 createOperands(
N, Ops);
9426 assert(
N->getMask().getValueType().getVectorElementCount() ==
9427 N->getValue().getValueType().getVectorElementCount() &&
9428 "Vector width mismatch between mask and data");
9430 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9431 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9432 "Scalable flags of index and data do not match");
9434 N->getIndex().getValueType().getVectorElementCount(),
9435 N->getValue().getValueType().getVectorElementCount()) &&
9436 "Vector width mismatch between index and data");
9437 assert(isa<ConstantSDNode>(
N->getScale()) &&
9438 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9439 "Scale should be a constant power of 2");
9441 CSEMap.InsertNode(
N, IP);
9456 "Unindexed masked load with an offset!");
9463 ID.AddInteger(getSyntheticNodeSubclassData<MaskedLoadSDNode>(
9464 dl.
getIROrder(), VTs, AM, ExtTy, isExpanding, MemVT, MMO));
9468 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9469 cast<MaskedLoadSDNode>(E)->refineAlignment(MMO);
9473 AM, ExtTy, isExpanding, MemVT, MMO);
9474 createOperands(
N, Ops);
9476 CSEMap.InsertNode(
N, IP);
9487 assert(LD->getOffset().isUndef() &&
"Masked load is already a indexed load!");
9489 Offset, LD->getMask(), LD->getPassThru(),
9490 LD->getMemoryVT(), LD->getMemOperand(), AM,
9491 LD->getExtensionType(), LD->isExpandingLoad());
9499 bool IsCompressing) {
9501 "Invalid chain type");
9504 "Unindexed masked store with an offset!");
9511 ID.AddInteger(getSyntheticNodeSubclassData<MaskedStoreSDNode>(
9512 dl.
getIROrder(), VTs, AM, IsTruncating, IsCompressing, MemVT, MMO));
9516 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9517 cast<MaskedStoreSDNode>(E)->refineAlignment(MMO);
9522 IsTruncating, IsCompressing, MemVT, MMO);
9523 createOperands(
N, Ops);
9525 CSEMap.InsertNode(
N, IP);
9536 assert(ST->getOffset().isUndef() &&
9537 "Masked store is already a indexed store!");
9539 ST->getMask(), ST->getMemoryVT(), ST->getMemOperand(),
9540 AM, ST->isTruncatingStore(), ST->isCompressingStore());
9548 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9553 ID.AddInteger(getSyntheticNodeSubclassData<MaskedGatherSDNode>(
9554 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, ExtTy));
9558 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9559 cast<MaskedGatherSDNode>(E)->refineAlignment(MMO);
9564 VTs, MemVT, MMO, IndexType, ExtTy);
9565 createOperands(
N, Ops);
9567 assert(
N->getPassThru().getValueType() ==
N->getValueType(0) &&
9568 "Incompatible type of the PassThru value in MaskedGatherSDNode");
9569 assert(
N->getMask().getValueType().getVectorElementCount() ==
9570 N->getValueType(0).getVectorElementCount() &&
9571 "Vector width mismatch between mask and data");
9572 assert(
N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9573 N->getValueType(0).getVectorElementCount().isScalable() &&
9574 "Scalable flags of index and data do not match");
9576 N->getIndex().getValueType().getVectorElementCount(),
9577 N->getValueType(0).getVectorElementCount()) &&
9578 "Vector width mismatch between index and data");
9579 assert(isa<ConstantSDNode>(
N->getScale()) &&
9580 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9581 "Scale should be a constant power of 2");
9583 CSEMap.InsertNode(
N, IP);
9595 assert(Ops.
size() == 6 &&
"Incompatible number of operands");
9600 ID.AddInteger(getSyntheticNodeSubclassData<MaskedScatterSDNode>(
9601 dl.
getIROrder(), VTs, MemVT, MMO, IndexType, IsTrunc));
9605 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP)) {
9606 cast<MaskedScatterSDNode>(E)->refineAlignment(MMO);
9611 VTs, MemVT, MMO, IndexType, IsTrunc);
9612 createOperands(
N, Ops);
9614 assert(
N->getMask().getValueType().getVectorElementCount() ==
9615 N->getValue().getValueType().getVectorElementCount() &&
9616 "Vector width mismatch between mask and data");
9618 N->getIndex().getValueType().getVectorElementCount().isScalable() ==
9619 N->getValue().getValueType().getVectorElementCount().isScalable() &&
9620 "Scalable flags of index and data do not match");
9622 N->getIndex().getValueType().getVectorElementCount(),
9623 N->getValue().getValueType().getVectorElementCount()) &&
9624 "Vector width mismatch between index and data");
9625 assert(isa<ConstantSDNode>(
N->getScale()) &&
9626 N->getScale()->getAsAPIntVal().isPowerOf2() &&
9627 "Scale should be a constant power of 2");
9629 CSEMap.InsertNode(
N, IP);
9644 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9649 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9654 createOperands(
N, Ops);
9656 CSEMap.InsertNode(
N, IP);
9671 ID.AddInteger(getSyntheticNodeSubclassData<FPStateAccessSDNode>(
9676 if (
SDNode *E = FindNodeOrInsertPos(
ID, dl, IP))
9681 createOperands(
N, Ops);
9683 CSEMap.InsertNode(
N, IP);
9703 if (
auto *CondC = dyn_cast<ConstantSDNode>(
Cond))
9704 return CondC->isZero() ?
F :
T;
9710 if (CondC->isZero())
9736 return !Val || Val->getAPIntValue().uge(
X.getScalarValueSizeInBits());
9742 if (
X.getValueType().getScalarType() == MVT::i1)
9755 bool HasNan = (XC && XC->getValueAPF().isNaN()) ||
9757 bool HasInf = (XC && XC->getValueAPF().isInfinity()) ||
9760 if (Flags.hasNoNaNs() && (HasNan ||
X.isUndef() ||
Y.isUndef()))
9763 if (Flags.hasNoInfs() && (HasInf ||
X.isUndef() ||
Y.isUndef()))
9786 if (Opcode ==
ISD::FMUL && Flags.hasNoNaNs() && Flags.hasNoSignedZeros())
9801 switch (Ops.
size()) {
9803 case 1:
return getNode(Opcode,
DL, VT,
static_cast<const SDValue>(Ops[0]));
9804 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1]);
9805 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2]);
9820 return getNode(Opcode,
DL, VT, Ops, Flags);
9825 unsigned NumOps = Ops.
size();
9828 case 1:
return getNode(Opcode,
DL, VT, Ops[0], Flags);
9829 case 2:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Flags);
9830 case 3:
return getNode(Opcode,
DL, VT, Ops[0], Ops[1], Ops[2], Flags);
9835 for (
const auto &
Op : Ops)
9837 "Operand is DELETED_NODE!");
9852 assert(NumOps == 5 &&
"SELECT_CC takes 5 operands!");
9854 "LHS and RHS of condition must have same type!");
9856 "True and False arms of SelectCC must have same type!");
9858 "select_cc node must be of same type as true and false value!");
9862 "Expected select_cc with vector result to have the same sized "
9863 "comparison type!");
9866 assert(NumOps == 5 &&
"BR_CC takes 5 operands!");
9868 "LHS/RHS of comparison should match types!");
9874 Opcode = ISD::VP_XOR;
9879 Opcode = ISD::VP_AND;
9881 case ISD::VP_REDUCE_MUL:
9884 Opcode = ISD::VP_REDUCE_AND;
9886 case ISD::VP_REDUCE_ADD:
9889 Opcode = ISD::VP_REDUCE_XOR;
9891 case ISD::VP_REDUCE_SMAX:
9892 case ISD::VP_REDUCE_UMIN:
9896 Opcode = ISD::VP_REDUCE_AND;
9898 case ISD::VP_REDUCE_SMIN:
9899 case ISD::VP_REDUCE_UMAX:
9903 Opcode = ISD::VP_REDUCE_OR;
9911 if (VT != MVT::Glue) {
9916 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
9919 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9920 createOperands(
N, Ops);
9922 CSEMap.InsertNode(
N, IP);
9924 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
9925 createOperands(
N, Ops);
9945 return getNode(Opcode,
DL, VTList, Ops, Flags);
9954 for (
const auto &
Op : Ops)
9956 "Operand is DELETED_NODE!");
9965 "Invalid add/sub overflow op!");
9967 Ops[0].getValueType() == Ops[1].getValueType() &&
9968 Ops[0].getValueType() == VTList.
VTs[0] &&
9969 "Binary operator types must match!");
9970 SDValue N1 = Ops[0], N2 = Ops[1];
9976 if (N2CV && N2CV->
isZero()) {
10008 "Invalid add/sub overflow op!");
10010 Ops[0].getValueType() == Ops[1].getValueType() &&
10011 Ops[0].getValueType() == VTList.
VTs[0] &&
10012 Ops[2].getValueType() == VTList.
VTs[1] &&
10013 "Binary operator types must match!");
10019 VTList.
VTs[0] == Ops[0].getValueType() &&
10020 VTList.
VTs[0] == Ops[1].getValueType() &&
10021 "Binary operator types must match!");
10027 unsigned OutWidth = Width * 2;
10031 Val = Val.
sext(OutWidth);
10032 Mul =
Mul.sext(OutWidth);
10034 Val = Val.
zext(OutWidth);
10035 Mul =
Mul.zext(OutWidth);
10049 VTList.
VTs[0] == Ops[0].getValueType() &&
"frexp type mismatch");
10065 "Invalid STRICT_FP_EXTEND!");
10067 Ops[1].getValueType().isFloatingPoint() &&
"Invalid FP cast!");
10069 "STRICT_FP_EXTEND result type should be vector iff the operand "
10070 "type is vector!");
10073 Ops[1].getValueType().getVectorElementCount()) &&
10074 "Vector element count mismatch!");
10076 "Invalid fpext node, dst <= src!");
10079 assert(VTList.
NumVTs == 2 && Ops.
size() == 3 &&
"Invalid STRICT_FP_ROUND!");
10081 "STRICT_FP_ROUND result type should be vector iff the operand "
10082 "type is vector!");
10085 Ops[1].getValueType().getVectorElementCount()) &&
10086 "Vector element count mismatch!");
10088 Ops[1].getValueType().isFloatingPoint() &&
10089 VTList.
VTs[0].
bitsLT(Ops[1].getValueType()) &&
10090 isa<ConstantSDNode>(Ops[2]) &&
10091 (Ops[2]->getAsZExtVal() == 0 || Ops[2]->getAsZExtVal() == 1) &&
10092 "Invalid STRICT_FP_ROUND!");
10102 cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
10103 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10104 else if (N3.getOpcode() ==
ISD::AND)
10105 if (
ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
10109 if ((AndRHS->getValue() & (NumBits-1)) == NumBits-1)
10110 return getNode(Opcode,
DL, VT, N1, N2, N3.getOperand(0));
10118 if (VTList.
VTs[VTList.
NumVTs-1] != MVT::Glue) {
10121 void *IP =
nullptr;
10122 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP))
10125 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10126 createOperands(
N, Ops);
10127 CSEMap.InsertNode(
N, IP);
10129 N = newSDNode<SDNode>(Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTList);
10130 createOperands(
N, Ops);
10133 N->setFlags(Flags);
10142 return getNode(Opcode,
DL, VTList, std::nullopt);
10148 return getNode(Opcode,
DL, VTList, Ops);
10154 return getNode(Opcode,
DL, VTList, Ops);
10159 SDValue Ops[] = { N1, N2, N3 };
10160 return getNode(Opcode,
DL, VTList, Ops);
10165 SDValue Ops[] = { N1, N2, N3, N4 };
10166 return getNode(Opcode,
DL, VTList, Ops);
10172 SDValue Ops[] = { N1, N2, N3, N4, N5 };
10173 return getNode(Opcode,
DL, VTList, Ops);
10177 return makeVTList(SDNode::getValueTypeList(VT), 1);
10186 void *IP =
nullptr;
10192 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 2);
10193 VTListMap.InsertNode(Result, IP);
10195 return Result->getSDVTList();
10205 void *IP =
nullptr;
10212 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 3);
10213 VTListMap.InsertNode(Result, IP);
10215 return Result->getSDVTList();
10226 void *IP =
nullptr;
10234 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, 4);
10235 VTListMap.InsertNode(Result, IP);
10237 return Result->getSDVTList();
10241 unsigned NumVTs = VTs.
size();
10243 ID.AddInteger(NumVTs);
10244 for (
unsigned index = 0; index < NumVTs; index++) {
10245 ID.AddInteger(VTs[index].getRawBits());
10248 void *IP =
nullptr;
10253 Result =
new (Allocator)
SDVTListNode(
ID.Intern(Allocator), Array, NumVTs);
10254 VTListMap.InsertNode(Result, IP);
10256 return Result->getSDVTList();
10267 assert(
N->getNumOperands() == 1 &&
"Update with wrong number of operands");
10270 if (
Op ==
N->getOperand(0))
return N;
10273 void *InsertPos =
nullptr;
10274 if (
SDNode *Existing = FindModifiedNodeSlot(
N,
Op, InsertPos))
10279 if (!RemoveNodeFromCSEMaps(
N))
10280 InsertPos =
nullptr;
10283 N->OperandList[0].set(
Op);
10287 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10292 assert(
N->getNumOperands() == 2 &&
"Update with wrong number of operands");
10295 if (Op1 ==
N->getOperand(0) && Op2 ==
N->getOperand(1))
10299 void *InsertPos =
nullptr;
10300 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Op1, Op2, InsertPos))
10305 if (!RemoveNodeFromCSEMaps(
N))
10306 InsertPos =
nullptr;
10309 if (
N->OperandList[0] != Op1)
10310 N->OperandList[0].set(Op1);
10311 if (
N->OperandList[1] != Op2)
10312 N->OperandList[1].set(Op2);
10316 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10322 SDValue Ops[] = { Op1, Op2, Op3 };
10329 SDValue Ops[] = { Op1, Op2, Op3, Op4 };
10336 SDValue Ops[] = { Op1, Op2, Op3, Op4, Op5 };
10342 unsigned NumOps = Ops.
size();
10343 assert(
N->getNumOperands() == NumOps &&
10344 "Update with wrong number of operands");
10347 if (std::equal(Ops.
begin(), Ops.
end(),
N->op_begin()))
10351 void *InsertPos =
nullptr;
10352 if (
SDNode *Existing = FindModifiedNodeSlot(
N, Ops, InsertPos))
10357 if (!RemoveNodeFromCSEMaps(
N))
10358 InsertPos =
nullptr;
10361 for (
unsigned i = 0; i != NumOps; ++i)
10362 if (
N->OperandList[i] != Ops[i])
10363 N->OperandList[i].set(Ops[i]);
10367 if (InsertPos) CSEMap.InsertNode(
N, InsertPos);
10384 if (NewMemRefs.
empty()) {
10390 if (NewMemRefs.
size() == 1) {
10391 N->MemRefs = NewMemRefs[0];
10397 Allocator.template Allocate<MachineMemOperand *>(NewMemRefs.
size());
10399 N->MemRefs = MemRefsBuffer;
10400 N->NumMemRefs =
static_cast<int>(NewMemRefs.
size());
10423 SDValue Ops[] = { Op1, Op2 };
10431 SDValue Ops[] = { Op1, Op2, Op3 };
10464 SDValue Ops[] = { Op1, Op2 };
10472 New->setNodeId(-1);
10492 unsigned Order = std::min(
N->getIROrder(), OLoc.
getIROrder());
10493 N->setIROrder(Order);
10516 void *IP =
nullptr;
10517 if (VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue) {
10521 return UpdateSDLocOnMergeSDNode(ON,
SDLoc(
N));
10524 if (!RemoveNodeFromCSEMaps(
N))
10529 N->ValueList = VTs.
VTs;
10539 if (Used->use_empty())
10540 DeadNodeSet.
insert(Used);
10545 MN->clearMemRefs();
10549 createOperands(
N, Ops);
10553 if (!DeadNodeSet.
empty()) {
10555 for (
SDNode *
N : DeadNodeSet)
10556 if (
N->use_empty())
10562 CSEMap.InsertNode(
N, IP);
10567 unsigned OrigOpc = Node->getOpcode();
10572#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10573 case ISD::STRICT_##DAGN: NewOpc = ISD::DAGN; break;
10574#define CMP_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
10575 case ISD::STRICT_##DAGN: NewOpc = ISD::SETCC; break;
10576#include "llvm/IR/ConstrainedOps.def"
10579 assert(Node->getNumValues() == 2 &&
"Unexpected number of results!");
10582 SDValue InputChain = Node->getOperand(0);
10587 for (
unsigned i = 1, e = Node->getNumOperands(); i != e; ++i)
10630 SDValue Ops[] = { Op1, Op2 };
10638 SDValue Ops[] = { Op1, Op2, Op3 };
10652 SDValue Ops[] = { Op1, Op2 };
10660 SDValue Ops[] = { Op1, Op2, Op3 };
10675 SDValue Ops[] = { Op1, Op2 };
10684 SDValue Ops[] = { Op1, Op2, Op3 };
10705 bool DoCSE = VTs.
VTs[VTs.
NumVTs-1] != MVT::Glue;
10707 void *IP =
nullptr;
10713 if (
SDNode *E = FindNodeOrInsertPos(
ID,
DL, IP)) {
10714 return cast<MachineSDNode>(UpdateSDLocOnMergeSDNode(E,
DL));
10719 N = newSDNode<MachineSDNode>(~Opcode,
DL.getIROrder(),
DL.getDebugLoc(), VTs);
10720 createOperands(
N, Ops);
10723 CSEMap.InsertNode(
N, IP);
10736 VT, Operand, SRIdxVal);
10746 VT, Operand, Subreg, SRIdxVal);
10763 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10766 void *IP =
nullptr;
10768 E->intersectFlagsWith(Flags);
10778 if (VTList.
VTs[VTList.
NumVTs - 1] != MVT::Glue) {
10781 void *IP =
nullptr;
10782 if (FindNodeOrInsertPos(
ID,
SDLoc(), IP))
10792 SDNode *
N,
unsigned R,
bool IsIndirect,
10794 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10795 "Expected inlined-at fields to agree");
10798 {}, IsIndirect,
DL, O,
10807 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10808 "Expected inlined-at fields to agree");
10821 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10822 "Expected inlined-at fields to agree");
10833 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10834 "Expected inlined-at fields to agree");
10837 Dependencies, IsIndirect,
DL, O,
10843 unsigned VReg,
bool IsIndirect,
10845 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10846 "Expected inlined-at fields to agree");
10849 {}, IsIndirect,
DL, O,
10857 unsigned O,
bool IsVariadic) {
10858 assert(cast<DILocalVariable>(Var)->isValidLocationForIntrinsic(
DL) &&
10859 "Expected inlined-at fields to agree");
10862 DL, O, IsVariadic);
10866 unsigned OffsetInBits,
unsigned SizeInBits,
10867 bool InvalidateDbg) {
10870 assert(FromNode && ToNode &&
"Can't modify dbg values");
10875 if (
From == To || FromNode == ToNode)
10887 if (Dbg->isInvalidated())
10894 bool Changed =
false;
10895 auto NewLocOps = Dbg->copyLocationOps();
10897 NewLocOps.begin(), NewLocOps.end(),
10899 bool Match = Op == FromLocOp;
10909 auto *Expr = Dbg->getExpression();
10915 if (
auto FI = Expr->getFragmentInfo())
10916 if (OffsetInBits + SizeInBits > FI->SizeInBits)
10925 auto AdditionalDependencies = Dbg->getAdditionalDependencies();
10928 Var, Expr, NewLocOps, AdditionalDependencies, Dbg->isIndirect(),
10929 Dbg->getDebugLoc(), std::max(ToNode->
getIROrder(), Dbg->getOrder()),
10930 Dbg->isVariadic());
10933 if (InvalidateDbg) {
10935 Dbg->setIsInvalidated();
10936 Dbg->setIsEmitted();
10942 "Transferred DbgValues should depend on the new SDNode");
10948 if (!
N.getHasDebugValue())
10953 if (DV->isInvalidated())
10955 switch (
N.getOpcode()) {
10961 if (!isa<ConstantSDNode>(N0)) {
10962 bool RHSConstant = isa<ConstantSDNode>(N1);
10965 Offset =
N.getConstantOperandVal(1);
10968 if (!RHSConstant && DV->isIndirect())
10975 auto *DIExpr = DV->getExpression();
10976 auto NewLocOps = DV->copyLocationOps();
10977 bool Changed =
false;
10978 size_t OrigLocOpsSize = NewLocOps.size();
10979 for (
size_t i = 0; i < OrigLocOpsSize; ++i) {
10984 NewLocOps[i].getSDNode() != &
N)
10995 const auto *TmpDIExpr =
11003 NewLocOps.push_back(
RHS);
11009 assert(Changed &&
"Salvage target doesn't use N");
11012 DV->isVariadic() || OrigLocOpsSize != NewLocOps.size();
11014 auto AdditionalDependencies = DV->getAdditionalDependencies();
11016 DV->getVariable(), DIExpr, NewLocOps, AdditionalDependencies,
11017 DV->isIndirect(), DV->getDebugLoc(), DV->getOrder(), IsVariadic);
11019 DV->setIsInvalidated();
11020 DV->setIsEmitted();
11022 N0.
getNode()->dumprFull(
this);
11023 dbgs() <<
" into " << *DIExpr <<
'\n');
11030 TypeSize ToSize =
N.getValueSizeInBits(0);
11034 auto NewLocOps = DV->copyLocationOps();
11035 bool Changed =
false;
11036 for (
size_t i = 0; i < NewLocOps.size(); ++i) {
11038 NewLocOps[i].getSDNode() != &
N)
11045 assert(Changed &&
"Salvage target doesn't use N");
11050 DV->getAdditionalDependencies(), DV->isIndirect(),
11051 DV->getDebugLoc(), DV->getOrder(), DV->isVariadic());
11054 DV->setIsInvalidated();
11055 DV->setIsEmitted();
11057 dbgs() <<
" into " << *DbgExpression <<
'\n');
11064 assert(!Dbg->getSDNodes().empty() &&
11065 "Salvaged DbgValue should depend on a new SDNode");
11073 assert(cast<DILabel>(Label)->isValidLocationForIntrinsic(
DL) &&
11074 "Expected inlined-at fields to agree");
11090 while (UI != UE &&
N == *UI)
11098 :
SelectionDAG::DAGUpdateListener(d), UI(ui), UE(ue) {}
11111 "Cannot replace with this method!");
11127 RAUWUpdateListener Listener(*
this, UI, UE);
11132 RemoveNodeFromCSEMaps(
User);
11144 }
while (UI != UE && *UI ==
User);
11147 AddModifiedNodeToCSEMaps(
User);
11163 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11166 "Cannot use this version of ReplaceAllUsesWith!");
11174 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i)
11175 if (
From->hasAnyUseOfValue(i)) {
11176 assert((i < To->getNumValues()) &&
"Invalid To location");
11185 RAUWUpdateListener Listener(*
this, UI, UE);
11190 RemoveNodeFromCSEMaps(
User);
11202 }
while (UI != UE && *UI ==
User);
11206 AddModifiedNodeToCSEMaps(
User);
11220 if (
From->getNumValues() == 1)
11223 for (
unsigned i = 0, e =
From->getNumValues(); i != e; ++i) {
11233 RAUWUpdateListener Listener(*
this, UI, UE);
11238 RemoveNodeFromCSEMaps(
User);
11244 bool To_IsDivergent =
false;
11251 }
while (UI != UE && *UI ==
User);
11253 if (To_IsDivergent !=
From->isDivergent())
11258 AddModifiedNodeToCSEMaps(
User);
11271 if (
From == To)
return;
11274 if (
From.getNode()->getNumValues() == 1) {
11286 UE =
From.getNode()->use_end();
11287 RAUWUpdateListener Listener(*
this, UI, UE);
11290 bool UserRemovedFromCSEMaps =
false;
11300 if (
Use.getResNo() !=
From.getResNo()) {
11307 if (!UserRemovedFromCSEMaps) {
11308 RemoveNodeFromCSEMaps(
User);
11309 UserRemovedFromCSEMaps =
true;
11316 }
while (UI != UE && *UI ==
User);
11319 if (!UserRemovedFromCSEMaps)
11324 AddModifiedNodeToCSEMaps(
User);
11343bool operator<(
const UseMemo &L,
const UseMemo &R) {
11344 return (intptr_t)L.User < (intptr_t)R.User;
11354 for (UseMemo &Memo :
Uses)
11355 if (Memo.User ==
N)
11356 Memo.User =
nullptr;
11369 "Conflicting divergence information!");
11374 for (
const auto &
Op :
N->ops()) {
11375 if (
Op.Val.getValueType() != MVT::Other &&
Op.getNode()->isDivergent())
11386 if (
N->SDNodeBits.IsDivergent != IsDivergent) {
11387 N->SDNodeBits.IsDivergent = IsDivergent;
11390 }
while (!Worklist.
empty());
11393void SelectionDAG::CreateTopologicalOrder(std::vector<SDNode *> &Order) {
11395 Order.
reserve(AllNodes.size());
11397 unsigned NOps =
N.getNumOperands();
11400 Order.push_back(&
N);
11402 for (
size_t I = 0;
I != Order.size(); ++
I) {
11404 for (
auto *U :
N->uses()) {
11405 unsigned &UnsortedOps = Degree[U];
11406 if (0 == --UnsortedOps)
11407 Order.push_back(U);
11414 std::vector<SDNode *> TopoOrder;
11415 CreateTopologicalOrder(TopoOrder);
11416 for (
auto *
N : TopoOrder) {
11418 "Divergence bit inconsistency detected");
11441 for (
unsigned i = 0; i != Num; ++i) {
11442 unsigned FromResNo =
From[i].getResNo();
11445 E = FromNode->
use_end(); UI != E; ++UI) {
11447 if (
Use.getResNo() == FromResNo) {
11448 UseMemo Memo = { *UI, i, &
Use };
11449 Uses.push_back(Memo);
11456 RAUOVWUpdateListener Listener(*
this,
Uses);
11458 for (
unsigned UseIndex = 0, UseIndexEnd =
Uses.size();
11459 UseIndex != UseIndexEnd; ) {
11465 if (
User ==
nullptr) {
11471 RemoveNodeFromCSEMaps(
User);
11478 unsigned i =
Uses[UseIndex].Index;
11483 }
while (UseIndex != UseIndexEnd &&
Uses[UseIndex].
User ==
User);
11487 AddModifiedNodeToCSEMaps(
User);
11495 unsigned DAGSize = 0;
11511 unsigned Degree =
N.getNumOperands();
11514 N.setNodeId(DAGSize++);
11516 if (Q != SortedPos)
11517 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(Q));
11518 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11522 N.setNodeId(Degree);
11534 unsigned Degree =
P->getNodeId();
11535 assert(Degree != 0 &&
"Invalid node degree");
11539 P->setNodeId(DAGSize++);
11540 if (
P->getIterator() != SortedPos)
11541 SortedPos = AllNodes.insert(SortedPos, AllNodes.remove(
P));
11542 assert(SortedPos != AllNodes.end() &&
"Overran node list");
11546 P->setNodeId(Degree);
11549 if (Node.getIterator() == SortedPos) {
11553 dbgs() <<
"Overran sorted position:\n";
11555 dbgs() <<
"Checking if this is due to cycles\n";
11562 assert(SortedPos == AllNodes.end() &&
11563 "Topological sort incomplete!");
11565 "First node in topological sort is not the entry token!");
11566 assert(AllNodes.front().getNodeId() == 0 &&
11567 "First node in topological sort has non-zero id!");
11568 assert(AllNodes.front().getNumOperands() == 0 &&
11569 "First node in topological sort has operands!");
11570 assert(AllNodes.back().getNodeId() == (
int)DAGSize-1 &&
11571 "Last node in topologic sort has unexpected id!");
11572 assert(AllNodes.back().use_empty() &&
11573 "Last node in topologic sort has users!");
11581 for (
SDNode *SD : DB->getSDNodes()) {
11585 SD->setHasDebugValue(
true);
11587 DbgInfo->
add(DB, isParameter);
11594 assert(isa<MemSDNode>(NewMemOpChain) &&
"Expected a memop node");
11600 if (OldChain == NewMemOpChain || OldChain.
use_empty())
11601 return NewMemOpChain;
11604 OldChain, NewMemOpChain);
11607 return TokenFactor;
11612 assert(isa<MemSDNode>(NewMemOp.
getNode()) &&
"Expected a memop node");
11620 assert(isa<ExternalSymbolSDNode>(
Op) &&
"Node should be an ExternalSymbol");
11622 auto *Symbol = cast<ExternalSymbolSDNode>(
Op)->getSymbol();
11626 if (OutFunction !=
nullptr)
11634 std::string ErrorStr;
11636 ErrorFormatter <<
"Undefined external symbol ";
11637 ErrorFormatter <<
'"' << Symbol <<
'"';
11647 return Const !=
nullptr && Const->isZero();
11652 return Const !=
nullptr && Const->isZero() && !Const->isNegative();
11657 return Const !=
nullptr && Const->isAllOnes();
11662 return Const !=
nullptr && Const->isOne();
11667 return Const !=
nullptr && Const->isMinSignedValue();
11671 unsigned OperandNo) {
11676 APInt Const = ConstV->getAPIntValue().trunc(V.getScalarValueSizeInBits());
11682 return Const.isZero();
11684 return Const.isOne();
11687 return Const.isAllOnes();
11689 return Const.isMinSignedValue();
11691 return Const.isMaxSignedValue();
11696 return OperandNo == 1 && Const.isZero();
11699 return OperandNo == 1 && Const.isOne();
11704 return ConstFP->isZero() &&
11705 (Flags.hasNoSignedZeros() || ConstFP->isNegative());
11707 return OperandNo == 1 && ConstFP->isZero() &&
11708 (Flags.hasNoSignedZeros() || !ConstFP->isNegative());
11710 return ConstFP->isExactlyValue(1.0);
11712 return OperandNo == 1 && ConstFP->isExactlyValue(1.0);
11716 EVT VT = V.getValueType();
11718 APFloat NeutralAF = !Flags.hasNoNaNs()
11720 : !Flags.hasNoInfs()
11726 return ConstFP->isExactlyValue(NeutralAF);
11735 V = V.getOperand(0);
11740 while (V.getOpcode() ==
ISD::BITCAST && V.getOperand(0).hasOneUse())
11741 V = V.getOperand(0);
11747 V = V.getOperand(0);
11753 V = V.getOperand(0);
11761 unsigned NumBits = V.getScalarValueSizeInBits();
11764 return C && (
C->getAPIntValue().countr_one() >= NumBits);
11768 bool AllowTruncation) {
11769 EVT VT =
N.getValueType();
11778 bool AllowTruncation) {
11785 EVT VecEltVT =
N->getValueType(0).getVectorElementType();
11786 if (
auto *CN = dyn_cast<ConstantSDNode>(
N->getOperand(0))) {
11787 EVT CVT = CN->getValueType(0);
11788 assert(CVT.
bitsGE(VecEltVT) &&
"Illegal splat_vector element extension");
11789 if (AllowTruncation || CVT == VecEltVT)
11796 ConstantSDNode *CN = BV->getConstantSplatNode(DemandedElts, &UndefElements);
11801 if (CN && (UndefElements.
none() || AllowUndefs)) {
11803 EVT NSVT =
N.getValueType().getScalarType();
11804 assert(CVT.
bitsGE(NSVT) &&
"Illegal build vector element extension");
11805 if (AllowTruncation || (CVT == NSVT))
11814 EVT VT =
N.getValueType();
11822 const APInt &DemandedElts,
11823 bool AllowUndefs) {
11830 BV->getConstantFPSplatNode(DemandedElts, &UndefElements);
11832 if (CN && (UndefElements.
none() || AllowUndefs))
11847 return C &&
C->isZero();
11853 return C &&
C->isOne();
11858 unsigned BitWidth =
N.getScalarValueSizeInBits();
11860 return C &&
C->isAllOnes() &&
C->getValueSizeInBits(0) ==
BitWidth;
11869 :
SDNode(Opc, Order, dl, VTs), MemoryVT(memvt), MMO(mmo) {
11893 std::vector<EVT> VTs;
11906const EVT *SDNode::getValueTypeList(
EVT VT) {
11907 static std::set<EVT, EVT::compareRawBits> EVTs;
11908 static EVTArray SimpleVTArray;
11913 return &(*EVTs.insert(VT).first);
11927 if (UI.getUse().getResNo() ==
Value) {
11944 if (UI.getUse().getResNo() ==
Value)
11982 return any_of(
N->op_values(),
11983 [
this](
SDValue Op) { return this == Op.getNode(); });
11997 unsigned Depth)
const {
11998 if (*
this == Dest)
return true;
12002 if (
Depth == 0)
return false;
12022 return Op.reachesChainWithoutSideEffects(Dest, Depth - 1);
12027 if (
LoadSDNode *Ld = dyn_cast<LoadSDNode>(*
this)) {
12028 if (Ld->isUnordered())
12029 return Ld->getChain().reachesChainWithoutSideEffects(Dest,
Depth-1);
12048 bool AllowPartials) {
12057 return Op.getOpcode() ==
unsigned(BinOp);
12063 unsigned CandidateBinOp =
Op.getOpcode();
12064 if (
Op.getValueType().isFloatingPoint()) {
12066 switch (CandidateBinOp) {
12068 if (!Flags.hasNoSignedZeros() || !Flags.hasAllowReassociation())
12078 auto PartialReduction = [&](
SDValue Op,
unsigned NumSubElts) {
12079 if (!AllowPartials || !
Op)
12081 EVT OpVT =
Op.getValueType();
12104 unsigned Stages =
Log2_32(
Op.getValueType().getVectorNumElements());
12106 for (
unsigned i = 0; i < Stages; ++i) {
12107 unsigned MaskEnd = (1 << i);
12109 if (
Op.getOpcode() != CandidateBinOp)
12110 return PartialReduction(PrevOp, MaskEnd);
12119 Shuffle = dyn_cast<ShuffleVectorSDNode>(Op1);
12126 return PartialReduction(PrevOp, MaskEnd);
12131 return PartialReduction(PrevOp, MaskEnd);
12138 while (
Op.getOpcode() == CandidateBinOp) {
12139 unsigned NumElts =
Op.getValueType().getVectorNumElements();
12147 unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
12148 if (NumSrcElts != (2 * NumElts))
12163 EVT VT =
N->getValueType(0);
12172 else if (NE > ResNE)
12175 if (
N->getNumValues() == 2) {
12178 EVT VT1 =
N->getValueType(1);
12182 for (i = 0; i != NE; ++i) {
12183 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12184 SDValue Operand =
N->getOperand(j);
12203 assert(
N->getNumValues() == 1 &&
12204 "Can't unroll a vector with multiple results!");
12210 for (i= 0; i != NE; ++i) {
12211 for (
unsigned j = 0, e =
N->getNumOperands(); j != e; ++j) {
12212 SDValue Operand =
N->getOperand(j);
12225 switch (
N->getOpcode()) {
12252 for (; i < ResNE; ++i)
12261 unsigned Opcode =
N->getOpcode();
12265 "Expected an overflow opcode");
12267 EVT ResVT =
N->getValueType(0);
12268 EVT OvVT =
N->getValueType(1);
12277 else if (NE > ResNE)
12289 for (
unsigned i = 0; i < NE; ++i) {
12290 SDValue Res =
getNode(Opcode, dl, VTs, LHSScalars[i], RHSScalars[i]);
12313 if (LD->isVolatile() ||
Base->isVolatile())
12316 if (!LD->isSimple())
12318 if (LD->isIndexed() ||
Base->isIndexed())
12320 if (LD->getChain() !=
Base->getChain())
12322 EVT VT = LD->getMemoryVT();
12330 if (BaseLocDecomp.equalBaseIndex(LocDecomp, *
this,
Offset))
12331 return (Dist * (int64_t)Bytes ==
Offset);
12340 int64_t GVOffset = 0;
12352 int FrameIdx = INT_MIN;
12353 int64_t FrameOffset = 0;
12355 FrameIdx = FI->getIndex();
12357 isa<FrameIndexSDNode>(
Ptr.getOperand(0))) {
12359 FrameIdx = cast<FrameIndexSDNode>(
Ptr.getOperand(0))->getIndex();
12360 FrameOffset =
Ptr.getConstantOperandVal(1);
12363 if (FrameIdx != INT_MIN) {
12368 return std::nullopt;
12378 "Split node must be a scalar type");
12383 return std::make_pair(
Lo,
Hi);
12396 return std::make_pair(LoVT, HiVT);
12404 bool *HiIsEmpty)
const {
12414 "Mixing fixed width and scalable vectors when enveloping a type");
12419 *HiIsEmpty =
false;
12427 return std::make_pair(LoVT, HiVT);
12432std::pair<SDValue, SDValue>
12437 "Splitting vector with an invalid mixture of fixed and scalable "
12440 N.getValueType().getVectorMinNumElements() &&
12441 "More vector elements requested than available!");
12451 return std::make_pair(
Lo,
Hi);
12458 EVT VT =
N.getValueType();
12460 "Expecting the mask to be an evenly-sized vector");
12468 return std::make_pair(
Lo,
Hi);
12473 EVT VT =
N.getValueType();
12482 unsigned Start,
unsigned Count,
12484 EVT VT =
Op.getValueType();
12487 if (EltVT ==
EVT())
12490 for (
unsigned i = Start, e = Start + Count; i != e; ++i) {
12503 return Val.MachineCPVal->getType();
12504 return Val.ConstVal->getType();
12508 unsigned &SplatBitSize,
12509 bool &HasAnyUndefs,
12510 unsigned MinSplatBits,
12511 bool IsBigEndian)
const {
12515 if (MinSplatBits > VecWidth)
12520 SplatValue =
APInt(VecWidth, 0);
12521 SplatUndef =
APInt(VecWidth, 0);
12528 assert(NumOps > 0 &&
"isConstantSplat has 0-size build vector");
12531 for (
unsigned j = 0; j < NumOps; ++j) {
12532 unsigned i = IsBigEndian ? NumOps - 1 - j : j;
12534 unsigned BitPos = j * EltWidth;
12537 SplatUndef.
setBits(BitPos, BitPos + EltWidth);
12538 else if (
auto *CN = dyn_cast<ConstantSDNode>(OpVal))
12539 SplatValue.
insertBits(CN->getAPIntValue().zextOrTrunc(EltWidth), BitPos);
12540 else if (
auto *CN = dyn_cast<ConstantFPSDNode>(OpVal))
12541 SplatValue.
insertBits(CN->getValueAPF().bitcastToAPInt(), BitPos);
12548 HasAnyUndefs = (SplatUndef != 0);
12551 while (VecWidth > 8) {
12556 unsigned HalfSize = VecWidth / 2;
12563 if ((HighValue & ~LowUndef) != (LowValue & ~HighUndef) ||
12564 MinSplatBits > HalfSize)
12567 SplatValue = HighValue | LowValue;
12568 SplatUndef = HighUndef & LowUndef;
12570 VecWidth = HalfSize;
12579 SplatBitSize = VecWidth;
12586 if (UndefElements) {
12587 UndefElements->
clear();
12588 UndefElements->
resize(NumOps);
12594 for (
unsigned i = 0; i != NumOps; ++i) {
12595 if (!DemandedElts[i])
12598 if (
Op.isUndef()) {
12600 (*UndefElements)[i] =
true;
12601 }
else if (!Splatted) {
12603 }
else if (Splatted !=
Op) {
12609 unsigned FirstDemandedIdx = DemandedElts.
countr_zero();
12611 "Can only have a splat without a constant for all undefs.");
12628 if (UndefElements) {
12629 UndefElements->
clear();
12630 UndefElements->
resize(NumOps);
12638 for (
unsigned I = 0;
I != NumOps; ++
I)
12640 (*UndefElements)[
I] =
true;
12643 for (
unsigned SeqLen = 1; SeqLen < NumOps; SeqLen *= 2) {
12644 Sequence.append(SeqLen,
SDValue());
12645 for (
unsigned I = 0;
I != NumOps; ++
I) {
12646 if (!DemandedElts[
I])
12648 SDValue &SeqOp = Sequence[
I % SeqLen];
12650 if (
Op.isUndef()) {
12655 if (SeqOp && !SeqOp.
isUndef() && SeqOp !=
Op) {
12661 if (!Sequence.empty())
12665 assert(Sequence.empty() &&
"Failed to empty non-repeating sequence pattern");
12678 return dyn_cast_or_null<ConstantSDNode>(
12684 return dyn_cast_or_null<ConstantSDNode>(
getSplatValue(UndefElements));
12690 return dyn_cast_or_null<ConstantFPSDNode>(
12696 return dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements));
12703 dyn_cast_or_null<ConstantFPSDNode>(
getSplatValue(UndefElements))) {
12706 const APFloat &APF = CN->getValueAPF();
12712 return IntVal.exactLogBase2();
12718 bool IsLittleEndian,
unsigned DstEltSizeInBits,
12726 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12727 "Invalid bitcast scale");
12732 BitVector SrcUndeElements(NumSrcOps,
false);
12734 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12736 if (
Op.isUndef()) {
12737 SrcUndeElements.
set(
I);
12740 auto *CInt = dyn_cast<ConstantSDNode>(
Op);
12741 auto *CFP = dyn_cast<ConstantFPSDNode>(
Op);
12742 assert((CInt || CFP) &&
"Unknown constant");
12743 SrcBitElements[
I] = CInt ? CInt->getAPIntValue().trunc(SrcEltSizeInBits)
12744 : CFP->getValueAPF().bitcastToAPInt();
12748 recastRawBits(IsLittleEndian, DstEltSizeInBits, RawBitElements,
12749 SrcBitElements, UndefElements, SrcUndeElements);
12754 unsigned DstEltSizeInBits,
12759 unsigned NumSrcOps = SrcBitElements.
size();
12760 unsigned SrcEltSizeInBits = SrcBitElements[0].getBitWidth();
12761 assert(((NumSrcOps * SrcEltSizeInBits) % DstEltSizeInBits) == 0 &&
12762 "Invalid bitcast scale");
12763 assert(NumSrcOps == SrcUndefElements.
size() &&
12764 "Vector size mismatch");
12766 unsigned NumDstOps = (NumSrcOps * SrcEltSizeInBits) / DstEltSizeInBits;
12767 DstUndefElements.
clear();
12768 DstUndefElements.
resize(NumDstOps,
false);
12772 if (SrcEltSizeInBits <= DstEltSizeInBits) {
12773 unsigned Scale = DstEltSizeInBits / SrcEltSizeInBits;
12774 for (
unsigned I = 0;
I != NumDstOps; ++
I) {
12775 DstUndefElements.
set(
I);
12776 APInt &DstBits = DstBitElements[
I];
12777 for (
unsigned J = 0; J != Scale; ++J) {
12778 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12779 if (SrcUndefElements[
Idx])
12781 DstUndefElements.
reset(
I);
12782 const APInt &SrcBits = SrcBitElements[
Idx];
12784 "Illegal constant bitwidths");
12785 DstBits.
insertBits(SrcBits, J * SrcEltSizeInBits);
12792 unsigned Scale = SrcEltSizeInBits / DstEltSizeInBits;
12793 for (
unsigned I = 0;
I != NumSrcOps; ++
I) {
12794 if (SrcUndefElements[
I]) {
12795 DstUndefElements.
set(
I * Scale, (
I + 1) * Scale);
12798 const APInt &SrcBits = SrcBitElements[
I];
12799 for (
unsigned J = 0; J != Scale; ++J) {
12800 unsigned Idx = (
I * Scale) + (IsLittleEndian ? J : (Scale - J - 1));
12801 APInt &DstBits = DstBitElements[
Idx];
12802 DstBits = SrcBits.
extractBits(DstEltSizeInBits, J * DstEltSizeInBits);
12809 unsigned Opc =
Op.getOpcode();
12816std::optional<std::pair<APInt, APInt>>
12820 return std::nullopt;
12824 return std::nullopt;
12831 return std::nullopt;
12833 for (
unsigned i = 2; i < NumOps; ++i) {
12835 return std::nullopt;
12838 if (Val != (Start + (Stride * i)))
12839 return std::nullopt;
12842 return std::make_pair(Start, Stride);
12858 for (
int Idx = Mask[i]; i != e; ++i)
12859 if (Mask[i] >= 0 && Mask[i] !=
Idx)
12867 if (isa<ConstantSDNode>(
N))
12868 return N.getNode();
12870 return N.getNode();
12878 isa<ConstantSDNode>(
N.getOperand(0)))
12879 return N.getNode();
12886 if (isa<ConstantFPSDNode>(
N))
12887 return N.getNode();
12890 return N.getNode();
12893 isa<ConstantFPSDNode>(
N.getOperand(0)))
12894 return N.getNode();
12900 assert(!Node->OperandList &&
"Node already has operands");
12902 "too many operands to fit into SDNode");
12903 SDUse *Ops = OperandRecycler.allocate(
12906 bool IsDivergent =
false;
12907 for (
unsigned I = 0;
I != Vals.
size(); ++
I) {
12908 Ops[
I].setUser(Node);
12909 Ops[
I].setInitial(Vals[
I]);
12910 if (Ops[
I].Val.getValueType() != MVT::Other)
12914 Node->OperandList = Ops;
12917 Node->SDNodeBits.IsDivergent = IsDivergent;
12925 while (Vals.
size() > Limit) {
12926 unsigned SliceIdx = Vals.
size() - Limit;
13000 const SDLoc &DLoc) {
13005 Entry.Ty =
Ptr.getValueType().getTypeForEVT(*
getContext());
13006 Args.push_back(Entry);
13018 assert(
From && To &&
"Invalid SDNode; empty source SDValue?");
13019 auto I = SDEI.find(
From);
13020 if (
I == SDEI.end())
13025 NodeExtraInfo NEI =
I->second;
13034 SDEI[To] = std::move(NEI);
13053 Leafs.emplace_back(
N);
13056 if (!FromReach.
insert(
N).second)
13064 auto DeepCopyTo = [&](
auto &&Self,
const SDNode *
N) {
13067 if (!Visited.
insert(
N).second)
13072 if (!Self(Self,
Op.getNode()))
13092 for (
const SDNode *
N : StartFrom)
13093 VisitFrom(VisitFrom,
N,
MaxDepth - PrevDepth);
13105 errs() <<
"warning: incomplete propagation of SelectionDAG::NodeExtraInfo\n";
13106 assert(
false &&
"From subgraph too complex - increase max. MaxDepth?");
13108 SDEI[To] = std::move(NEI);
13122 if (!Visited.
insert(
N).second) {
13123 errs() <<
"Detected cycle in SelectionDAG\n";
13124 dbgs() <<
"Offending node:\n";
13125 N->dumprFull(DAG);
dbgs() <<
"\n";
13141 bool check = force;
13142#ifdef EXPENSIVE_CHECKS
13146 assert(
N &&
"Checking nonexistent SDNode");
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
static bool isConstant(const MachineInstr &MI)
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
This file implements the APSInt class, which is a simple class that represents an arbitrary sized int...
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
static GCRegistry::Add< CoreCLRGC > E("coreclr", "CoreCLR-compatible GC")
Analysis containing CSE Info
static std::optional< bool > isBigEndian(const SmallDenseMap< int64_t, int64_t, 8 > &MemOffset2Idx, int64_t LowestIdx)
Given a map from byte offsets in memory to indices in a load/store, determine if that map corresponds...
#define __asan_unpoison_memory_region(p, size)
#define LLVM_LIKELY(EXPR)
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
Looks at all the uses of the given value Returns the Liveness deduced from the uses of this value Adds all uses that cause the result to be MaybeLive to MaybeLiveRetUses If the result is MaybeLiveUses might be modified but its content should be ignored(since it might not be complete). DeadArgumentEliminationPass
Given that RA is a live propagate it s liveness to any other values it uses(according to Uses). void DeadArgumentEliminationPass
Given that RA is a live value
This file defines the DenseSet and SmallDenseSet classes.
This file contains constants used for implementing Dwarf debug support.
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
This file defines a hash set that can be used to remove duplication of nodes in a graph.
Rewrite Partial Register Uses
static const unsigned MaxDepth
static Register getMemsetValue(Register Val, LLT Ty, MachineIRBuilder &MIB)
static bool shouldLowerMemFuncForSize(const MachineFunction &MF)
static bool isZero(Value *V, const DataLayout &DL, DominatorTree *DT, AssumptionCache *AC)
static Align getPrefTypeAlign(EVT VT, SelectionDAG &DAG)
mir Rename Register Operands
This file declares the MachineConstantPool class which is an abstract constant pool to keep track of ...
unsigned const TargetRegisterInfo * TRI
This file provides utility analysis objects describing memory locations.
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
PowerPC Reduce CR logical Operation
const SmallVectorImpl< MachineOperand > & Cond
Contains matchers for matching SelectionDAG nodes and values.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static uint64_t umul_ov(uint64_t i, uint64_t j, bool &Overflow)
static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo)
Lower the call to 'memset' intrinsic function into a series of store operations.
static std::optional< APInt > FoldValueWithUndef(unsigned Opcode, const APInt &C1, bool IsUndef1, const APInt &C2, bool IsUndef2)
static SDValue FoldSTEP_VECTOR(const SDLoc &DL, EVT VT, SDValue Step, SelectionDAG &DAG)
static void AddNodeIDNode(FoldingSetNodeID &ID, unsigned OpC, SDVTList VTList, ArrayRef< SDValue > OpList)
static SDValue getMemsetStringVal(EVT VT, const SDLoc &dl, SelectionDAG &DAG, const TargetLowering &TLI, const ConstantDataArraySlice &Slice)
getMemsetStringVal - Similar to getMemsetValue.
static cl::opt< bool > EnableMemCpyDAGOpt("enable-memcpy-dag-opt", cl::Hidden, cl::init(true), cl::desc("Gang up loads and stores generated by inlining of memcpy"))
static bool haveNoCommonBitsSetCommutative(SDValue A, SDValue B)
static void AddNodeIDValueTypes(FoldingSetNodeID &ID, SDVTList VTList)
AddNodeIDValueTypes - Value type lists are intern'd so we can represent them solely with their pointe...
static void commuteShuffle(SDValue &N1, SDValue &N2, MutableArrayRef< int > M)
Swaps the values of N1 and N2.
static bool isMemSrcFromConstant(SDValue Src, ConstantDataArraySlice &Slice)
Returns true if memcpy source is constant data.
static SDValue getMemmoveLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo)
static SDValue getMemcpyLoadsAndStores(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Dst, SDValue Src, uint64_t Size, Align Alignment, bool isVol, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo, AAResults *AA)
static void AddNodeIDOpcode(FoldingSetNodeID &ID, unsigned OpC)
AddNodeIDOpcode - Add the node opcode to the NodeID data.
static ISD::CondCode getSetCCInverseImpl(ISD::CondCode Op, bool isIntegerLike)
static bool doNotCSE(SDNode *N)
doNotCSE - Return true if CSE should not be performed for this node.
static cl::opt< int > MaxLdStGlue("ldstmemcpy-glue-max", cl::desc("Number limit for gluing ld/st of memcpy."), cl::Hidden, cl::init(0))
static void AddNodeIDOperands(FoldingSetNodeID &ID, ArrayRef< SDValue > Ops)
AddNodeIDOperands - Various routines for adding operands to the NodeID data.
static SDValue foldCONCAT_VECTORS(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
Try to simplify vector concatenation to an input value, undef, or build vector.
static MachinePointerInfo InferPointerInfo(const MachinePointerInfo &Info, SelectionDAG &DAG, SDValue Ptr, int64_t Offset=0)
InferPointerInfo - If the specified ptr/offset is a frame index, infer a MachinePointerInfo record fr...
static void AddNodeIDCustom(FoldingSetNodeID &ID, const SDNode *N)
If this is an SDNode with special info, add this info to the NodeID data.
static void NewSDValueDbgMsg(SDValue V, StringRef Msg, SelectionDAG *G)
static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs)
makeVTList - Return an instance of the SDVTList struct initialized with the specified members.
static void VerifySDNode(SDNode *N, const TargetLowering *TLI)
VerifySDNode - Check the given SDNode. Aborts if it is invalid.
static void checkForCyclesHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallPtrSetImpl< const SDNode * > &Checked, const llvm::SelectionDAG *DAG)
static void chainLoadsAndStoresForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SmallVector< SDValue, 32 > &OutChains, unsigned From, unsigned To, SmallVector< SDValue, 16 > &OutLoadChains, SmallVector< SDValue, 16 > &OutStoreChains)
static int isSignedOp(ISD::CondCode Opcode)
For an integer comparison, return 1 if the comparison is a signed operation and 2 if the result is an...
static std::optional< APInt > FoldValue(unsigned Opcode, const APInt &C1, const APInt &C2)
static SDValue FoldBUILD_VECTOR(const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops, SelectionDAG &DAG)
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI, unsigned AS)
static Constant * ConstantFold(Instruction *I, const DataLayout &DL, const SmallDenseMap< Value *, Constant * > &ConstantPool)
Try to fold instruction I into a constant.
This file defines the SmallPtrSet class.
This file defines the SmallVector class.
This file describes how to lower LLVM code to machine code.
static std::optional< unsigned > getOpcode(ArrayRef< VPValue * > Values)
Returns the opcode of Values or ~0 if they do not all agree.
static OverflowResult mapOverflowResult(ConstantRange::OverflowResult OR)
Convert ConstantRange OverflowResult into ValueTracking OverflowResult.
static unsigned getSize(unsigned Kind)
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
static APFloat getQNaN(const fltSemantics &Sem, bool Negative=false, const APInt *payload=nullptr)
Factory for QNaN values.
opStatus divide(const APFloat &RHS, roundingMode RM)
void copySign(const APFloat &RHS)
opStatus convert(const fltSemantics &ToSemantics, roundingMode RM, bool *losesInfo)
opStatus subtract(const APFloat &RHS, roundingMode RM)
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
opStatus add(const APFloat &RHS, roundingMode RM)
opStatus convertFromAPInt(const APInt &Input, bool IsSigned, roundingMode RM)
opStatus multiply(const APFloat &RHS, roundingMode RM)
opStatus fusedMultiplyAdd(const APFloat &Multiplicand, const APFloat &Addend, roundingMode RM)
static APFloat getLargest(const fltSemantics &Sem, bool Negative=false)
Returns the largest finite number in the given semantics.
opStatus convertToInteger(MutableArrayRef< integerPart > Input, unsigned int Width, bool IsSigned, roundingMode RM, bool *IsExact) const
static APFloat getInf(const fltSemantics &Sem, bool Negative=false)
Factory for Positive and Negative Infinity.
opStatus mod(const APFloat &RHS)
static APFloat getNaN(const fltSemantics &Sem, bool Negative=false, uint64_t payload=0)
Factory for NaN values.
Class for arbitrary precision integers.
APInt umul_ov(const APInt &RHS, bool &Overflow) const
APInt usub_sat(const APInt &RHS) const
APInt udiv(const APInt &RHS) const
Unsigned division operation.
static APInt getAllOnes(unsigned numBits)
Return an APInt of a specified width with all bits set.
void clearBit(unsigned BitPosition)
Set a given bit to 0.
APInt zext(unsigned width) const
Zero extend to a new width.
static APInt getSignMask(unsigned BitWidth)
Get the SignMask for a specific bit width.
uint64_t getZExtValue() const
Get zero extended value.
void setHighBits(unsigned hiBits)
Set the top hiBits bits.
unsigned popcount() const
Count the number of bits set.
void setBitsFrom(unsigned loBit)
Set the top bits starting from loBit.
APInt getHiBits(unsigned numBits) const
Compute an APInt containing numBits highbits from this APInt.
APInt zextOrTrunc(unsigned width) const
Zero extend or truncate to width.
unsigned getActiveBits() const
Compute the number of active bits in the value.
APInt trunc(unsigned width) const
Truncate to new width.
void setBit(unsigned BitPosition)
Set the given bit to 1 whose position is given as "bitPosition".
APInt abs() const
Get the absolute value.
APInt sadd_sat(const APInt &RHS) const
bool isAllOnes() const
Determine if all bits are set. This is true for zero-width values.
bool ugt(const APInt &RHS) const
Unsigned greater than comparison.
bool isZero() const
Determine if this value is zero, i.e. all bits are clear.
APInt urem(const APInt &RHS) const
Unsigned remainder operation.
unsigned getBitWidth() const
Return the number of bits in the APInt.
bool ult(const APInt &RHS) const
Unsigned less than comparison.
static APInt getSignedMaxValue(unsigned numBits)
Gets maximum signed value of APInt for a specific bit width.
bool isNegative() const
Determine sign of this APInt.
APInt sdiv(const APInt &RHS) const
Signed division function for APInt.
void clearAllBits()
Set every bit to 0.
APInt rotr(unsigned rotateAmt) const
Rotate right by rotateAmt.
APInt reverseBits() const
void ashrInPlace(unsigned ShiftAmt)
Arithmetic right-shift this APInt by ShiftAmt in place.
bool sle(const APInt &RHS) const
Signed less or equal comparison.
unsigned countr_zero() const
Count the number of trailing zero bits.
unsigned getNumSignBits() const
Computes the number of leading bits of this APInt that are equal to its sign bit.
unsigned countl_zero() const
The APInt version of std::countl_zero.
static APInt getSplat(unsigned NewLen, const APInt &V)
Return a value containing V broadcasted over NewLen bits.
static APInt getSignedMinValue(unsigned numBits)
Gets minimum signed value of APInt for a specific bit width.
APInt sshl_sat(const APInt &RHS) const
APInt ushl_sat(const APInt &RHS) const
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
APInt rotl(unsigned rotateAmt) const
Rotate left by rotateAmt.
void insertBits(const APInt &SubBits, unsigned bitPosition)
Insert the bits from a smaller APInt starting at bitPosition.
void clearLowBits(unsigned loBits)
Set bottom loBits bits to 0.
unsigned logBase2() const
APInt uadd_sat(const APInt &RHS) const
APInt ashr(unsigned ShiftAmt) const
Arithmetic right-shift function.
void setAllBits()
Set every bit to 1.
APInt srem(const APInt &RHS) const
Function for signed remainder operation.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool ule(const APInt &RHS) const
Unsigned less or equal comparison.
APInt sext(unsigned width) const
Sign extend to a new width.
void setBits(unsigned loBit, unsigned hiBit)
Set the bits from loBit (inclusive) to hiBit (exclusive) to 1.
APInt shl(unsigned shiftAmt) const
Left-shift function.
bool isSubsetOf(const APInt &RHS) const
This operation checks that all bits set in this APInt are also set in RHS.
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
static APInt getLowBitsSet(unsigned numBits, unsigned loBitsSet)
Constructs an APInt value that has the bottom loBitsSet bits set.
static APInt getZero(unsigned numBits)
Get the '0' value for the specified bit-width.
void setLowBits(unsigned loBits)
Set the bottom loBits bits.
APInt extractBits(unsigned numBits, unsigned bitPosition) const
Return an APInt with the extracted bits [bitPosition,bitPosition+numBits).
bool sge(const APInt &RHS) const
Signed greater or equal comparison.
static APInt getBitsSetFrom(unsigned numBits, unsigned loBit)
Constructs an APInt value that has a contiguous range of bits set.
static APInt getOneBitSet(unsigned numBits, unsigned BitNo)
Return an APInt with exactly one bit set in the result.
void lshrInPlace(unsigned ShiftAmt)
Logical right-shift this APInt by ShiftAmt in place.
APInt lshr(unsigned shiftAmt) const
Logical right-shift function.
bool uge(const APInt &RHS) const
Unsigned greater or equal comparison.
APInt ssub_sat(const APInt &RHS) const
An arbitrary precision integer that knows its signedness.
Recycle small arrays allocated from a BumpPtrAllocator.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
ArrayRef< T > slice(size_t N, size_t M) const
slice(n, m) - Chop off the first N elements of the array, and keep M elements in the array.
This is an SDNode representing atomic operations.
static BaseIndexOffset match(const SDNode *N, const SelectionDAG &DAG)
Parses tree in N for base, index, offset addresses.
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
void clear()
clear - Removes all bits from the bitvector.
bool none() const
none - Returns true if none of the bits are set.
size_type size() const
size - Returns the number of bits in this bitvector.
int64_t getOffset() const
unsigned getTargetFlags() const
const BlockAddress * getBlockAddress() const
The address of a basic block.
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
A "pseudo-class" with methods for operating on BUILD_VECTORs.
bool getConstantRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &RawBitElements, BitVector &UndefElements) const
Extract the raw bit data from a build vector of Undef, Constant or ConstantFP node elements.
static void recastRawBits(bool IsLittleEndian, unsigned DstEltSizeInBits, SmallVectorImpl< APInt > &DstBitElements, ArrayRef< APInt > SrcBitElements, BitVector &DstUndefElements, const BitVector &SrcUndefElements)
Recast bit data SrcBitElements to DstEltSizeInBits wide elements.
bool getRepeatedSequence(const APInt &DemandedElts, SmallVectorImpl< SDValue > &Sequence, BitVector *UndefElements=nullptr) const
Find the shortest repeating sequence of values in the build vector.
ConstantFPSDNode * getConstantFPSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant FP or null if this is not a constant FP splat.
std::optional< std::pair< APInt, APInt > > isConstantSequence() const
If this BuildVector is constant and represents the numerical series "<a, a+n, a+2n,...
SDValue getSplatValue(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted value or a null value if this is not a splat.
bool isConstantSplat(APInt &SplatValue, APInt &SplatUndef, unsigned &SplatBitSize, bool &HasAnyUndefs, unsigned MinSplatBits=0, bool isBigEndian=false) const
Check if this is a constant splat, and if so, find the smallest element size that splats the vector.
ConstantSDNode * getConstantSplatNode(const APInt &DemandedElts, BitVector *UndefElements=nullptr) const
Returns the demanded splatted constant or null if this is not a constant splat.
int32_t getConstantFPSplatPow2ToLog2Int(BitVector *UndefElements, uint32_t BitWidth) const
If this is a constant FP splat and the splatted constant FP is an exact power or 2,...
LLVM_ATTRIBUTE_RETURNS_NONNULL void * Allocate(size_t Size, Align Alignment)
Allocate space at the specified alignment.
void Reset()
Deallocate all but the current slab and reset the current pointer to the beginning of it,...
static bool isValueValidForType(EVT VT, const APFloat &Val)
const APFloat & getValueAPF() const
bool isExactlyValue(double V) const
We don't rely on operator== working on double values, as it returns true for things that are clearly ...
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
unsigned getBitWidth() const
getBitWidth - Return the scalar bitwidth of this constant.
const APInt & getValue() const
Return the constant as an APInt value reference.
bool isMachineConstantPoolEntry() const
This class represents a range of values.
ConstantRange multiply(const ConstantRange &Other) const
Return a new range representing the possible values resulting from a multiplication of a value in thi...
const APInt * getSingleElement() const
If this set contains a single element, return it, otherwise return null.
static ConstantRange fromKnownBits(const KnownBits &Known, bool IsSigned)
Initialize a range based on a known bits constraint.
OverflowResult unsignedSubMayOverflow(const ConstantRange &Other) const
Return whether unsigned sub of the two ranges always/never overflows.
OverflowResult unsignedAddMayOverflow(const ConstantRange &Other) const
Return whether unsigned add of the two ranges always/never overflows.
KnownBits toKnownBits() const
Return known bits for values in this range.
ConstantRange zeroExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getSignedMin() const
Return the smallest signed value contained in the ConstantRange.
OverflowResult unsignedMulMayOverflow(const ConstantRange &Other) const
Return whether unsigned mul of the two ranges always/never overflows.
ConstantRange signExtend(uint32_t BitWidth) const
Return a new range in the specified integer type, which must be strictly larger than the current type...
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
APInt getSignedMax() const
Return the largest signed value contained in the ConstantRange.
OverflowResult
Represents whether an operation on the given constant range is known to always or never overflow.
@ NeverOverflows
Never overflows.
@ AlwaysOverflowsHigh
Always overflows in the direction of signed/unsigned max value.
@ AlwaysOverflowsLow
Always overflows in the direction of signed/unsigned min value.
@ MayOverflow
May or may not overflow.
uint32_t getBitWidth() const
Get the bit width of this ConstantRange.
OverflowResult signedSubMayOverflow(const ConstantRange &Other) const
Return whether signed sub of the two ranges always/never overflows.
uint64_t getZExtValue() const
const APInt & getAPIntValue() const
This is an important base class in LLVM.
Constant * getSplatValue(bool AllowPoison=false) const
If all elements of the vector constant have the same value, return that value.
Constant * getAggregateElement(unsigned Elt) const
For aggregates (struct/array/vector) return the constant that corresponds to the specified element if...
static ExtOps getExtOps(unsigned FromSize, unsigned ToSize, bool Signed)
Returns the ops for a zero- or sign-extension in a DIExpression.
static void appendOffset(SmallVectorImpl< uint64_t > &Ops, int64_t Offset)
Append Ops with operations to apply the Offset.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static const DIExpression * convertToVariadicExpression(const DIExpression *Expr)
If Expr is a non-variadic expression (i.e.
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
Base class for variables.
This class represents an Operation in the Expression.
uint64_t getNumOperands() const
A parsed version of the target data layout string in and methods for querying it.
bool isLittleEndian() const
Layout endianness...
IntegerType * getIntPtrType(LLVMContext &C, unsigned AddressSpace=0) const
Returns an integer type with size at least as big as that of a pointer in the given address space.
Align getABITypeAlign(Type *Ty) const
Returns the minimum ABI-required alignment for the specified type.
unsigned getPointerTypeSizeInBits(Type *) const
Layout pointer size, in bits, based on the type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
Implements a dense probed hash-table based set.
const char * getSymbol() const
unsigned getTargetFlags() const
FoldingSetNodeID - This class is used to gather all the unique data bits of a node.
MachineBasicBlock * MBB
MBB - The current block.
Data structure describing the variable locations in a function.
bool hasOptSize() const
Optimize this function for size (-Os) or minimum size (-Oz).
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
AttributeList getAttributes() const
Return the attribute list for this Function.
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
int64_t getOffset() const
unsigned getAddressSpace() const
unsigned getTargetFlags() const
const GlobalValue * getGlobal() const
bool isThreadLocal() const
If the value is "Thread Local", its value isn't shared by the threads.
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
PointerType * getType() const
Global values are always pointers.
This class is used to form a handle around another node that is persistent and is updated across invo...
static bool compare(const APInt &LHS, const APInt &RHS, ICmpInst::Predicate Pred)
Return result of LHS Pred RHS comparison.
constexpr bool isValid() const
This is an important class for using LLVM in a threaded context.
This SDNode is used for LIFETIME_START/LIFETIME_END values, which indicate the offet and size that ar...
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
TypeSize getValue() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
static MVT getIntegerVT(unsigned BitWidth)
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
Abstract base class for all machine specific constantpool value subclasses.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
bool isFixedObjectIndex(int ObjectIdx) const
Returns true if the specified index corresponds to a fixed stack object.
void setObjectAlignment(int ObjectIdx, Align Alignment)
setObjectAlignment - Change the alignment of the specified stack object.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
Function & getFunction()
Return the LLVM function that this machine code represents.
const LLVMTargetMachine & getTarget() const
getTarget - Return the target machine this machine code is compiled with
A description of a memory reference used in the backend.
LocationSize getSize() const
Return the size in bytes of the memory reference.
bool isNonTemporal() const
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
const MachinePointerInfo & getPointerInfo() const
Flags getFlags() const
Return the raw flags of the source value,.
bool isDereferenceable() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
This class is used to represent an MGATHER node.
This class is used to represent an MLOAD node.
This class is used to represent an MSCATTER node.
This class is used to represent an MSTORE node.
This SDNode is used for target intrinsics that touch memory and need an associated MachineMemOperand.
MemSDNode(unsigned Opc, unsigned Order, const DebugLoc &dl, SDVTList VTs, EVT memvt, MachineMemOperand *MMO)
MachineMemOperand * MMO
Memory reference information.
MachineMemOperand * getMemOperand() const
Return a MachineMemOperand object describing the memory reference performed by operation.
const MachinePointerInfo & getPointerInfo() const
unsigned getRawSubclassData() const
Return the SubclassData value, without HasDebugValue.
EVT getMemoryVT() const
Return the type of the in-memory value.
Representation for a specific memory location.
A Module instance is used to store all the information related to an LLVM module.
Function * getFunction(StringRef Name) const
Look up the specified function in the module symbol table.
MutableArrayRef - Represent a mutable reference to an array (0 or more elements consecutively in memo...
Pass interface - Implemented by all 'passes'.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
unsigned getAddressSpace() const
Return the address space of the Pointer type.
bool isNull() const
Test if the pointer held in the union is null, regardless of which type it is.
Analysis providing profile information.
void Deallocate(SubClass *E)
Deallocate - Release storage for the pointed-to object.
Keeps track of dbg_value information through SDISel.
BumpPtrAllocator & getAlloc()
void add(SDDbgValue *V, bool isParameter)
void erase(const SDNode *Node)
Invalidate all DbgValues attached to the node and remove it from the Node-to-DbgValues map.
ArrayRef< SDDbgValue * > getSDDbgValues(const SDNode *Node) const
Holds the information from a dbg_label node through SDISel.
Holds the information for a single machine location through SDISel; either an SDNode,...
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
@ SDNODE
Value is the result of an expression.
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
const DebugLoc & getDebugLoc() const
unsigned getIROrder() const
This class provides iterator support for SDUse operands that use a specific SDNode.
Represents one node in the SelectionDAG.
ArrayRef< SDUse > ops() const
const APInt & getAsAPIntVal() const
Helper method returns the APInt value of a ConstantSDNode.
void dumprFull(const SelectionDAG *G=nullptr) const
printrFull to dbgs().
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
bool isOnlyUserOf(const SDNode *N) const
Return true if this node is the only use of N.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
static constexpr size_t getMaxNumOperands()
Return the maximum number of operands that a SDNode can hold.
MemSDNodeBitfields MemSDNodeBits
void Profile(FoldingSetNodeID &ID) const
Gather unique data for the node.
bool getHasDebugValue() const
SDNodeFlags getFlags() const
void setNodeId(int Id)
Set unique node id.
void intersectFlagsWith(const SDNodeFlags Flags)
Clear any flags in this node that aren't also set in Flags.
static bool hasPredecessorHelper(const SDNode *N, SmallPtrSetImpl< const SDNode * > &Visited, SmallVectorImpl< const SDNode * > &Worklist, unsigned int MaxSteps=0, bool TopologicalPrune=false)
Returns true if N is a predecessor of any node in Worklist.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
bool use_empty() const
Return true if there are no uses of this node.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
unsigned getNumOperands() const
Return the number of values used by this operation.
const SDValue & getOperand(unsigned Num) const
static bool areOnlyUsersOf(ArrayRef< const SDNode * > Nodes, const SDNode *N)
Return true if all the users of N are contained in Nodes.
use_iterator use_begin() const
Provide iteration support to walk over all uses of an SDNode.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
const APInt & getConstantOperandAPInt(unsigned Num) const
Helper method returns the APInt of a ConstantSDNode operand.
bool hasPredecessor(const SDNode *N) const
Return true if N is a predecessor of this node.
bool hasAnyUseOfValue(unsigned Value) const
Return true if there are any use of the indicated value.
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
bool isUndef() const
Return true if the type of the node type undefined.
bool hasNUsesOfValue(unsigned NUses, unsigned Value) const
Return true if there are exactly NUSES uses of the indicated value.
op_iterator op_end() const
op_iterator op_begin() const
static use_iterator use_end()
void DropOperands()
Release the operands and set this node to have zero operands.
Represents a use of a SDNode.
SDNode * getNode() const
Convenience function for get().getNode().
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
bool hasOneUse() const
Return true if there is exactly one node using value ResNo of Node.
bool isOperandOf(const SDNode *N) const
Return true if this node is an operand of N.
bool reachesChainWithoutSideEffects(SDValue Dest, unsigned Depth=2) const
Return true if this operand (which must be a chain) reaches the specified operand without crossing an...
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
bool use_empty() const
Return true if there are no nodes using value ResNo of Node.
const APInt & getConstantOperandAPInt(unsigned i) const
uint64_t getScalarValueSizeInBits() const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
uint64_t getConstantOperandVal(unsigned i) const
unsigned getOpcode() const
virtual SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo) const
Emit target-specific code that performs a memset.
virtual SDValue EmitTargetCodeForMemmove(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memmove.
virtual SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, Align Alignment, bool isVolatile, bool AlwaysInline, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memcpy.
SDNodeFlags getFlags() const
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
Align getReducedAlign(EVT VT, bool UseABI)
In most cases this function returns the ABI alignment for a given type, except for illegal vector typ...
SDValue getShiftAmountOperand(EVT LHSTy, SDValue Op)
Return the specified value casted to the target's desired shift amount type.
SDValue getExtLoad(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getExtLoadVP(ISD::LoadExtType ExtType, const SDLoc &dl, EVT VT, SDValue Chain, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, MaybeAlign Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsExpanding=false)
SDValue getSplatSourceVector(SDValue V, int &SplatIndex)
If V is a splatted value, return the source vector and its splat index.
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
OverflowKind computeOverflowForUnsignedSub(SDValue N0, SDValue N1) const
Determine if the result of the unsigned sub of 2 nodes can overflow.
unsigned ComputeMaxSignificantBits(SDValue Op, unsigned Depth=0) const
Get the upper bound on bit size for this Value Op as a signed integer.
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
bool isKnownNeverSNaN(SDValue Op, unsigned Depth=0) const
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
SDValue getSelect(const SDLoc &DL, EVT VT, SDValue Cond, SDValue LHS, SDValue RHS)
Helper function to make it easier to build Select's if you just have operands and don't want to check...
SDValue getStackArgumentTokenFactor(SDValue Chain)
Compute a TokenFactor to force all the incoming stack arguments to be loaded from the stack.
const TargetSubtargetInfo & getSubtarget() const
const APInt * getValidMaximumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
void updateDivergence(SDNode *N)
SDValue getSplatValue(SDValue V, bool LegalTypes=false)
If V is a splat vector, return its scalar source operand by extracting that element from the source v...
SDValue FoldSetCC(EVT VT, SDValue N1, SDValue N2, ISD::CondCode Cond, const SDLoc &dl)
Constant fold a setcc to true or false.
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getNeutralElement(unsigned Opcode, const SDLoc &DL, EVT VT, SDNodeFlags Flags)
Get the (commutative) neutral element for the given opcode, if it exists.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getFreeze(SDValue V)
Return a freeze using the SDLoc of the value operand.
SDNode * SelectNodeTo(SDNode *N, unsigned MachineOpc, EVT VT)
These are used for target selectors to mutate the specified node to have the specified return type,...
SelectionDAG(const TargetMachine &TM, CodeGenOptLevel)
SDValue getBitcastedSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDNode * isConstantIntBuildVectorOrConstantInt(SDValue N) const
Test whether the given value is a constant int or similar node.
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDValue makeEquivalentMemoryOrdering(SDValue OldChain, SDValue NewMemOpChain)
If an existing load has uses of its chain, create a token factor node with that chain and the new mem...
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getJumpTableDebugInfo(int JTI, SDValue Chain, const SDLoc &DL)
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
SDValue getSymbolFunctionGlobalAddress(SDValue Op, Function **TargetFunction=nullptr)
Return a GlobalAddress of the function from the current module with name matching the given ExternalS...
SDValue UnrollVectorOp(SDNode *N, unsigned ResNE=0)
Utility function used by legalize and lowering to "unroll" a vector operation by splitting out the sc...
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
OverflowKind
Used to represent the possible overflow behavior of an operation.
bool haveNoCommonBitsSet(SDValue A, SDValue B) const
Return true if A and B have no common bits set.
bool cannotBeOrderedNegativeFP(SDValue Op) const
Test whether the given float value is known to be positive.
bool calculateDivergence(SDNode *N)
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDNode * mutateStrictFPToFP(SDNode *Node)
Mutate the specified strict FP node to its non-strict equivalent, unlinking the node from its chain a...
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getBitcastedZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
void VerifyDAGDivergence()
bool shouldOptForSize() const
SDValue getNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a bitwise NOT operation as (XOR Val, -1).
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
bool isEqualTo(SDValue A, SDValue B) const
Test whether two SDValues are known to compare equal.
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue expandVACopy(SDNode *Node)
Expand the specified ISD::VACOPY node as the Legalize pass would.
SDValue getIndexedMaskedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
APInt computeVectorKnownZeroElements(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
For each demanded element of a vector, see if it is known to be zero.
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
bool NewNodesMustHaveLegalTypes
When true, additional steps are taken to ensure that getConstant() and similar functions return DAG n...
std::pair< EVT, EVT > GetSplitDestVTs(const EVT &VT) const
Compute the VTs needed for the low/hi parts of a type which is split (or expanded) into two not neces...
void salvageDebugInfo(SDNode &N)
To be invoked on an SDNode that is slated to be erased.
SDNode * MorphNodeTo(SDNode *N, unsigned Opc, SDVTList VTs, ArrayRef< SDValue > Ops)
This mutates the specified node to have the specified return type, opcode, and operands.
std::pair< SDValue, SDValue > UnrollVectorOverflowOp(SDNode *N, unsigned ResNE=0)
Like UnrollVectorOp(), but for the [US](ADD|SUB|MUL)O family of opcodes.
allnodes_const_iterator allnodes_begin() const
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getBitcastedAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by first bitcasting (from potentia...
bool isSplatValue(SDValue V, const APInt &DemandedElts, APInt &UndefElts, unsigned Depth=0) const
Test whether V has a splatted value for all the demanded elements.
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
SDValue simplifySelect(SDValue Cond, SDValue TVal, SDValue FVal)
Try to simplify a select/vselect into 1 of its operands or a constant.
SDValue getZeroExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to zero extend the Op value assuming it was the smaller SrcTy value.
const DataLayout & getDataLayout() const
SDNode * isConstantFPBuildVectorOrConstantFP(SDValue N) const
Test whether the given value is a constant FP or similar node.
SDValue expandVAArg(SDNode *Node)
Expand the specified ISD::VAARG node as the Legalize pass would.
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
bool doesNodeExist(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops)
Check if a node exists without modifying its flags.
bool areNonVolatileConsecutiveLoads(LoadSDNode *LD, LoadSDNode *Base, unsigned Bytes, int Dist) const
Return true if loads are next to each other and can be merged.
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
OverflowKind computeOverflowForUnsignedMul(SDValue N0, SDValue N1) const
Determine if the result of the unsigned mul of 2 nodes can overflow.
void copyExtraInfo(SDNode *From, SDNode *To)
Copy extra info associated with one node to another.
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getAllOnesConstant(const SDLoc &DL, EVT VT, bool IsTarget=false, bool IsOpaque=false)
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void clear()
Clear state and free memory necessary to make this SelectionDAG ready to process a new block.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getCommutedVectorShuffle(const ShuffleVectorSDNode &SV)
Returns an ISD::VECTOR_SHUFFLE node semantically equivalent to the shuffle node in input but with swa...
std::pair< SDValue, SDValue > SplitVector(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the vector with EXTRACT_SUBVECTOR using the provided VTs and return the low/high part.
const APInt * getValidShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has a constant or splat constant shift amount that is less than the element b...
SDValue makeStateFunctionCall(unsigned LibFunc, SDValue Ptr, SDValue InChain, const SDLoc &DLoc)
Helper used to make a call to a library function that has one argument of pointer type.
bool isGuaranteedNotToBeUndefOrPoison(SDValue Op, bool PoisonOnly=false, unsigned Depth=0) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getIndexedLoadVP(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
OverflowKind computeOverflowForSignedMul(SDValue N0, SDValue N1) const
Determine if the result of the signed mul of 2 nodes can overflow.
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
bool MaskedValueIsAllOnes(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if '(Op & Mask) == Mask'.
bool SignBitIsZero(SDValue Op, unsigned Depth=0) const
Return true if the sign bit of Op is known to be zero.
SDValue getRegister(unsigned Reg, EVT VT)
void init(MachineFunction &NewMF, OptimizationRemarkEmitter &NewORE, Pass *PassPtr, const TargetLibraryInfo *LibraryInfo, UniformityInfo *UA, ProfileSummaryInfo *PSIin, BlockFrequencyInfo *BFIin, FunctionVarLocs const *FnVarLocs)
Prepare this SelectionDAG to process code in the given MachineFunction.
void RemoveDeadNodes()
This method deletes all unreachable nodes in the SelectionDAG.
void RemoveDeadNode(SDNode *N)
Remove the specified node from the system.
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
bool isConstantValueOfAnyType(SDValue N) const
SDValue getTargetExtractSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand)
A convenience function for creating TargetInstrInfo::EXTRACT_SUBREG nodes.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth=0) const
Test if the given value is known to have exactly one bit set.
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getIndexedStoreVP(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
bool isKnownNeverZero(SDValue Op, unsigned Depth=0) const
Test whether the given SDValue is known to contain non-zero value(s).
SDValue getIndexedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getBoolExtOrTrunc(SDValue Op, const SDLoc &SL, EVT VT, EVT OpVT)
Convert Op, which must be of integer type, to the integer type VT, by using an extension appropriate ...
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
static const fltSemantics & EVTToAPFloatSemantics(EVT VT)
Returns an APFloat semantics tag appropriate for the given type.
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
std::pair< SDValue, SDValue > getStrictFPExtendOrRound(SDValue Op, SDValue Chain, const SDLoc &DL, EVT VT)
Convert Op, which must be a STRICT operation of float type, to the float type VT, by either extending...
std::pair< SDValue, SDValue > SplitEVL(SDValue N, EVT VecVT, const SDLoc &DL)
Split the explicit vector length parameter of a VP operation.
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getVPLogicalNOT(const SDLoc &DL, SDValue Val, SDValue Mask, SDValue EVL, EVT VT)
Create a vector-predicated logical NOT operation as (VP_XOR Val, BooleanOne, Mask,...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
iterator_range< allnodes_iterator > allnodes()
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue WidenVector(const SDValue &N, const SDLoc &DL)
Widen the vector up to the next power of two using INSERT_SUBVECTOR.
bool isKnownNeverZeroFloat(SDValue Op) const
Test whether the given floating point SDValue is known to never be positive or negative zero.
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
ArrayRef< SDDbgValue * > GetDbgValues(const SDNode *SD) const
Get the debug values which reference the given SDNode.
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
OverflowKind computeOverflowForSignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the signed addition of 2 nodes can overflow.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
unsigned AssignTopologicalOrder()
Topological-sort the AllNodes list and a assign a unique node id for each node in the DAG based on th...
ilist< SDNode >::size_type allnodes_size() const
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
bool isKnownNeverNaN(SDValue Op, bool SNaN=false, unsigned Depth=0) const
Test whether the given SDValue (or all elements of it, if it is a vector) is known to never be NaN.
SDValue getIndexedMaskedStore(SDValue OrigStore, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTruncStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, bool IsCompressing=false)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
unsigned ComputeNumSignBits(SDValue Op, unsigned Depth=0) const
Return the number of times the sign bit of the register is replicated into the other bits.
bool MaskedVectorIsZero(SDValue Op, const APInt &DemandedElts, unsigned Depth=0) const
Return true if 'Op' is known to be zero in DemandedElts.
SDValue getBoolConstant(bool V, const SDLoc &DL, EVT VT, EVT OpVT)
Create a true or false constant of type VT using the target's BooleanContent for type OpVT.
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getExtStridedLoadVP(ISD::LoadExtType ExtType, const SDLoc &DL, EVT VT, SDValue Chain, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
bool isBaseWithConstantOffset(SDValue Op) const
Return true if the specified operand is an ISD::ADD with a ConstantSDNode on the right-hand side,...
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
void ReplaceAllUsesOfValueWith(SDValue From, SDValue To)
Replace any uses of From with To, leaving uses of other values produced by From.getNode() alone.
MachineFunction & getMachineFunction() const
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
bool canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, bool PoisonOnly=false, bool ConsiderFlags=true, unsigned Depth=0) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
OverflowKind computeOverflowForUnsignedAdd(SDValue N0, SDValue N1) const
Determine if the result of the unsigned addition of 2 nodes can overflow.
SDValue getSplatBuildVector(EVT VT, const SDLoc &DL, SDValue Op)
Return a splat ISD::BUILD_VECTOR node, consisting of Op splatted to all elements.
SDValue FoldConstantArithmetic(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
SDValue getTruncStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Stride, SDValue Mask, SDValue EVL, EVT SVT, MachineMemOperand *MMO, bool IsCompressing=false)
void canonicalizeCommutativeBinop(unsigned Opcode, SDValue &N1, SDValue &N2) const
Swap N1 and N2 if Opcode is a commutative binary opcode and the canonical form expects the opposite o...
KnownBits computeKnownBits(SDValue Op, unsigned Depth=0) const
Determine which bits of Op are known to be either zero or one and return them in Known.
SDValue getRegisterMask(const uint32_t *RegMask)
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
bool MaskedValueIsZero(SDValue Op, const APInt &Mask, unsigned Depth=0) const
Return true if 'Op & Mask' is known to be zero.
bool isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth=0) const
Test if the given fp value is known to be an integer power-of-2, either positive or negative.
OverflowKind computeOverflowForSignedSub(SDValue N0, SDValue N1) const
Determine if the result of the signed sub of 2 nodes can overflow.
LLVMContext * getContext() const
SDValue simplifyFPBinop(unsigned Opcode, SDValue X, SDValue Y, SDNodeFlags Flags)
Try to simplify a floating-point binary operation into 1 of its operands or a constant.
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
const APInt * getValidMinimumShiftAmountConstant(SDValue V, const APInt &DemandedElts) const
If a SHL/SRA/SRL node V has constant shift amounts that are all less than the element bit-width of th...
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
bool isUndef(unsigned Opcode, ArrayRef< SDValue > Ops)
Return true if the result of this operation is always undefined.
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDNode * UpdateNodeOperands(SDNode *N, SDValue Op)
Mutate the specified node in-place to have the specified operands.
std::pair< EVT, EVT > GetDependentSplitDestVTs(const EVT &VT, const EVT &EnvVT, bool *HiIsEmpty) const
Compute the VTs needed for the low/hi parts of a type, dependent on an enveloping VT that has been sp...
SDValue foldConstantFPMath(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDValue > Ops)
Fold floating-point operations when all operands are constants and/or undefined.
SDNode * getNodeIfExists(unsigned Opcode, SDVTList VTList, ArrayRef< SDValue > Ops, const SDNodeFlags Flags)
Get the specified node if it's already available, or else return NULL.
SDValue FoldSymbolOffset(unsigned Opcode, EVT VT, const GlobalAddressSDNode *GA, const SDNode *N2)
SDValue getIndexedLoad(SDValue OrigLoad, const SDLoc &dl, SDValue Base, SDValue Offset, ISD::MemIndexedMode AM)
SDValue getTargetInsertSubreg(int SRIdx, const SDLoc &DL, EVT VT, SDValue Operand, SDValue Subreg)
A convenience function for creating TargetInstrInfo::INSERT_SUBREG nodes.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
std::pair< SDValue, SDValue > SplitScalar(const SDValue &N, const SDLoc &DL, const EVT &LoVT, const EVT &HiVT)
Split the scalar node with EXTRACT_ELEMENT using the provided VTs and return the low/high part.
SDValue matchBinOpReduction(SDNode *Extract, ISD::NodeType &BinOp, ArrayRef< ISD::NodeType > CandidateBinOps, bool AllowPartials=false)
Match a binop + shuffle pyramid that represents a horizontal reduction over the elements of a vector ...
bool isADDLike(SDValue Op, bool NoWrap=false) const
Return true if the specified operand is an ISD::OR or ISD::XOR node that can be treated as an ISD::AD...
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue simplifyShift(SDValue X, SDValue Y)
Try to simplify a shift into 1 of its operands or a constant.
void transferDbgValues(SDValue From, SDValue To, unsigned OffsetInBits=0, unsigned SizeInBits=0, bool InvalidateDbg=true)
Transfer debug values from one node to another, while optionally generating fragment expressions for ...
SDValue getLogicalNOT(const SDLoc &DL, SDValue Val, EVT VT)
Create a logical NOT operation as (XOR Val, BooleanOne).
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
ilist< SDNode >::iterator allnodes_iterator
This SDNode is used to implement the code generator support for the llvm IR shufflevector instruction...
static bool isSplatMask(const int *Mask, EVT VT)
int getMaskElt(unsigned Idx) const
ArrayRef< int > getMask() const
static void commuteMask(MutableArrayRef< int > Mask)
Change values in a shuffle permute mask assuming the two vector operands have swapped position.
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
bool erase(PtrType Ptr)
erase - If the set contains the specified pointer, remove it and return true, otherwise return false.
size_type count(ConstPtrType Ptr) const
count - Return 1 if the specified pointer is in the set, 0 otherwise.
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
void assign(size_type NumElts, ValueParamT Elt)
reference emplace_back(ArgTypes &&... Args)
void reserve(size_type N)
iterator erase(const_iterator CI)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
This class is used to represent ISD::STORE nodes.
StringRef - Represent a constant reference to a string, i.e.
Information about stack frame layout on the target.
virtual TargetStackID::Value getStackIDForScalableVectors() const
Returns the StackID that scalable vectors should be associated with.
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
Completely target-dependent object reference.
int64_t getOffset() const
unsigned getTargetFlags() const
Provides information about what library functions are available for the current target.
CallingConv::ID getLibcallCallingConv(RTLIB::Libcall Call) const
Get the CallingConv that should be used for the specified libcall.
virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm, Type *Ty) const
Return true if it is beneficial to convert a load of a constant to just the constant itself.
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
const TargetMachine & getTargetMachine() const
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
unsigned getMaxStoresPerMemcpy(bool OptSize) const
Get maximum # of store operations permitted for llvm.memcpy.
virtual bool isCommutativeBinOp(unsigned Opcode) const
Returns true if the opcode is a commutative binary operation.
virtual ISD::NodeType getExtendForAtomicOps() const
Returns how the platform's atomic operations are extended (ZERO_EXTEND, SIGN_EXTEND,...
virtual bool isExtractSubvectorCheap(EVT ResVT, EVT SrcVT, unsigned Index) const
Return true if EXTRACT_SUBVECTOR is cheap for extracting this result type from this source type with ...
virtual bool shallExtractConstSplatVectorElementToStore(Type *VectorTy, unsigned ElemSizeInBits, unsigned &Index) const
Return true if the target shall perform extract vector element and store given that the vector is kno...
virtual bool isTruncateFree(Type *FromTy, Type *ToTy) const
Return true if it's free to truncate a value of type FromTy to type ToTy.
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
BooleanContent getBooleanContents(bool isVec, bool isFloat) const
For targets without i1 registers, this gives the nature of the high-bits of boolean values held in ty...
bool isCondCodeLegal(ISD::CondCode CC, MVT VT) const
Return true if the specified condition code is legal on this target.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
bool isOperationLegal(unsigned Op, EVT VT) const
Return true if the specified operation is legal on this target.
BooleanContent
Enum that describes how the target represents true/false values.
@ ZeroOrOneBooleanContent
@ UndefinedBooleanContent
@ ZeroOrNegativeOneBooleanContent
unsigned getMaxStoresPerMemmove(bool OptSize) const
Get maximum # of store operations permitted for llvm.memmove.
virtual unsigned getMaxGluedStoresPerMemcpy() const
Get maximum # of store operations to be glued together.
Align getMinStackArgumentAlignment() const
Return the minimum stack alignment of an argument.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
const char * getLibcallName(RTLIB::Libcall Call) const
Get the libcall routine name for the specified libcall.
std::vector< ArgListEntry > ArgListTy
virtual bool hasVectorBlend() const
Return true if the target has a vector blend instruction.
unsigned getMaxStoresPerMemset(bool OptSize) const
Get maximum # of store operations permitted for llvm.memset.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual bool isLegalStoreImmediate(int64_t Value) const
Return true if the specified immediate is legal for the value input of a store instruction.
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
static ISD::NodeType getExtendForContent(BooleanContent Content)
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual void computeKnownBitsForFrameIndex(int FIOp, KnownBits &Known, const MachineFunction &MF) const
Determine which of the bits of FrameIndex FIOp are known to be 0.
virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
This method can be implemented by targets that want to expose additional information about sign bits ...
virtual void verifyTargetSDNode(const SDNode *N) const
Check the given SDNode. Aborts if it is invalid.
virtual bool findOptimalMemOpLowering(std::vector< EVT > &MemOps, unsigned Limit, const MemOp &Op, unsigned DstAS, unsigned SrcAS, const AttributeList &FuncAttributes) const
Determines the optimal series of memory ops to replace the memset / memcpy.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual bool isKnownNeverNaNForTargetNode(SDValue Op, const SelectionDAG &DAG, bool SNaN=false, unsigned Depth=0) const
If SNaN is false,.
virtual void computeKnownBitsForTargetNode(const SDValue Op, KnownBits &Known, const APInt &DemandedElts, const SelectionDAG &DAG, unsigned Depth=0) const
Determine which of the bits specified in Mask are known to be either zero or one and return them in t...
virtual bool isSDNodeSourceOfDivergence(const SDNode *N, FunctionLoweringInfo *FLI, UniformityInfo *UA) const
virtual bool isSDNodeAlwaysUniform(const SDNode *N) const
virtual bool isSplatValueForTargetNode(SDValue Op, const APInt &DemandedElts, APInt &UndefElts, const SelectionDAG &DAG, unsigned Depth=0) const
Return true if vector Op has the same value across all DemandedElts, indicating any elements which ma...
virtual bool isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const
Return true if folding a constant offset with the given GlobalAddress is legal.
virtual const Constant * getTargetConstantFromLoad(LoadSDNode *LD) const
This method returns the constant pool value that will be loaded by LD.
virtual bool isGAPlusOffset(SDNode *N, const GlobalValue *&GA, int64_t &Offset) const
Returns true (and the GlobalValue and the offset) if the node is a GlobalAddress + offset.
virtual bool isGuaranteedNotToBeUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, unsigned Depth) const
Return true if this function can prove that Op is never poison and, if PoisonOnly is false,...
virtual bool canCreateUndefOrPoisonForTargetNode(SDValue Op, const APInt &DemandedElts, const SelectionDAG &DAG, bool PoisonOnly, bool ConsiderFlags, unsigned Depth) const
Return true if Op can create undef or poison from non-undef & non-poison operands.
Primary interface to the complete machine description for the target machine.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const SelectionDAGTargetInfo * getSelectionDAGInfo() const
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetLowering * getTargetLowering() const
bool isOSDarwin() const
Is this a "Darwin" OS (macOS, iOS, tvOS, watchOS, XROS, or DriverKit).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
unsigned getScalarSizeInBits() const LLVM_READONLY
If this is a vector type, return the getPrimitiveSizeInBits value for the element type.
static Type * getVoidTy(LLVMContext &C)
static IntegerType * getInt8Ty(LLVMContext &C)
TypeSize getPrimitiveSizeInBits() const LLVM_READONLY
Return the basic size of this type if it is a primitive type.
A Use represents the edge between a Value definition and its users.
This class is used to represent an VP_GATHER node.
This class is used to represent a VP_LOAD node.
This class is used to represent an VP_SCATTER node.
This class is used to represent a VP_STORE node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_LOAD node.
This class is used to represent an EXPERIMENTAL_VP_STRIDED_STORE node.
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
std::pair< iterator, bool > insert(const ValueT &V)
bool contains(const_arg_type_t< ValueT > V) const
Check if the set contains the given element.
constexpr ScalarTy getFixedValue() const
static constexpr bool isKnownLE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr bool isKnownEven() const
A return value of true indicates we know at compile time that the number of elements (vscale * Min) i...
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
static constexpr bool isKnownGE(const FixedOrScalableQuantity &LHS, const FixedOrScalableQuantity &RHS)
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
SmartMutex - A mutex with a compile time constant parameter that indicates whether this mutex should ...
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
APInt mulhu(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on zero-extended operands.
const APInt abdu(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be unsigned.
APInt avgCeilU(const APInt &C1, const APInt &C2)
Compute the ceil of the unsigned average of C1 and C2.
APInt avgFloorU(const APInt &C1, const APInt &C2)
Compute the floor of the unsigned average of C1 and C2.
const APInt abds(const APInt &A, const APInt &B)
Determine the absolute difference of two APInts considered to be signed.
APInt mulhs(const APInt &C1, const APInt &C2)
Performs (2*N)-bit multiplication on sign-extended operands.
APInt ScaleBitMask(const APInt &A, unsigned NewBitWidth, bool MatchAllBits=false)
Splat/Merge neighboring bits to widen/narrow the bitmask represented by.
APInt avgFloorS(const APInt &C1, const APInt &C2)
Compute the floor of the signed average of C1 and C2.
APInt avgCeilS(const APInt &C1, const APInt &C2)
Compute the ceil of the signed average of C1 and C2.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ C
The default llvm calling convention, compatible with C.
CondCode getSetCCInverse(CondCode Operation, bool isIntegerLike)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
CondCode getSetCCAndOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical AND between different comparisons of identical values: ((X op1 Y) & (X...
bool isConstantSplatVectorAllOnes(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are ~0 ...
bool isNON_EXTLoad(const SDNode *N)
Returns true if the specified node is a non-extending load.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ SETCC
SetCC operator - This evaluates to a true value iff the condition is true.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ MDNODE_SDNODE
MDNODE_SDNODE - This is a node that holdes an MDNode*, which is used to reference metadata in the IR.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ FGETSIGN
INT = FGETSIGN(FP) - Return the sign bit of the specified floating point value as an integer 0/1 valu...
@ SMUL_LOHI
SMUL_LOHI/UMUL_LOHI - Multiply two integers of type iN, producing a signed/unsigned value of type i[2...
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ JUMP_TABLE_DEBUG_INFO
JUMP_TABLE_DEBUG_INFO - Jumptable debug info.
@ BSWAP
Byte Swap and Counting operators.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ ADDC
Carry-setting nodes for multiple precision addition and subtraction.
@ FMAD
FMAD - Perform a * b + c, while getting the same result as the separately rounded operations.
@ ADD
Simple integer binary arithmetic operators.
@ LOAD
LOAD and STORE have token chains as their first operand, then the same operands as an LLVM load/store...
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ SIGN_EXTEND_VECTOR_INREG
SIGN_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register sign-extension of the low ...
@ FP16_TO_FP
FP16_TO_FP, FP_TO_FP16 - These operators are used to perform promotions and truncation for half-preci...
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ BUILTIN_OP_END
BUILTIN_OP_END - This must be the last enum value in this list.
@ SRCVALUE
SRCVALUE - This is a node type that holds a Value* that is used to make reference to a value in the L...
@ EH_LABEL
EH_LABEL - Represents a label in mid basic block used to track locations needed for debug and excepti...
@ SIGN_EXTEND
Conversion operators.
@ AVGCEILS
AVGCEILS/AVGCEILU - Rounding averaging add - Add two integers using an integer of type i[N+2],...
@ SCALAR_TO_VECTOR
SCALAR_TO_VECTOR(VAL) - This represents the operation of loading a scalar value into element 0 of the...
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ TargetIndex
TargetIndex - Like a constant pool entry, but with completely target-dependent semantics.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SETCCCARRY
Like SetCC, ops #0 and #1 are the LHS and RHS operands to compare, but op #2 is a boolean indicating ...
@ FNEG
Perform various unary floating-point operations inspired by libm.
@ BR_CC
BR_CC - Conditional branch.
@ SSUBO
Same for subtraction.
@ STEP_VECTOR
STEP_VECTOR(IMM) - Returns a scalable vector whose lanes are comprised of a linear sequence of unsign...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ UNDEF
UNDEF - An undefined node.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ AssertAlign
AssertAlign - These nodes record if a register contains a value that has a known alignment and the tr...
@ BasicBlock
Various leaf nodes.
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ TargetGlobalAddress
TargetGlobalAddress - Like GlobalAddress, but the DAG does no folding or anything else with this node...
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ MULHU
MULHU/MULHS - Multiply high - Multiply two integers of type iN, producing an unsigned/signed value of...
@ SHL
Shift and rotation operations.
@ VECTOR_SHUFFLE
VECTOR_SHUFFLE(VEC1, VEC2) - Returns a vector, of the same type as VEC1/VEC2.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ FMINNUM_IEEE
FMINNUM_IEEE/FMAXNUM_IEEE - Perform floating-point minimumNumber or maximumNumber on two values,...
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ SELECT_CC
Select with condition operator - This selects between a true value and a false value (ops #2 and #3) ...
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ ATOMIC_CMP_SWAP
Val, OUTCHAIN = ATOMIC_CMP_SWAP(INCHAIN, ptr, cmp, swap) For double-word atomic operations: ValLo,...
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ ANY_EXTEND_VECTOR_INREG
ANY_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register any-extension of the low la...
@ SIGN_EXTEND_INREG
SIGN_EXTEND_INREG - This operator atomically performs a SHL/SRA pair to sign extend a small value in ...
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ LIFETIME_START
This corresponds to the llvm.lifetime.
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ UADDO_CARRY
Carry-using nodes for multiple precision addition and subtraction.
@ HANDLENODE
HANDLENODE node - Used as a handle for various purposes.
@ BF16_TO_FP
BF16_TO_FP, FP_TO_BF16 - These operators are used to perform promotions and truncation for bfloat16.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ TargetConstant
TargetConstant* - Like Constant*, but the DAG does not do any folding, simplification,...
@ STRICT_FP_EXTEND
X = STRICT_FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ GET_FPENV_MEM
Gets the current floating-point environment.
@ PSEUDO_PROBE
Pseudo probe for AutoFDO, as a place holder in a basic block to improve the sample counts quality.
@ AVGFLOORS
AVGFLOORS/AVGFLOORU - Averaging add - Add two integers using an integer of type i[N+1],...
@ ADDE
Carry-using nodes for multiple precision addition and subtraction.
@ SPLAT_VECTOR_PARTS
SPLAT_VECTOR_PARTS(SCALAR1, SCALAR2, ...) - Returns a vector with the scalar values joined together a...
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ ZERO_EXTEND_VECTOR_INREG
ZERO_EXTEND_VECTOR_INREG(Vector) - This operator represents an in-register zero-extension of the low ...
@ ADDRSPACECAST
ADDRSPACECAST - This operator converts between pointers of different address spaces.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ VAARG
VAARG - VAARG has four operands: an input chain, a pointer, a SRCVALUE, and the alignment.
@ SHL_PARTS
SHL_PARTS/SRA_PARTS/SRL_PARTS - These operators are used for expanded integer shift operations.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ SET_FPENV_MEM
Sets the current floating point environment.
@ SADDO_CARRY
Carry-using overflow-aware nodes for multiple precision addition and subtraction.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
unsigned getVPForBaseOpcode(unsigned Opcode)
Translate this non-VP Opcode to its corresponding VP Opcode.
bool isBuildVectorOfConstantSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantSDNode or undef.
NodeType getExtForLoadExtType(bool IsFP, LoadExtType)
bool matchUnaryPredicate(SDValue Op, std::function< bool(ConstantSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantSDNode predicate.
bool isZEXTLoad(const SDNode *N)
Returns true if the specified node is a ZEXTLOAD.
bool matchUnaryFpPredicate(SDValue Op, std::function< bool(ConstantFPSDNode *)> Match, bool AllowUndefs=false)
Hook for matching ConstantFPSDNode predicate.
static const int FIRST_TARGET_MEMORY_OPCODE
FIRST_TARGET_MEMORY_OPCODE - Target-specific pre-isel operations which do not reference a specific me...
bool isConstantSplatVectorAllZeros(const SDNode *N, bool BuildVectorOnly=false)
Return true if the specified node is a BUILD_VECTOR or SPLAT_VECTOR where all of the elements are 0 o...
bool isVectorShrinkable(const SDNode *N, unsigned NewEltSize, bool Signed)
Returns true if the specified node is a vector where all elements can be truncated to the specified e...
bool matchUnaryPredicateImpl(SDValue Op, std::function< bool(ConstNodeType *)> Match, bool AllowUndefs=false)
Attempt to match a unary predicate against a scalar/splat constant or every element of a constant BUI...
bool isVPBinaryOp(unsigned Opcode)
Whether this is a vector-predicated binary operation opcode.
CondCode getSetCCInverse(CondCode Operation, EVT Type)
Return the operation corresponding to !(X op Y), where 'op' is a valid SetCC operation.
std::optional< unsigned > getBaseOpcodeForVP(unsigned Opcode, bool hasFPExcept)
Translate this VP Opcode to its corresponding non-VP Opcode.
bool isTrueWhenEqual(CondCode Cond)
Return true if the specified condition returns true if the two operands to the condition are equal.
std::optional< unsigned > getVPMaskIdx(unsigned Opcode)
The operand position of the vector mask.
unsigned getUnorderedFlavor(CondCode Cond)
This function returns 0 if the condition is always false if an operand is a NaN, 1 if the condition i...
std::optional< unsigned > getVPExplicitVectorLengthIdx(unsigned Opcode)
The operand position of the explicit vector length parameter.
bool isEXTLoad(const SDNode *N)
Returns true if the specified node is a EXTLOAD.
bool allOperandsUndef(const SDNode *N)
Return true if the node has at least one operand and all operands of the specified node are ISD::UNDE...
bool isFreezeUndef(const SDNode *N)
Return true if the specified node is FREEZE(UNDEF).
CondCode getSetCCSwappedOperands(CondCode Operation)
Return the operation corresponding to (Y op X) when given the operation for (X op Y).
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
bool isBuildVectorAllZeros(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are 0 or undef.
bool isConstantSplatVector(const SDNode *N, APInt &SplatValue)
Node predicates.
bool matchBinaryPredicate(SDValue LHS, SDValue RHS, std::function< bool(ConstantSDNode *, ConstantSDNode *)> Match, bool AllowUndefs=false, bool AllowTypeMismatch=false)
Attempt to match a binary predicate against a pair of scalar/splat constants or every element of a pa...
bool isVPReduction(unsigned Opcode)
Whether this is a vector-predicated reduction opcode.
MemIndexedMode
MemIndexedMode enum - This enum defines the load / store indexed addressing modes.
bool isBuildVectorOfConstantFPSDNodes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR node of all ConstantFPSDNode or undef.
bool isSEXTLoad(const SDNode *N)
Returns true if the specified node is a SEXTLOAD.
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
bool isBuildVectorAllOnes(const SDNode *N)
Return true if the specified node is a BUILD_VECTOR where all of the elements are ~0 or undef.
NodeType getVecReduceBaseOpcode(unsigned VecReduceOpcode)
Get underlying scalar opcode for VECREDUCE opcode.
LoadExtType
LoadExtType enum - This enum defines the three variants of LOADEXT (load with extension).
bool isVPOpcode(unsigned Opcode)
Whether this is a vector-predicated Opcode.
CondCode getSetCCOrOperation(CondCode Op1, CondCode Op2, EVT Type)
Return the result of a logical OR between different comparisons of identical values: ((X op1 Y) | (X ...
BinaryOp_match< LHS, RHS, Instruction::And > m_And(const LHS &L, const RHS &R)
deferredval_ty< Value > m_Deferred(Value *const &V)
Like m_Specific(), but works if the specific value to match is determined as part of the same match()...
BinaryOp_match< cst_pred_ty< is_zero_int >, ValTy, Instruction::Sub > m_Neg(const ValTy &V)
Matches a 'Neg' as 'sub 0, V'.
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
Libcall
RTLIB::Libcall enum - This enum defines all of the runtime library calls the backend can emit.
Libcall getMEMCPY_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMCPY_ELEMENT_UNORDERED_ATOMIC - Return MEMCPY_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMSET_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMSET_ELEMENT_UNORDERED_ATOMIC - Return MEMSET_ELEMENT_UNORDERED_ATOMIC_* value for the given ele...
Libcall getMEMMOVE_ELEMENT_UNORDERED_ATOMIC(uint64_t ElementSize)
getMEMMOVE_ELEMENT_UNORDERED_ATOMIC - Return MEMMOVE_ELEMENT_UNORDERED_ATOMIC_* value for the given e...
bool sd_match(SDNode *N, const SelectionDAG *DAG, Pattern &&P)
initializer< Ty > init(const Ty &Val)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
std::lock_guard< SmartMutex< mt_only > > SmartScopedLock
This is an optimization pass for GlobalISel generic memory operations.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
bool operator<(int64_t V1, const APSInt &V2)
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
SDValue peekThroughExtractSubvectors(SDValue V)
Return the non-extracted vector source operand of V if it exists.
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
bool isNullConstant(SDValue V)
Returns true if V is a constant integer zero.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isAllOnesOrAllOnesSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant -1 integer or a splatted vector of a constant -1 integer (with...
SDValue getBitwiseNotOperand(SDValue V, SDValue Mask, bool AllowUndefs)
If V is a bitwise not, returns the inverted operand.
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
bool getAlign(const Function &F, unsigned index, unsigned &align)
bool getConstantDataArrayInfo(const Value *V, ConstantDataArraySlice &Slice, unsigned ElementSize, uint64_t Offset=0)
Returns true if the value V is a pointer into a ConstantDataArray.
int bit_width(T Value)
Returns the number of bits needed to represent Value if Value is nonzero.
LLVM_READONLY APFloat maximum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 maximum semantics.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
bool shouldOptimizeForSize(const MachineFunction *MF, ProfileSummaryInfo *PSI, const MachineBlockFrequencyInfo *BFI, PGSOQueryType QueryType=PGSOQueryType::Other)
Returns true if machine function MF is suggested to be size-optimized based on the profile.
iterator_range< early_inc_iterator_impl< detail::IterOfRange< RangeT > > > make_early_inc_range(RangeT &&Range)
Make a range that does early increment to allow mutation of the underlying range without disrupting i...
bool isNullOrNullSplat(const MachineInstr &MI, const MachineRegisterInfo &MRI, bool AllowUndefs=false)
Return true if the value is a constant 0 integer or a splatted vector of a constant 0 integer (with n...
bool isMinSignedConstant(SDValue V)
Returns true if V is a constant min signed integer value.
ConstantFPSDNode * isConstOrConstSplatFP(SDValue N, bool AllowUndefs=false)
Returns the SDNode if it is a constant splat BuildVector or constant float.
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
APFloat frexp(const APFloat &X, int &Exp, APFloat::roundingMode RM)
Equivalent of C standard library function.
static Error getOffset(const SymbolRef &Sym, SectionRef Sec, uint64_t &Result)
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
bool getShuffleDemandedElts(int SrcWidth, ArrayRef< int > Mask, const APInt &DemandedElts, APInt &DemandedLHS, APInt &DemandedRHS, bool AllowUndefElts=false)
Transform a shuffle mask's output demanded element mask into demanded element masks for the 2 operand...
LLVM_READONLY APFloat maxnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 maximumNumber semantics.
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
bool isBitwiseNot(SDValue V, bool AllowUndefs=false)
Returns true if V is a bitwise not operation.
constexpr bool isPowerOf2_32(uint32_t Value)
Return true if the argument is a power of two > 0.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
void checkForCycles(const SelectionDAG *DAG, bool force=false)
void sort(IteratorTy Start, IteratorTy End)
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
SDValue peekThroughTruncates(SDValue V)
Return the non-truncated source operand of V if it exists.
bool none_of(R &&Range, UnaryPredicate P)
Provide wrappers to std::none_of which take ranges instead of having to pass begin/end explicitly.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
SDValue peekThroughOneUseBitcasts(SDValue V)
Return the non-bitcasted and one-use source operand of V if it exists.
CodeGenOptLevel
Code generation optimization level.
bool isOneOrOneSplat(SDValue V, bool AllowUndefs=false)
Return true if the value is a constant 1 integer or a splatted vector of a constant 1 integer (with n...
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
LLVM_READONLY APFloat minnum(const APFloat &A, const APFloat &B)
Implements IEEE-754 2019 minimumNumber semantics.
@ Mul
Product of integers.
void computeKnownBits(const Value *V, KnownBits &Known, const DataLayout &DL, unsigned Depth=0, AssumptionCache *AC=nullptr, const Instruction *CxtI=nullptr, const DominatorTree *DT=nullptr, bool UseInstrInfo=true)
Determine which bits of V are known to be either zero or one and return them in the KnownZero/KnownOn...
DWARFExpression::Operation Op
ConstantSDNode * isConstOrConstSplat(SDValue N, bool AllowUndefs=false, bool AllowTruncation=false)
Returns the SDNode if it is a constant splat BuildVector or constant int.
OutputIt copy(R &&Range, OutputIt Out)
constexpr unsigned BitWidth
bool isOneConstant(SDValue V)
Returns true if V is a constant integer one.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isNullFPConstant(SDValue V)
Returns true if V is an FP constant with a value of positive zero.
constexpr int64_t SignExtend64(uint64_t x)
Sign-extend the number in the bottom B bits of X to a 64-bit integer.
unsigned Log2(Align A)
Returns the log2 of the alignment.
void computeKnownBitsFromRangeMetadata(const MDNode &Ranges, KnownBits &Known)
Compute known bits from the range metadata.
LLVM_READONLY APFloat minimum(const APFloat &A, const APFloat &B)
Implements IEEE 754-2019 minimum semantics.
bool isNeutralConstant(unsigned Opc, SDNodeFlags Flags, SDValue V, unsigned OperandNo)
Returns true if V is a neutral element of Opc with Flags.
bool isAllOnesConstant(SDValue V)
Returns true if V is an integer constant with all bits set.
constexpr uint64_t NextPowerOf2(uint64_t A)
Returns the next power of two (in 64-bits) that is strictly greater than A.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
MDNode * TBAAStruct
The tag for type-based alias analysis (tbaa struct).
MDNode * TBAA
The tag for type-based alias analysis.
static const fltSemantics & IEEEsingle() LLVM_READNONE
cmpResult
IEEE-754R 5.11: Floating Point Comparison Relations.
static constexpr roundingMode rmTowardNegative
static constexpr roundingMode rmNearestTiesToEven
static constexpr roundingMode rmTowardZero
static const fltSemantics & IEEEquad() LLVM_READNONE
static const fltSemantics & IEEEdouble() LLVM_READNONE
static const fltSemantics & IEEEhalf() LLVM_READNONE
static constexpr roundingMode rmTowardPositive
static const fltSemantics & BFloat() LLVM_READNONE
opStatus
IEEE-754R 7: Default exception handling.
This struct is a compact representation of a valid (non-zero power of two) alignment.
Represents offset+length into a ConstantDataArray.
uint64_t Length
Length of the slice.
uint64_t Offset
Slice starts at this Offset.
void move(uint64_t Delta)
Moves the Offset and adjusts Length accordingly.
const ConstantDataArray * Array
ConstantDataArray pointer.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool isSimple() const
Test if the given EVT is simple (as opposed to being extended).
intptr_t getRawBits() const
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
bool bitsEq(EVT VT) const
Return true if this has the same number of bits as VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isExtended() const
Test if the given EVT is extended (as opposed to being simple).
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
bool bitsLE(EVT VT) const
Return true if this has no more bits than VT.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
static KnownBits makeConstant(const APInt &C)
Create known bits from a known constant.
KnownBits sextInReg(unsigned SrcBitWidth) const
Return known bits for a in-register sign extension of the value we're tracking.
static KnownBits mulhu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from zero-extended multiply-hi.
unsigned countMinSignBits() const
Returns the number of times the sign bit is replicated into the other bits.
static KnownBits smax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smax(LHS, RHS).
bool isNonNegative() const
Returns true if this value is known to be non-negative.
bool isZero() const
Returns true if value is all zero.
void makeNonNegative()
Make this value non-negative.
static KnownBits usub_sat(const KnownBits &LHS, const KnownBits &RHS)
Compute knownbits resulting from llvm.usub.sat(LHS, RHS)
unsigned countMinTrailingZeros() const
Returns the minimum number of trailing zero bits.
static KnownBits ashr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for ashr(LHS, RHS).
static KnownBits urem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for urem(LHS, RHS).
bool isUnknown() const
Returns true if we don't know any bits.
unsigned countMaxTrailingZeros() const
Returns the maximum number of trailing zero bits possible.
static std::optional< bool > ne(const KnownBits &LHS, const KnownBits &RHS)
Determine if these known bits always give the same ICMP_NE result.
void makeNegative()
Make this value negative.
KnownBits trunc(unsigned BitWidth) const
Return known bits for a truncation of the value we're tracking.
KnownBits byteSwap() const
bool hasConflict() const
Returns true if there is conflicting information.
unsigned countMaxPopulation() const
Returns the maximum number of bits that could be one.
void setAllZero()
Make all bits known to be zero and discard any previous information.
KnownBits reverseBits() const
KnownBits concat(const KnownBits &Lo) const
Concatenate the bits from Lo onto the bottom of *this.
unsigned getBitWidth() const
Get the bit width of this value.
static KnownBits umax(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umax(LHS, RHS).
KnownBits zext(unsigned BitWidth) const
Return known bits for a zero extension of the value we're tracking.
void resetAll()
Resets the known state of all bits.
KnownBits unionWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for either this or RHS or both.
static KnownBits lshr(const KnownBits &LHS, const KnownBits &RHS, bool ShAmtNonZero=false, bool Exact=false)
Compute known bits for lshr(LHS, RHS).
bool isNonZero() const
Returns true if this value is known to be non-zero.
static KnownBits abdu(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for abdu(LHS, RHS).
KnownBits extractBits(unsigned NumBits, unsigned BitPosition) const
Return a subset of the known bits from [bitPosition,bitPosition+numBits).
KnownBits intersectWith(const KnownBits &RHS) const
Returns KnownBits information that is known to be true for both this and RHS.
KnownBits sext(unsigned BitWidth) const
Return known bits for a sign extension of the value we're tracking.
static KnownBits computeForSubBorrow(const KnownBits &LHS, KnownBits RHS, const KnownBits &Borrow)
Compute known bits results from subtracting RHS from LHS with 1-bit Borrow.
KnownBits zextOrTrunc(unsigned BitWidth) const
Return known bits for a zero extension or truncation of the value we're tracking.
APInt getMaxValue() const
Return the maximal unsigned value possible given these KnownBits.
static KnownBits abds(KnownBits LHS, KnownBits RHS)
Compute known bits for abds(LHS, RHS).
static KnownBits smin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for smin(LHS, RHS).
static KnownBits mulhs(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits from sign-extended multiply-hi.
static KnownBits srem(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for srem(LHS, RHS).
static KnownBits udiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for udiv(LHS, RHS).
static KnownBits computeForAddSub(bool Add, bool NSW, bool NUW, const KnownBits &LHS, const KnownBits &RHS)
Compute known bits resulting from adding LHS and RHS.
bool isStrictlyPositive() const
Returns true if this value is known to be positive.
static KnownBits sdiv(const KnownBits &LHS, const KnownBits &RHS, bool Exact=false)
Compute known bits for sdiv(LHS, RHS).
static bool haveNoCommonBitsSet(const KnownBits &LHS, const KnownBits &RHS)
Return true if LHS and RHS have no common bits set.
bool isNegative() const
Returns true if this value is known to be negative.
static KnownBits computeForAddCarry(const KnownBits &LHS, const KnownBits &RHS, const KnownBits &Carry)
Compute known bits resulting from adding LHS, RHS and a 1-bit Carry.
unsigned countMaxLeadingZeros() const
Returns the maximum number of leading zero bits possible.
void insertBits(const KnownBits &SubBits, unsigned BitPosition)
Insert the bits from a smaller known bits starting at bitPosition.
static KnownBits mul(const KnownBits &LHS, const KnownBits &RHS, bool NoUndefSelfMultiply=false)
Compute known bits resulting from multiplying LHS and RHS.
KnownBits anyext(unsigned BitWidth) const
Return known bits for an "any" extension of the value we're tracking, where we don't know anything ab...
KnownBits abs(bool IntMinIsPoison=false) const
Compute known bits for the absolute value.
static KnownBits shl(const KnownBits &LHS, const KnownBits &RHS, bool NUW=false, bool NSW=false, bool ShAmtNonZero=false)
Compute known bits for shl(LHS, RHS).
static KnownBits umin(const KnownBits &LHS, const KnownBits &RHS)
Compute known bits for umin(LHS, RHS).
This class contains a discriminated union of information about pointers in memory operands,...
bool isDereferenceable(unsigned Size, LLVMContext &C, const DataLayout &DL) const
Return true if memory region [V, V+Offset+Size) is known to be dereferenceable.
unsigned getAddrSpace() const
Return the LLVM IR address space number that this pointer points into.
PointerUnion< const Value *, const PseudoSourceValue * > V
This is the IR pointer value for the access, or it is null if unknown.
MachinePointerInfo getWithOffset(int64_t O) const
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
static MemOp Set(uint64_t Size, bool DstAlignCanChange, Align DstAlign, bool IsZeroMemset, bool IsVolatile)
static MemOp Copy(uint64_t Size, bool DstAlignCanChange, Align DstAlign, Align SrcAlign, bool IsVolatile, bool MemcpyStrSrc=false)
These are IR-level optimization flags that may be propagated to SDNodes.
void intersectWith(const SDNodeFlags Flags)
Clear any flags in this flag set that aren't also set in Flags.
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
Clients of various APIs that cause global effects on the DAG can optionally implement this interface.
DAGUpdateListener *const Next
virtual void NodeDeleted(SDNode *N, SDNode *E)
The node N that was deleted and, if E is not null, an equivalent node E that replaced it.
virtual void NodeInserted(SDNode *N)
The node N that was inserted.
virtual void NodeUpdated(SDNode *N)
The node N that was updated.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setLibCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList)
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setChain(SDValue InChain)