79#include "llvm/IR/IntrinsicsAArch64.h"
80#include "llvm/IR/IntrinsicsAMDGPU.h"
81#include "llvm/IR/IntrinsicsWebAssembly.h"
113using namespace PatternMatch;
114using namespace SwitchCG;
116#define DEBUG_TYPE "isel"
124 cl::desc(
"Insert the experimental `assertalign` node."),
129 cl::desc(
"Generate low-precision inline sequences "
130 "for some float libcalls"),
136 cl::desc(
"Set the case probability threshold for peeling the case from a "
137 "switch statement. A value greater than 100 will void this "
157 const SDValue *Parts,
unsigned NumParts,
160 std::optional<CallingConv::ID>
CC);
169 unsigned NumParts,
MVT PartVT,
EVT ValueVT,
const Value *V,
171 std::optional<CallingConv::ID>
CC = std::nullopt,
172 std::optional<ISD::NodeType> AssertOp = std::nullopt) {
176 PartVT, ValueVT,
CC))
183 assert(NumParts > 0 &&
"No parts to assemble!");
194 unsigned RoundBits = PartBits * RoundParts;
195 EVT RoundVT = RoundBits == ValueBits ?
201 if (RoundParts > 2) {
205 PartVT, HalfVT, V, InChain);
216 if (RoundParts < NumParts) {
218 unsigned OddParts = NumParts - RoundParts;
221 OddVT, V, InChain,
CC);
238 assert(ValueVT ==
EVT(MVT::ppcf128) && PartVT == MVT::f64 &&
249 !PartVT.
isVector() &&
"Unexpected split");
261 if (PartEVT == ValueVT)
265 ValueVT.
bitsLT(PartEVT)) {
278 if (ValueVT.
bitsLT(PartEVT)) {
283 Val = DAG.
getNode(*AssertOp,
DL, PartEVT, Val,
298 llvm::Attribute::StrictFP)) {
300 DAG.
getVTList(ValueVT, MVT::Other), InChain, Val,
312 if (PartEVT == MVT::x86mmx && ValueVT.
isInteger() &&
313 ValueVT.
bitsLT(PartEVT)) {
322 const Twine &ErrMsg) {
323 const Instruction *
I = dyn_cast_or_null<Instruction>(V);
327 const char *AsmError =
", possible invalid constraint for vector type";
328 if (
const CallInst *CI = dyn_cast<CallInst>(
I))
329 if (CI->isInlineAsm())
341 const SDValue *Parts,
unsigned NumParts,
344 std::optional<CallingConv::ID> CallConv) {
346 assert(NumParts > 0 &&
"No parts to assemble!");
347 const bool IsABIRegCopy = CallConv.has_value();
356 unsigned NumIntermediates;
361 *DAG.
getContext(), *CallConv, ValueVT, IntermediateVT,
362 NumIntermediates, RegisterVT);
366 NumIntermediates, RegisterVT);
369 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
371 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
374 "Part type sizes don't match!");
378 if (NumIntermediates == NumParts) {
381 for (
unsigned i = 0; i != NumParts; ++i)
383 V, InChain, CallConv);
384 }
else if (NumParts > 0) {
387 assert(NumParts % NumIntermediates == 0 &&
388 "Must expand into a divisible number of parts!");
389 unsigned Factor = NumParts / NumIntermediates;
390 for (
unsigned i = 0; i != NumIntermediates; ++i)
392 IntermediateVT, V, InChain, CallConv);
407 DL, BuiltVectorTy, Ops);
413 if (PartEVT == ValueVT)
429 "Cannot narrow, it would be a lossy transformation");
435 if (PartEVT == ValueVT)
460 }
else if (ValueVT.
bitsLT(PartEVT)) {
469 *DAG.
getContext(), V,
"non-trivial scalar-to-vector conversion");
500 std::optional<CallingConv::ID> CallConv);
507 unsigned NumParts,
MVT PartVT,
const Value *V,
508 std::optional<CallingConv::ID> CallConv = std::nullopt,
522 unsigned OrigNumParts = NumParts;
524 "Copying to an illegal type!");
530 EVT PartEVT = PartVT;
531 if (PartEVT == ValueVT) {
532 assert(NumParts == 1 &&
"No-op copy with multiple parts!");
541 assert(NumParts == 1 &&
"Do not know what to promote to!");
552 "Unknown mismatch!");
554 Val = DAG.
getNode(ExtendKind,
DL, ValueVT, Val);
555 if (PartVT == MVT::x86mmx)
560 assert(NumParts == 1 && PartEVT != ValueVT);
566 "Unknown mismatch!");
569 if (PartVT == MVT::x86mmx)
576 "Failed to tile the value with PartVT!");
579 if (PartEVT != ValueVT) {
581 "scalar-to-vector conversion failed");
590 if (NumParts & (NumParts - 1)) {
593 "Do not know what to expand to!");
595 unsigned RoundBits = RoundParts * PartBits;
596 unsigned OddParts = NumParts - RoundParts;
605 std::reverse(Parts + RoundParts, Parts + NumParts);
607 NumParts = RoundParts;
619 for (
unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
620 for (
unsigned i = 0; i < NumParts; i += StepSize) {
621 unsigned ThisBits = StepSize * PartBits / 2;
624 SDValue &Part1 = Parts[i+StepSize/2];
631 if (ThisBits == PartBits && ThisVT != PartVT) {
639 std::reverse(Parts, Parts + OrigNumParts);
656 if (ElementCount::isKnownLE(PartNumElts, ValueNumElts) ||
661 if (ValueEVT == MVT::bf16 && PartEVT == MVT::f16) {
663 "Cannot widen to illegal type");
666 }
else if (PartEVT != ValueEVT) {
681 Ops.
append((PartNumElts - ValueNumElts).getFixedValue(), EltUndef);
692 std::optional<CallingConv::ID> CallConv) {
696 const bool IsABIRegCopy = CallConv.has_value();
699 EVT PartEVT = PartVT;
700 if (PartEVT == ValueVT) {
719 TargetLowering::TypeWidenVector) {
737 "lossy conversion of vector to scalar type");
752 unsigned NumIntermediates;
756 *DAG.
getContext(), *CallConv, ValueVT, IntermediateVT, NumIntermediates,
761 NumIntermediates, RegisterVT);
764 assert(NumRegs == NumParts &&
"Part count doesn't match vector breakdown!");
766 assert(RegisterVT == PartVT &&
"Part type doesn't match vector breakdown!");
769 "Mixing scalable and fixed vectors when copying in parts");
771 std::optional<ElementCount> DestEltCnt;
781 if (ValueVT == BuiltVectorTy) {
805 for (
unsigned i = 0; i != NumIntermediates; ++i) {
820 if (NumParts == NumIntermediates) {
823 for (
unsigned i = 0; i != NumParts; ++i)
825 }
else if (NumParts > 0) {
828 assert(NumIntermediates != 0 &&
"division by zero");
829 assert(NumParts % NumIntermediates == 0 &&
830 "Must expand into a divisible number of parts!");
831 unsigned Factor = NumParts / NumIntermediates;
832 for (
unsigned i = 0; i != NumIntermediates; ++i)
839 EVT valuevt, std::optional<CallingConv::ID>
CC)
840 : ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs),
841 RegCount(1, regs.
size()), CallConv(
CC) {}
845 std::optional<CallingConv::ID>
CC) {
859 for (
unsigned i = 0; i != NumRegs; ++i)
861 RegVTs.push_back(RegisterVT);
890 for (
unsigned i = 0; i != NumRegs; ++i) {
896 *Glue =
P.getValue(2);
899 Chain =
P.getValue(1);
928 EVT FromVT(MVT::Other);
932 }
else if (NumSignBits > 1) {
940 assert(FromVT != MVT::Other);
946 RegisterVT, ValueVT, V, Chain,
CallConv);
976 NumParts, RegisterVT, V,
CallConv, ExtendKind);
982 for (
unsigned i = 0; i != NumRegs; ++i) {
994 if (NumRegs == 1 || Glue)
1005 Chain = Chains[NumRegs-1];
1011 unsigned MatchingIdx,
const SDLoc &dl,
1013 std::vector<SDValue> &Ops)
const {
1018 Flag.setMatchingOp(MatchingIdx);
1027 Flag.setRegClass(RC->
getID());
1038 "No 1:1 mapping from clobbers to regs?");
1041 for (
unsigned I = 0, E =
ValueVTs.size();
I != E; ++
I) {
1046 "If we clobbered the stack pointer, MFI should know about it.");
1055 for (
unsigned i = 0; i != NumRegs; ++i) {
1057 unsigned TheReg =
Regs[Reg++];
1068 unsigned RegCount = std::get<0>(CountAndVT);
1069 MVT RegisterVT = std::get<1>(CountAndVT);
1093 UnusedArgNodeMap.clear();
1095 PendingExports.clear();
1096 PendingConstrainedFP.clear();
1097 PendingConstrainedFPStrict.clear();
1105 DanglingDebugInfoMap.clear();
1112 if (Pending.
empty())
1118 unsigned i = 0, e = Pending.
size();
1119 for (; i != e; ++i) {
1120 assert(Pending[i].getNode()->getNumOperands() > 1);
1121 if (Pending[i].getNode()->getOperand(0) == Root)
1129 if (Pending.
size() == 1)
1148 PendingConstrainedFP.size() +
1149 PendingConstrainedFPStrict.size());
1151 PendingConstrainedFP.end());
1152 PendingLoads.append(PendingConstrainedFPStrict.begin(),
1153 PendingConstrainedFPStrict.end());
1154 PendingConstrainedFP.clear();
1155 PendingConstrainedFPStrict.clear();
1162 PendingExports.append(PendingConstrainedFPStrict.begin(),
1163 PendingConstrainedFPStrict.end());
1164 PendingConstrainedFPStrict.clear();
1165 return updateRoot(PendingExports);
1172 assert(Variable &&
"Missing variable");
1179 <<
"dbg_declare: Dropping debug info (bad/undef/unused-arg address)\n");
1186 if (!
N.getNode() && isa<Argument>(
Address))
1194 auto *FINode = dyn_cast<FrameIndexSDNode>(
N.getNode());
1195 if (IsParameter && FINode) {
1198 true,
DL, SDNodeOrder);
1199 }
else if (isa<Argument>(
Address)) {
1203 FuncArgumentDbgValueKind::Declare,
N);
1207 true,
DL, SDNodeOrder);
1214 FuncArgumentDbgValueKind::Declare,
N)) {
1216 <<
" (could not emit func-arg dbg_value)\n");
1228 for (
auto It = FnVarLocs->locs_begin(&
I),
End = FnVarLocs->locs_end(&
I);
1230 auto *Var = FnVarLocs->getDILocalVariable(It->VariableID);
1232 if (It->Values.isKillLocation(It->Expr)) {
1238 It->Values.hasArgList())) {
1240 for (
Value *V : It->Values.location_ops())
1243 FnVarLocs->getDILocalVariable(It->VariableID),
1244 It->Expr, Vals.
size() > 1, It->DL, SDNodeOrder);
1260 for (
DbgRecord &DR :
I.getDbgRecordRange()) {
1262 assert(DLR->getLabel() &&
"Missing label");
1264 DAG.
getDbgLabel(DLR->getLabel(), DLR->getDebugLoc(), SDNodeOrder);
1269 if (SkipDbgVariableRecords)
1279 LLVM_DEBUG(
dbgs() <<
"SelectionDAG visiting dbg_declare: " << DVR
1288 if (Values.
empty()) {
1297 [](
Value *V) {
return !V || isa<UndefValue>(V); })) {
1305 SDNodeOrder, IsVariadic)) {
1316 if (
I.isTerminator()) {
1317 HandlePHINodesInSuccessorBlocks(
I.getParent());
1321 if (!isa<DbgInfoIntrinsic>(
I))
1327 bool NodeInserted =
false;
1328 std::unique_ptr<SelectionDAG::DAGNodeInsertedListener> InsertedListener;
1329 MDNode *PCSectionsMD =
I.getMetadata(LLVMContext::MD_pcsections);
1330 MDNode *MMRA =
I.getMetadata(LLVMContext::MD_mmra);
1331 if (PCSectionsMD || MMRA) {
1332 InsertedListener = std::make_unique<SelectionDAG::DAGNodeInsertedListener>(
1333 DAG, [&](
SDNode *) { NodeInserted =
true; });
1339 !isa<GCStatepointInst>(
I))
1343 if (PCSectionsMD || MMRA) {
1344 auto It = NodeMap.find(&
I);
1345 if (It != NodeMap.end()) {
1350 }
else if (NodeInserted) {
1353 errs() <<
"warning: loosing !pcsections and/or !mmra metadata ["
1354 <<
I.getModule()->getName() <<
"]\n";
1363void SelectionDAGBuilder::visitPHI(
const PHINode &) {
1373#define HANDLE_INST(NUM, OPCODE, CLASS) \
1374 case Instruction::OPCODE: visit##OPCODE((const CLASS&)I); break;
1375#include "llvm/IR/Instruction.def"
1387 for (
const Value *V : Values) {
1412 DanglingDebugInfoMap[Values[0]].emplace_back(Var, Expr,
DL, Order);
1417 auto isMatchingDbgValue = [&](DanglingDebugInfo &DDI) {
1418 DIVariable *DanglingVariable = DDI.getVariable();
1420 if (DanglingVariable == Variable && Expr->
fragmentsOverlap(DanglingExpr)) {
1422 << printDDI(
nullptr, DDI) <<
"\n");
1428 for (
auto &DDIMI : DanglingDebugInfoMap) {
1429 DanglingDebugInfoVector &DDIV = DDIMI.second;
1433 for (
auto &DDI : DDIV)
1434 if (isMatchingDbgValue(DDI))
1437 erase_if(DDIV, isMatchingDbgValue);
1445 auto DanglingDbgInfoIt = DanglingDebugInfoMap.find(V);
1446 if (DanglingDbgInfoIt == DanglingDebugInfoMap.end())
1449 DanglingDebugInfoVector &DDIV = DanglingDbgInfoIt->second;
1450 for (
auto &DDI : DDIV) {
1453 unsigned DbgSDNodeOrder = DDI.getSDNodeOrder();
1457 "Expected inlined-at fields to agree");
1466 if (!EmitFuncArgumentDbgValue(V, Variable, Expr,
DL,
1467 FuncArgumentDbgValueKind::Value, Val)) {
1469 << printDDI(V, DDI) <<
"\n");
1476 <<
"changing SDNodeOrder from " << DbgSDNodeOrder <<
" to "
1477 << ValSDNodeOrder <<
"\n");
1478 SDV = getDbgValue(Val, Variable, Expr,
DL,
1479 std::max(DbgSDNodeOrder, ValSDNodeOrder));
1484 <<
" in EmitFuncArgumentDbgValue\n");
1486 LLVM_DEBUG(
dbgs() <<
"Dropping debug info for " << printDDI(V, DDI)
1498 DanglingDebugInfo &DDI) {
1503 const Value *OrigV = V;
1507 unsigned SDOrder = DDI.getSDNodeOrder();
1511 bool StackValue =
true;
1520 while (isa<Instruction>(V)) {
1521 const Instruction &VAsInst = *cast<const Instruction>(V);
1536 if (!AdditionalValues.
empty())
1546 dbgs() <<
"Salvaged debug location info for:\n " << *Var <<
"\n"
1547 << *OrigV <<
"\nBy stripping back to:\n " << *V <<
"\n");
1555 assert(OrigV &&
"V shouldn't be null");
1560 << printDDI(OrigV, DDI) <<
"\n");
1577 unsigned Order,
bool IsVariadic) {
1582 if (visitEntryValueDbgValue(Values, Var, Expr, DbgLoc))
1587 for (
const Value *V : Values) {
1589 if (isa<ConstantInt>(V) || isa<ConstantFP>(V) || isa<UndefValue>(V) ||
1590 isa<ConstantPointerNull>(V)) {
1596 if (
auto *CE = dyn_cast<ConstantExpr>(V))
1597 if (CE->getOpcode() == Instruction::IntToPtr) {
1604 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1615 if (!
N.getNode() && isa<Argument>(V))
1616 N = UnusedArgNodeMap[V];
1620 EmitFuncArgumentDbgValue(V, Var, Expr, DbgLoc,
1621 FuncArgumentDbgValueKind::Value,
N))
1623 if (
auto *FISDN = dyn_cast<FrameIndexSDNode>(
N.getNode())) {
1648 bool IsParamOfFunc =
1658 unsigned Reg = VMI->second;
1662 V->getType(), std::nullopt);
1668 unsigned BitsToDescribe = 0;
1670 BitsToDescribe = *VarSize;
1672 BitsToDescribe = Fragment->SizeInBits;
1675 if (
Offset >= BitsToDescribe)
1678 unsigned RegisterSize = RegAndSize.second;
1679 unsigned FragmentSize = (
Offset + RegisterSize > BitsToDescribe)
1680 ? BitsToDescribe -
Offset
1683 Expr,
Offset, FragmentSize);
1687 Var, *FragmentExpr, RegAndSize.first,
false, DbgLoc, SDNodeOrder);
1706 SDNodeOrder, IsVariadic);
1713 for (
auto &Pair : DanglingDebugInfoMap)
1714 for (
auto &DDI : Pair.second)
1746 if (
N.getNode())
return N;
1788 if (
const Constant *
C = dyn_cast<Constant>(V)) {
1797 if (isa<ConstantPointerNull>(
C)) {
1798 unsigned AS = V->getType()->getPointerAddressSpace();
1806 if (
const ConstantFP *CFP = dyn_cast<ConstantFP>(
C))
1809 if (isa<UndefValue>(
C) && !V->getType()->isAggregateType())
1813 visit(CE->getOpcode(), *CE);
1815 assert(N1.
getNode() &&
"visit didn't populate the NodeMap!");
1819 if (isa<ConstantStruct>(
C) || isa<ConstantArray>(
C)) {
1821 for (
const Use &U :
C->operands()) {
1827 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1835 dyn_cast<ConstantDataSequential>(
C)) {
1837 for (
unsigned i = 0, e = CDS->getNumElements(); i != e; ++i) {
1841 for (
unsigned i = 0, e = Val->
getNumValues(); i != e; ++i)
1845 if (isa<ArrayType>(CDS->getType()))
1850 if (
C->getType()->isStructTy() ||
C->getType()->isArrayTy()) {
1851 assert((isa<ConstantAggregateZero>(
C) || isa<UndefValue>(
C)) &&
1852 "Unknown struct or array constant!");
1856 unsigned NumElts = ValueVTs.
size();
1860 for (
unsigned i = 0; i != NumElts; ++i) {
1861 EVT EltVT = ValueVTs[i];
1862 if (isa<UndefValue>(
C))
1876 if (
const auto *Equiv = dyn_cast<DSOLocalEquivalent>(
C))
1877 return getValue(Equiv->getGlobalValue());
1879 if (
const auto *
NC = dyn_cast<NoCFIValue>(
C))
1882 if (VT == MVT::aarch64svcount) {
1883 assert(
C->isNullValue() &&
"Can only zero this target type!");
1888 VectorType *VecTy = cast<VectorType>(V->getType());
1894 unsigned NumElements = cast<FixedVectorType>(VecTy)->getNumElements();
1895 for (
unsigned i = 0; i != NumElements; ++i)
1901 if (isa<ConstantAggregateZero>(
C)) {
1919 if (
const AllocaInst *AI = dyn_cast<AllocaInst>(V)) {
1928 if (
const Instruction *Inst = dyn_cast<Instruction>(V)) {
1932 Inst->getType(), std::nullopt);
1940 if (
const auto *BB = dyn_cast<BasicBlock>(V))
1946void SelectionDAGBuilder::visitCatchPad(
const CatchPadInst &
I) {
1955 if (IsMSVCCXX || IsCoreCLR)
1982 Value *ParentPad =
I.getCatchSwitchParentPad();
1984 if (isa<ConstantTokenNone>(ParentPad))
1987 SuccessorColor = cast<Instruction>(ParentPad)->
getParent();
1988 assert(SuccessorColor &&
"No parent funclet for catchret!");
1990 assert(SuccessorColorMBB &&
"No MBB for SuccessorColor!");
1999void SelectionDAGBuilder::visitCleanupPad(
const CleanupPadInst &CPI) {
2043 if (isa<CleanupPadInst>(Pad)) {
2045 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2046 UnwindDests.back().first->setIsEHScopeEntry();
2048 }
else if (
const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2051 for (
const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2052 UnwindDests.emplace_back(FuncInfo.
MBBMap[CatchPadBB], Prob);
2053 UnwindDests.back().first->setIsEHScopeEntry();
2084 assert(UnwindDests.size() <= 1 &&
2085 "There should be at most one unwind destination for wasm");
2092 if (isa<LandingPadInst>(Pad)) {
2094 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2096 }
else if (isa<CleanupPadInst>(Pad)) {
2099 UnwindDests.emplace_back(FuncInfo.
MBBMap[EHPadBB], Prob);
2100 UnwindDests.
back().first->setIsEHScopeEntry();
2101 UnwindDests.back().first->setIsEHFuncletEntry();
2103 }
else if (
const auto *CatchSwitch = dyn_cast<CatchSwitchInst>(Pad)) {
2105 for (
const BasicBlock *CatchPadBB : CatchSwitch->handlers()) {
2106 UnwindDests.emplace_back(FuncInfo.
MBBMap[CatchPadBB], Prob);
2108 if (IsMSVCCXX || IsCoreCLR)
2109 UnwindDests.back().first->setIsEHFuncletEntry();
2111 UnwindDests.back().first->setIsEHScopeEntry();
2113 NewEHPadBB = CatchSwitch->getUnwindDest();
2119 if (BPI && NewEHPadBB)
2121 EHPadBB = NewEHPadBB;
2128 auto UnwindDest =
I.getUnwindDest();
2135 for (
auto &UnwindDest : UnwindDests) {
2136 UnwindDest.first->setIsEHPad();
2137 addSuccessorWithProb(
FuncInfo.
MBB, UnwindDest.first, UnwindDest.second);
2147void SelectionDAGBuilder::visitCatchSwitch(
const CatchSwitchInst &CSI) {
2151void SelectionDAGBuilder::visitRet(
const ReturnInst &
I) {
2165 if (
I.getParent()->getTerminatingDeoptimizeCall()) {
2172 const Function *
F =
I.getParent()->getParent();
2191 unsigned NumValues = ValueVTs.
size();
2194 Align BaseAlign =
DL.getPrefTypeAlign(
I.getOperand(0)->getType());
2195 for (
unsigned i = 0; i != NumValues; ++i) {
2202 if (MemVTs[i] != ValueVTs[i])
2212 MVT::Other, Chains);
2213 }
else if (
I.getNumOperands() != 0) {
2216 unsigned NumValues = ValueVTs.
size();
2220 const Function *
F =
I.getParent()->getParent();
2223 I.getOperand(0)->getType(),
F->getCallingConv(),
2227 if (
F->getAttributes().hasRetAttr(Attribute::SExt))
2229 else if (
F->getAttributes().hasRetAttr(Attribute::ZExt))
2233 bool RetInReg =
F->getAttributes().hasRetAttr(Attribute::InReg);
2235 for (
unsigned j = 0;
j != NumValues; ++
j) {
2236 EVT VT = ValueVTs[
j];
2248 &Parts[0], NumParts, PartVT, &
I,
CC, ExtendKind);
2255 if (
I.getOperand(0)->getType()->isPointerTy()) {
2257 Flags.setPointerAddrSpace(
2258 cast<PointerType>(
I.getOperand(0)->getType())->getAddressSpace());
2261 if (NeedsRegBlock) {
2262 Flags.setInConsecutiveRegs();
2263 if (j == NumValues - 1)
2264 Flags.setInConsecutiveRegsLast();
2273 for (
unsigned i = 0; i < NumParts; ++i) {
2275 Parts[i].getValueType().getSimpleVT(),
2286 const Function *
F =
I.getParent()->getParent();
2288 F->getAttributes().hasAttrSomewhere(Attribute::SwiftError)) {
2291 Flags.setSwiftError();
2310 "LowerReturn didn't return a valid chain!");
2321 if (V->getType()->isEmptyTy())
2326 assert((!V->use_empty() || isa<CallBrInst>(V)) &&
2327 "Unused value assigned virtual registers!");
2337 if (!isa<Instruction>(V) && !isa<Argument>(V))
return;
2350 if (
const Instruction *VI = dyn_cast<Instruction>(V)) {
2352 if (VI->getParent() == FromBB)
2361 if (isa<Argument>(V)) {
2378 const BasicBlock *SrcBB = Src->getBasicBlock();
2379 const BasicBlock *DstBB = Dst->getBasicBlock();
2383 auto SuccSize = std::max<uint32_t>(
succ_size(SrcBB), 1);
2393 Src->addSuccessorWithoutProb(Dst);
2396 Prob = getEdgeProbability(Src, Dst);
2397 Src->addSuccessor(Dst, Prob);
2403 return I->getParent() == BB;
2423 if (
const CmpInst *BOp = dyn_cast<CmpInst>(
Cond)) {
2427 if (CurBB == SwitchBB ||
2433 InvertCond ? IC->getInversePredicate() : IC->getPredicate();
2438 InvertCond ? FC->getInversePredicate() : FC->getPredicate();
2444 CaseBlock CB(Condition, BOp->getOperand(0), BOp->getOperand(1),
nullptr,
2446 SL->SwitchCases.push_back(CB);
2455 SL->SwitchCases.push_back(CB);
2463 unsigned Depth = 0) {
2468 auto *
I = dyn_cast<Instruction>(V);
2472 if (Necessary !=
nullptr) {
2475 if (Necessary->contains(
I))
2483 for (
unsigned OpIdx = 0, E =
I->getNumOperands(); OpIdx < E; ++OpIdx)
2494 if (
I.getNumSuccessors() != 2)
2497 if (!
I.isConditional())
2509 if (BPI !=
nullptr) {
2515 std::optional<bool> Likely;
2518 else if (BPI->
isEdgeHot(
I.getParent(), IfFalse))
2522 if (Opc == (*Likely ? Instruction::And : Instruction::Or))
2534 if (CostThresh <= 0)
2548 if (
const auto *RhsI = dyn_cast<Instruction>(Rhs))
2559 Value *BrCond =
I.getCondition();
2560 auto ShouldCountInsn = [&RhsDeps, &BrCond](
const Instruction *Ins) {
2561 for (
const auto *U : Ins->users()) {
2563 if (
auto *UIns = dyn_cast<Instruction>(U))
2564 if (UIns != BrCond && !RhsDeps.
contains(UIns))
2577 for (
unsigned PruneIters = 0; PruneIters < MaxPruneIters; ++PruneIters) {
2579 for (
const auto &InsPair : RhsDeps) {
2580 if (!ShouldCountInsn(InsPair.first)) {
2581 ToDrop = InsPair.first;
2585 if (ToDrop ==
nullptr)
2587 RhsDeps.erase(ToDrop);
2590 for (
const auto &InsPair : RhsDeps) {
2598 if (CostOfIncluding > CostThresh)
2624 const Value *BOpOp0, *BOpOp1;
2638 if (BOpc == Instruction::And)
2639 BOpc = Instruction::Or;
2640 else if (BOpc == Instruction::Or)
2641 BOpc = Instruction::And;
2647 bool BOpIsInOrAndTree = BOpc && BOpc == Opc && BOp->
hasOneUse();
2652 TProb, FProb, InvertCond);
2662 if (Opc == Instruction::Or) {
2683 auto NewTrueProb = TProb / 2;
2684 auto NewFalseProb = TProb / 2 + FProb;
2687 NewFalseProb, InvertCond);
2694 Probs[1], InvertCond);
2696 assert(Opc == Instruction::And &&
"Unknown merge op!");
2716 auto NewTrueProb = TProb + FProb / 2;
2717 auto NewFalseProb = FProb / 2;
2720 NewFalseProb, InvertCond);
2727 Probs[1], InvertCond);
2736 if (Cases.size() != 2)
return true;
2740 if ((Cases[0].CmpLHS == Cases[1].CmpLHS &&
2741 Cases[0].CmpRHS == Cases[1].CmpRHS) ||
2742 (Cases[0].CmpRHS == Cases[1].CmpLHS &&
2743 Cases[0].CmpLHS == Cases[1].CmpRHS)) {
2749 if (Cases[0].CmpRHS == Cases[1].CmpRHS &&
2750 Cases[0].
CC == Cases[1].
CC &&
2751 isa<Constant>(Cases[0].CmpRHS) &&
2752 cast<Constant>(Cases[0].CmpRHS)->isNullValue()) {
2753 if (Cases[0].
CC ==
ISD::SETEQ && Cases[0].TrueBB == Cases[1].ThisBB)
2755 if (Cases[0].
CC ==
ISD::SETNE && Cases[0].FalseBB == Cases[1].ThisBB)
2762void SelectionDAGBuilder::visitBr(
const BranchInst &
I) {
2768 if (
I.isUnconditional()) {
2774 if (Succ0MBB != NextBlock(BrMBB) ||
2787 const Value *CondVal =
I.getCondition();
2807 const Instruction *BOp = dyn_cast<Instruction>(CondVal);
2809 BOp->
hasOneUse() && !
I.hasMetadata(LLVMContext::MD_unpredictable)) {
2811 const Value *BOp0, *BOp1;
2814 Opcode = Instruction::And;
2816 Opcode = Instruction::Or;
2824 Opcode, BOp0, BOp1))) {
2826 getEdgeProbability(BrMBB, Succ0MBB),
2827 getEdgeProbability(BrMBB, Succ1MBB),
2832 assert(
SL->SwitchCases[0].ThisBB == BrMBB &&
"Unexpected lowering!");
2836 for (
unsigned i = 1, e =
SL->SwitchCases.size(); i != e; ++i) {
2843 SL->SwitchCases.erase(
SL->SwitchCases.begin());
2849 for (
unsigned i = 1, e =
SL->SwitchCases.size(); i != e; ++i)
2852 SL->SwitchCases.clear();
2858 nullptr, Succ0MBB, Succ1MBB, BrMBB,
getCurSDLoc());
2877 if (CB.
TrueBB != NextBlock(SwitchBB)) {
2919 if (cast<ConstantInt>(CB.
CmpLHS)->isMinValue(
true)) {
2940 if (CB.
TrueBB == NextBlock(SwitchBB)) {
2964 assert(JT.SL &&
"Should set SDLoc for SelectionDAG!");
2965 assert(JT.Reg != -1U &&
"Should lower JT Header first!");
2979 assert(JT.SL &&
"Should set SDLoc for SelectionDAG!");
2980 const SDLoc &dl = *JT.SL;
2996 unsigned JumpTableReg =
2999 JumpTableReg, SwitchOp);
3000 JT.Reg = JumpTableReg;
3012 MVT::Other, CopyTo, CMP,
3016 if (JT.MBB != NextBlock(SwitchBB))
3023 if (JT.MBB != NextBlock(SwitchBB))
3051 if (PtrTy != PtrMemTy)
3099 Entry.Node = GuardVal;
3101 if (GuardCheckFn->hasParamAttribute(0, Attribute::AttrKind::InReg))
3102 Entry.IsInReg =
true;
3103 Args.push_back(Entry);
3109 getValue(GuardCheckFn), std::move(Args));
3111 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
3125 Guard =
DAG.
getLoad(PtrMemTy, dl, Chain, GuardPtr,
3162 TLI.
makeLibCall(
DAG, RTLIB::STACKPROTECTOR_CHECK_FAIL, MVT::isVoid,
3193 bool UsePtrType =
false;
3197 for (
unsigned i = 0, e =
B.Cases.size(); i != e; ++i)
3217 if (!
B.FallthroughUnreachable)
3218 addSuccessorWithProb(SwitchBB,
B.Default,
B.DefaultProb);
3219 addSuccessorWithProb(SwitchBB,
MBB,
B.Prob);
3223 if (!
B.FallthroughUnreachable) {
3236 if (
MBB != NextBlock(SwitchBB))
3255 if (PopCount == 1) {
3262 }
else if (PopCount == BB.
Range) {
3281 addSuccessorWithProb(SwitchBB,
B.TargetBB,
B.ExtraProb);
3283 addSuccessorWithProb(SwitchBB, NextMBB, BranchProbToNext);
3294 if (NextMBB != NextBlock(SwitchBB))
3301void SelectionDAGBuilder::visitInvoke(
const InvokeInst &
I) {
3312 assert(!
I.hasOperandBundlesOtherThan(
3313 {LLVMContext::OB_deopt, LLVMContext::OB_gc_transition,
3314 LLVMContext::OB_gc_live, LLVMContext::OB_funclet,
3315 LLVMContext::OB_cfguardtarget,
3316 LLVMContext::OB_clang_arc_attachedcall}) &&
3317 "Cannot lower invokes with arbitrary operand bundles yet!");
3319 const Value *Callee(
I.getCalledOperand());
3320 const Function *Fn = dyn_cast<Function>(Callee);
3321 if (isa<InlineAsm>(Callee))
3322 visitInlineAsm(
I, EHPadBB);
3327 case Intrinsic::donothing:
3329 case Intrinsic::seh_try_begin:
3330 case Intrinsic::seh_scope_begin:
3331 case Intrinsic::seh_try_end:
3332 case Intrinsic::seh_scope_end:
3338 case Intrinsic::experimental_patchpoint_void:
3339 case Intrinsic::experimental_patchpoint:
3340 visitPatchpoint(
I, EHPadBB);
3342 case Intrinsic::experimental_gc_statepoint:
3345 case Intrinsic::wasm_rethrow: {
3360 }
else if (
I.hasDeoptState()) {
3374 if (!isa<GCStatepointInst>(
I)) {
3386 addSuccessorWithProb(InvokeMBB, Return);
3387 for (
auto &UnwindDest : UnwindDests) {
3388 UnwindDest.first->setIsEHPad();
3389 addSuccessorWithProb(InvokeMBB, UnwindDest.first, UnwindDest.second);
3398void SelectionDAGBuilder::visitCallBr(
const CallBrInst &
I) {
3403 assert(!
I.hasOperandBundlesOtherThan(
3404 {LLVMContext::OB_deopt, LLVMContext::OB_funclet}) &&
3405 "Cannot lower callbrs with arbitrary operand bundles yet!");
3407 assert(
I.isInlineAsm() &&
"Only know how to handle inlineasm callbr");
3413 Dests.
insert(
I.getDefaultDest());
3418 for (
unsigned i = 0, e =
I.getNumIndirectDests(); i < e; ++i) {
3421 Target->setIsInlineAsmBrIndirectTarget();
3422 Target->setMachineBlockAddressTaken();
3423 Target->setLabelMustBeEmitted();
3425 if (Dests.
insert(Dest).second)
3436void SelectionDAGBuilder::visitResume(
const ResumeInst &RI) {
3437 llvm_unreachable(
"SelectionDAGBuilder shouldn't visit resume instructions!");
3440void SelectionDAGBuilder::visitLandingPad(
const LandingPadInst &LP) {
3442 "Call to landingpad not in landing pad!");
3462 assert(ValueVTs.
size() == 2 &&
"Only two-valued landingpads are supported");
3492 if (JTB.first.HeaderBB ==
First)
3493 JTB.first.HeaderBB =
Last;
3506 for (
unsigned i = 0, e =
I.getNumSuccessors(); i != e; ++i) {
3508 bool Inserted =
Done.insert(BB).second;
3513 addSuccessorWithProb(IndirectBrMBB, Succ);
3528 if (
const CallInst *Call = dyn_cast_or_null<CallInst>(
I.getPrevNode())) {
3529 if (
Call->doesNotReturn())
3537void SelectionDAGBuilder::visitUnary(
const User &
I,
unsigned Opcode) {
3539 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3540 Flags.copyFMF(*FPOp);
3548void SelectionDAGBuilder::visitBinary(
const User &
I,
unsigned Opcode) {
3550 if (
auto *OFBinOp = dyn_cast<OverflowingBinaryOperator>(&
I)) {
3551 Flags.setNoSignedWrap(OFBinOp->hasNoSignedWrap());
3552 Flags.setNoUnsignedWrap(OFBinOp->hasNoUnsignedWrap());
3554 if (
auto *ExactOp = dyn_cast<PossiblyExactOperator>(&
I))
3555 Flags.setExact(ExactOp->isExact());
3556 if (
auto *DisjointOp = dyn_cast<PossiblyDisjointInst>(&
I))
3557 Flags.setDisjoint(DisjointOp->isDisjoint());
3558 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3559 Flags.copyFMF(*FPOp);
3568void SelectionDAGBuilder::visitShift(
const User &
I,
unsigned Opcode) {
3577 if (!
I.getType()->isVectorTy() && Op2.
getValueType() != ShiftTy) {
3579 "Unexpected shift type");
3590 dyn_cast<const OverflowingBinaryOperator>(&
I)) {
3591 nuw = OFBinOp->hasNoUnsignedWrap();
3592 nsw = OFBinOp->hasNoSignedWrap();
3595 dyn_cast<const PossiblyExactOperator>(&
I))
3596 exact = ExactOp->isExact();
3599 Flags.setExact(exact);
3600 Flags.setNoSignedWrap(nsw);
3601 Flags.setNoUnsignedWrap(nuw);
3607void SelectionDAGBuilder::visitSDiv(
const User &
I) {
3612 Flags.setExact(isa<PossiblyExactOperator>(&
I) &&
3613 cast<PossiblyExactOperator>(&
I)->isExact());
3618void SelectionDAGBuilder::visitICmp(
const User &
I) {
3620 if (
const ICmpInst *IC = dyn_cast<ICmpInst>(&
I))
3621 predicate = IC->getPredicate();
3622 else if (
const ConstantExpr *IC = dyn_cast<ConstantExpr>(&
I))
3645void SelectionDAGBuilder::visitFCmp(
const User &
I) {
3647 if (
const FCmpInst *FC = dyn_cast<FCmpInst>(&
I))
3648 predicate =
FC->getPredicate();
3649 else if (
const ConstantExpr *FC = dyn_cast<ConstantExpr>(&
I))
3655 auto *FPMO = cast<FPMathOperator>(&
I);
3660 Flags.copyFMF(*FPMO);
3672 return isa<SelectInst>(V);
3676void SelectionDAGBuilder::visitSelect(
const User &
I) {
3680 unsigned NumValues = ValueVTs.
size();
3681 if (NumValues == 0)
return;
3691 bool IsUnaryAbs =
false;
3692 bool Negate =
false;
3695 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
3696 Flags.copyFMF(*FPOp);
3698 Flags.setUnpredictable(
3699 cast<SelectInst>(
I).getMetadata(LLVMContext::MD_unpredictable));
3703 EVT VT = ValueVTs[0];
3715 bool UseScalarMinMax = VT.
isVector() &&
3724 switch (SPR.Flavor) {
3730 switch (SPR.NaNBehavior) {
3743 switch (SPR.NaNBehavior) {
3787 for (
unsigned i = 0; i != NumValues; ++i) {
3796 for (
unsigned i = 0; i != NumValues; ++i) {
3810void SelectionDAGBuilder::visitTrunc(
const User &
I) {
3818void SelectionDAGBuilder::visitZExt(
const User &
I) {
3826 if (
auto *PNI = dyn_cast<PossiblyNonNegInst>(&
I))
3827 Flags.setNonNeg(PNI->hasNonNeg());
3832 if (
Flags.hasNonNeg() &&
3841void SelectionDAGBuilder::visitSExt(
const User &
I) {
3850void SelectionDAGBuilder::visitFPTrunc(
const User &
I) {
3861void SelectionDAGBuilder::visitFPExt(
const User &
I) {
3869void SelectionDAGBuilder::visitFPToUI(
const User &
I) {
3877void SelectionDAGBuilder::visitFPToSI(
const User &
I) {
3885void SelectionDAGBuilder::visitUIToFP(
const User &
I) {
3891 if (
auto *PNI = dyn_cast<PossiblyNonNegInst>(&
I))
3892 Flags.setNonNeg(PNI->hasNonNeg());
3897void SelectionDAGBuilder::visitSIToFP(
const User &
I) {
3905void SelectionDAGBuilder::visitPtrToInt(
const User &
I) {
3919void SelectionDAGBuilder::visitIntToPtr(
const User &
I) {
3931void SelectionDAGBuilder::visitBitCast(
const User &
I) {
3939 if (DestVT !=
N.getValueType())
3946 else if(
ConstantInt *
C = dyn_cast<ConstantInt>(
I.getOperand(0)))
3953void SelectionDAGBuilder::visitAddrSpaceCast(
const User &
I) {
3955 const Value *SV =
I.getOperand(0);
3960 unsigned DestAS =
I.getType()->getPointerAddressSpace();
3968void SelectionDAGBuilder::visitInsertElement(
const User &
I) {
3976 InVec, InVal, InIdx));
3979void SelectionDAGBuilder::visitExtractElement(
const User &
I) {
3989void SelectionDAGBuilder::visitShuffleVector(
const User &
I) {
3993 if (
auto *SVI = dyn_cast<ShuffleVectorInst>(&
I))
3994 Mask = SVI->getShuffleMask();
3996 Mask = cast<ConstantExpr>(
I).getShuffleMask();
4002 if (
all_of(Mask, [](
int Elem) {
return Elem == 0; }) &&
4018 unsigned MaskNumElts =
Mask.size();
4020 if (SrcNumElts == MaskNumElts) {
4026 if (SrcNumElts < MaskNumElts) {
4030 if (MaskNumElts % SrcNumElts == 0) {
4034 unsigned NumConcat = MaskNumElts / SrcNumElts;
4035 bool IsConcat =
true;
4037 for (
unsigned i = 0; i != MaskNumElts; ++i) {
4043 if ((
Idx % SrcNumElts != (i % SrcNumElts)) ||
4044 (ConcatSrcs[i / SrcNumElts] >= 0 &&
4045 ConcatSrcs[i / SrcNumElts] != (
int)(
Idx / SrcNumElts))) {
4050 ConcatSrcs[i / SrcNumElts] =
Idx / SrcNumElts;
4057 for (
auto Src : ConcatSrcs) {
4070 unsigned PaddedMaskNumElts =
alignTo(MaskNumElts, SrcNumElts);
4071 unsigned NumConcat = PaddedMaskNumElts / SrcNumElts;
4088 for (
unsigned i = 0; i != MaskNumElts; ++i) {
4090 if (
Idx >= (
int)SrcNumElts)
4091 Idx -= SrcNumElts - PaddedMaskNumElts;
4099 if (MaskNumElts != PaddedMaskNumElts)
4107 if (SrcNumElts > MaskNumElts) {
4110 int StartIdx[2] = { -1, -1 };
4111 bool CanExtract =
true;
4112 for (
int Idx : Mask) {
4117 if (
Idx >= (
int)SrcNumElts) {
4126 if (NewStartIdx + MaskNumElts > SrcNumElts ||
4127 (StartIdx[Input] >= 0 && StartIdx[Input] != NewStartIdx))
4131 StartIdx[Input] = NewStartIdx;
4134 if (StartIdx[0] < 0 && StartIdx[1] < 0) {
4140 for (
unsigned Input = 0; Input < 2; ++Input) {
4141 SDValue &Src = Input == 0 ? Src1 : Src2;
4142 if (StartIdx[Input] < 0)
4152 for (
int &
Idx : MappedOps) {
4153 if (
Idx >= (
int)SrcNumElts)
4154 Idx -= SrcNumElts + StartIdx[1] - MaskNumElts;
4169 for (
int Idx : Mask) {
4175 SDValue &Src =
Idx < (int)SrcNumElts ? Src1 : Src2;
4176 if (
Idx >= (
int)SrcNumElts)
Idx -= SrcNumElts;
4190 const Value *Op0 =
I.getOperand(0);
4191 const Value *Op1 =
I.getOperand(1);
4192 Type *AggTy =
I.getType();
4194 bool IntoUndef = isa<UndefValue>(Op0);
4195 bool FromUndef = isa<UndefValue>(Op1);
4205 unsigned NumAggValues = AggValueVTs.
size();
4206 unsigned NumValValues = ValValueVTs.
size();
4210 if (!NumAggValues) {
4218 for (; i != LinearIndex; ++i)
4219 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4224 for (; i != LinearIndex + NumValValues; ++i)
4225 Values[i] = FromUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4229 for (; i != NumAggValues; ++i)
4230 Values[i] = IntoUndef ?
DAG.
getUNDEF(AggValueVTs[i]) :
4239 const Value *Op0 =
I.getOperand(0);
4241 Type *ValTy =
I.getType();
4242 bool OutOfUndef = isa<UndefValue>(Op0);
4250 unsigned NumValValues = ValValueVTs.
size();
4253 if (!NumValValues) {
4262 for (
unsigned i = LinearIndex; i != LinearIndex + NumValValues; ++i)
4263 Values[i - LinearIndex] =
4272void SelectionDAGBuilder::visitGetElementPtr(
const User &
I) {
4273 Value *Op0 =
I.getOperand(0);
4283 bool IsVectorGEP =
I.getType()->isVectorTy();
4285 IsVectorGEP ? cast<VectorType>(
I.getType())->getElementCount()
4288 if (IsVectorGEP && !
N.getValueType().isVector()) {
4296 const Value *
Idx = GTI.getOperand();
4297 if (
StructType *StTy = GTI.getStructTypeOrNull()) {
4298 unsigned Field = cast<Constant>(
Idx)->getUniqueInteger().getZExtValue();
4307 if (int64_t(
Offset) >= 0 && cast<GEPOperator>(
I).isInBounds())
4308 Flags.setNoUnsignedWrap(
true);
4324 bool ElementScalable = ElementSize.
isScalable();
4328 const auto *
C = dyn_cast<Constant>(
Idx);
4329 if (
C && isa<VectorType>(
C->getType()))
4330 C =
C->getSplatValue();
4332 const auto *CI = dyn_cast_or_null<ConstantInt>(
C);
4333 if (CI && CI->isZero())
4335 if (CI && !ElementScalable) {
4349 Flags.setNoUnsignedWrap(
true);
4362 VectorElementCount);
4370 if (ElementScalable) {
4371 EVT VScaleTy =
N.getValueType().getScalarType();
4381 if (ElementMul != 1) {
4382 if (ElementMul.isPowerOf2()) {
4383 unsigned Amt = ElementMul.logBase2();
4385 N.getValueType(), IdxN,
4391 N.getValueType(), IdxN, Scale);
4397 N.getValueType(),
N, IdxN);
4408 if (PtrMemTy != PtrTy && !cast<GEPOperator>(
I).isInBounds())
4414void SelectionDAGBuilder::visitAlloca(
const AllocaInst &
I) {
4421 Type *Ty =
I.getAllocatedType();
4425 MaybeAlign Alignment = std::max(
DL.getPrefTypeAlign(Ty),
I.getAlign());
4449 if (*Alignment <= StackAlign)
4450 Alignment = std::nullopt;
4457 Flags.setNoUnsignedWrap(
true);
4467 DAG.
getConstant(Alignment ? Alignment->value() : 0, dl, IntPtr)};
4483 if (!
I.hasMetadata(LLVMContext::MD_noundef))
4485 return I.getMetadata(LLVMContext::MD_range);
4488void SelectionDAGBuilder::visitLoad(
const LoadInst &
I) {
4490 return visitAtomicLoad(
I);
4493 const Value *SV =
I.getOperand(0);
4497 if (
const Argument *Arg = dyn_cast<Argument>(SV)) {
4498 if (Arg->hasSwiftErrorAttr())
4499 return visitLoadFromSwiftError(
I);
4502 if (
const AllocaInst *Alloca = dyn_cast<AllocaInst>(SV)) {
4503 if (Alloca->isSwiftError())
4504 return visitLoadFromSwiftError(
I);
4510 Type *Ty =
I.getType();
4514 unsigned NumValues = ValueVTs.
size();
4518 Align Alignment =
I.getAlign();
4521 bool isVolatile =
I.isVolatile();
4526 bool ConstantMemory =
false;
4539 ConstantMemory =
true;
4554 unsigned ChainI = 0;
4555 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4578 MMOFlags, AAInfo, Ranges);
4579 Chains[ChainI] =
L.getValue(1);
4581 if (MemVTs[i] != ValueVTs[i])
4587 if (!ConstantMemory) {
4600void SelectionDAGBuilder::visitStoreToSwiftError(
const StoreInst &
I) {
4602 "call visitStoreToSwiftError when backend supports swifterror");
4606 const Value *SrcV =
I.getOperand(0);
4608 SrcV->
getType(), ValueVTs, &Offsets, 0);
4609 assert(ValueVTs.
size() == 1 && Offsets[0] == 0 &&
4610 "expect a single EVT for swifterror");
4619 SDValue(Src.getNode(), Src.getResNo()));
4623void SelectionDAGBuilder::visitLoadFromSwiftError(
const LoadInst &
I) {
4625 "call visitLoadFromSwiftError when backend supports swifterror");
4628 !
I.hasMetadata(LLVMContext::MD_nontemporal) &&
4629 !
I.hasMetadata(LLVMContext::MD_invariant_load) &&
4630 "Support volatile, non temporal, invariant for load_from_swift_error");
4632 const Value *SV =
I.getOperand(0);
4633 Type *Ty =
I.getType();
4638 I.getAAMetadata()))) &&
4639 "load_from_swift_error should not be constant memory");
4644 ValueVTs, &Offsets, 0);
4645 assert(ValueVTs.
size() == 1 && Offsets[0] == 0 &&
4646 "expect a single EVT for swifterror");
4656void SelectionDAGBuilder::visitStore(
const StoreInst &
I) {
4658 return visitAtomicStore(
I);
4660 const Value *SrcV =
I.getOperand(0);
4661 const Value *PtrV =
I.getOperand(1);
4667 if (
const Argument *Arg = dyn_cast<Argument>(PtrV)) {
4668 if (Arg->hasSwiftErrorAttr())
4669 return visitStoreToSwiftError(
I);
4672 if (
const AllocaInst *Alloca = dyn_cast<AllocaInst>(PtrV)) {
4673 if (Alloca->isSwiftError())
4674 return visitStoreToSwiftError(
I);
4681 SrcV->
getType(), ValueVTs, &MemVTs, &Offsets);
4682 unsigned NumValues = ValueVTs.
size();
4695 Align Alignment =
I.getAlign();
4700 unsigned ChainI = 0;
4701 for (
unsigned i = 0; i != NumValues; ++i, ++ChainI) {
4718 if (MemVTs[i] != ValueVTs[i])
4721 DAG.
getStore(Root, dl, Val,
Add, PtrInfo, Alignment, MMOFlags, AAInfo);
4722 Chains[ChainI] = St;
4731void SelectionDAGBuilder::visitMaskedStore(
const CallInst &
I,
4732 bool IsCompressing) {
4738 Src0 =
I.getArgOperand(0);
4739 Ptr =
I.getArgOperand(1);
4740 Alignment = cast<ConstantInt>(
I.getArgOperand(2))->getAlignValue();
4741 Mask =
I.getArgOperand(3);
4746 Src0 =
I.getArgOperand(0);
4747 Ptr =
I.getArgOperand(1);
4748 Mask =
I.getArgOperand(2);
4749 Alignment =
I.getParamAlign(1).valueOrOne();
4752 Value *PtrOperand, *MaskOperand, *Src0Operand;
4755 getCompressingStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4757 getMaskedStoreOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4767 if (
I.hasMetadata(LLVMContext::MD_nontemporal))
4803 assert(
Ptr->getType()->isVectorTy() &&
"Unexpected pointer type");
4806 if (
auto *
C = dyn_cast<Constant>(
Ptr)) {
4807 C =
C->getSplatValue();
4813 ElementCount NumElts = cast<VectorType>(
Ptr->getType())->getElementCount();
4822 if (!
GEP ||
GEP->getParent() != CurBB)
4825 if (
GEP->getNumOperands() != 2)
4828 const Value *BasePtr =
GEP->getPointerOperand();
4829 const Value *IndexVal =
GEP->getOperand(
GEP->getNumOperands() - 1);
4835 TypeSize ScaleVal =
DL.getTypeAllocSize(
GEP->getResultElementType());
4840 if (ScaleVal != 1 &&
4853void SelectionDAGBuilder::visitMaskedScatter(
const CallInst &
I) {
4861 Align Alignment = cast<ConstantInt>(
I.getArgOperand(2))
4862 ->getMaybeAlignValue()
4873 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
4893 Ops, MMO, IndexType,
false);
4898void SelectionDAGBuilder::visitMaskedLoad(
const CallInst &
I,
bool IsExpanding) {
4904 Ptr =
I.getArgOperand(0);
4905 Alignment = cast<ConstantInt>(
I.getArgOperand(1))->getAlignValue();
4906 Mask =
I.getArgOperand(2);
4907 Src0 =
I.getArgOperand(3);
4912 Ptr =
I.getArgOperand(0);
4913 Alignment =
I.getParamAlign(0).valueOrOne();
4914 Mask =
I.getArgOperand(1);
4915 Src0 =
I.getArgOperand(2);
4918 Value *PtrOperand, *MaskOperand, *Src0Operand;
4921 getExpandingLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4923 getMaskedLoadOps(PtrOperand, MaskOperand, Src0Operand, Alignment);
4941 if (
I.hasMetadata(LLVMContext::MD_nontemporal))
4956void SelectionDAGBuilder::visitMaskedGather(
const CallInst &
I) {
4966 Align Alignment = cast<ConstantInt>(
I.getArgOperand(1))
4967 ->getMaybeAlignValue()
4979 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
5025 AAMDNodes(),
nullptr, SSID, SuccessOrdering, FailureOrdering);
5028 dl, MemVT, VTs, InChain,
5039void SelectionDAGBuilder::visitAtomicRMW(
const AtomicRMWInst &
I) {
5042 switch (
I.getOperation()) {
5092void SelectionDAGBuilder::visitFence(
const FenceInst &
I) {
5106void SelectionDAGBuilder::visitAtomicLoad(
const LoadInst &
I) {
5126 nullptr, SSID, Order);
5142void SelectionDAGBuilder::visitAtomicStore(
const StoreInst &
I) {
5164 nullptr, SSID, Ordering);
5180void SelectionDAGBuilder::visitTargetIntrinsic(
const CallInst &
I,
5181 unsigned Intrinsic) {
5186 bool HasChain = !
F->doesNotAccessMemory();
5187 bool OnlyLoad = HasChain &&
F->onlyReadsMemory();
5214 for (
unsigned i = 0, e =
I.arg_size(); i != e; ++i) {
5215 const Value *Arg =
I.getArgOperand(i);
5216 if (!
I.paramHasAttr(i, Attribute::ImmArg)) {
5223 if (
const ConstantInt *CI = dyn_cast<ConstantInt>(Arg)) {
5224 assert(CI->getBitWidth() <= 64 &&
5225 "large intrinsic immediates not handled");
5243 if (
auto *FPMO = dyn_cast<FPMathOperator>(&
I))
5244 Flags.copyFMF(*FPMO);
5251 auto *Token = Bundle->Inputs[0].get();
5253 assert(Ops.
back().getValueType() != MVT::Glue &&
5254 "Did not expected another glue node here.");
5262 if (IsTgtIntrinsic) {
5270 else if (
Info.fallbackAddressSpace)
5274 Info.size,
I.getAAMetadata());
5275 }
else if (!HasChain) {
5277 }
else if (!
I.getType()->isVoidTy()) {
5291 if (!
I.getType()->isVoidTy()) {
5292 if (!isa<VectorType>(
I.getType()))
5364 SDValue TwoToFractionalPartOfX;
5441 if (
Op.getValueType() == MVT::f32 &&
5465 if (
Op.getValueType() == MVT::f32 &&
5564 if (
Op.getValueType() == MVT::f32 &&
5648 return DAG.
getNode(
ISD::FADD, dl, MVT::f32, LogOfExponent, Log2ofMantissa);
5661 if (
Op.getValueType() == MVT::f32 &&
5738 return DAG.
getNode(
ISD::FADD, dl, MVT::f32, LogOfExponent, Log10ofMantissa);
5749 if (
Op.getValueType() == MVT::f32 &&
5762 bool IsExp10 =
false;
5763 if (
LHS.getValueType() == MVT::f32 &&
RHS.getValueType() == MVT::f32 &&
5767 IsExp10 = LHSC->isExactlyValue(Ten);
5794 unsigned Val = RHSC->getSExtValue();
5823 CurSquare, CurSquare);
5828 if (RHSC->getSExtValue() < 0)
5842 EVT VT =
LHS.getValueType();
5865 if ((ScaleInt > 0 || (Saturating &&
Signed)) &&
5869 Opcode, VT, ScaleInt);
5904 switch (
N.getOpcode()) {
5907 Regs.emplace_back(cast<RegisterSDNode>(
Op)->
getReg(),
5908 Op.getValueType().getSizeInBits());
5933bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
5936 const Argument *Arg = dyn_cast<Argument>(V);
5950 auto &Inst =
TII->get(TargetOpcode::DBG_INSTR_REF);
5957 auto *NewDIExpr = FragExpr;
5964 return BuildMI(MF,
DL, Inst,
false, MOs, Variable, NewDIExpr);
5967 auto &Inst =
TII->get(TargetOpcode::DBG_VALUE);
5968 return BuildMI(MF,
DL, Inst, Indirect, Reg, Variable, FragExpr);
5972 if (Kind == FuncArgumentDbgValueKind::Value) {
5977 if (!IsInEntryBlock)
5993 bool VariableIsFunctionInputArg = Variable->
isParameter() &&
5994 !
DL->getInlinedAt();
5996 if (!IsInPrologue && !VariableIsFunctionInputArg)
6030 if (VariableIsFunctionInputArg) {
6035 return !NodeMap[
V].getNode();
6040 bool IsIndirect =
false;
6041 std::optional<MachineOperand>
Op;
6044 if (FI != std::numeric_limits<int>::max())
6048 if (!
Op &&
N.getNode()) {
6051 if (ArgRegsAndSizes.
size() == 1)
6052 Reg = ArgRegsAndSizes.
front().first;
6054 if (Reg &&
Reg.isVirtual()) {
6062 IsIndirect =
Kind != FuncArgumentDbgValueKind::Value;
6066 if (!
Op &&
N.getNode()) {
6071 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
6080 for (
const auto &RegAndSize : SplitRegs) {
6084 int RegFragmentSizeInBits = RegAndSize.second;
6086 uint64_t ExprFragmentSizeInBits = ExprFragmentInfo->SizeInBits;
6089 if (
Offset >= ExprFragmentSizeInBits)
6093 if (
Offset + RegFragmentSizeInBits > ExprFragmentSizeInBits) {
6094 RegFragmentSizeInBits = ExprFragmentSizeInBits -
Offset;
6099 Expr,
Offset, RegFragmentSizeInBits);
6100 Offset += RegAndSize.second;
6103 if (!FragmentExpr) {
6110 MakeVRegDbgValue(RegAndSize.first, *FragmentExpr,
6111 Kind != FuncArgumentDbgValueKind::Value);
6122 V->getType(), std::nullopt);
6123 if (RFV.occupiesMultipleRegs()) {
6124 splitMultiRegDbgValue(RFV.getRegsAndSizes());
6129 IsIndirect =
Kind != FuncArgumentDbgValueKind::Value;
6130 }
else if (ArgRegsAndSizes.
size() > 1) {
6133 splitMultiRegDbgValue(ArgRegsAndSizes);
6142 "Expected inlined-at fields to agree");
6146 NewMI = MakeVRegDbgValue(
Op->getReg(), Expr, IsIndirect);
6148 NewMI =
BuildMI(MF,
DL,
TII->get(TargetOpcode::DBG_VALUE),
true, *
Op,
6161 unsigned DbgSDNodeOrder) {
6162 if (
auto *FISDN = dyn_cast<FrameIndexSDNode>(
N.getNode())) {
6174 false, dl, DbgSDNodeOrder);
6177 false, dl, DbgSDNodeOrder);
6181 switch (Intrinsic) {
6182 case Intrinsic::smul_fix:
6184 case Intrinsic::umul_fix:
6186 case Intrinsic::smul_fix_sat:
6188 case Intrinsic::umul_fix_sat:
6190 case Intrinsic::sdiv_fix:
6192 case Intrinsic::udiv_fix:
6194 case Intrinsic::sdiv_fix_sat:
6196 case Intrinsic::udiv_fix_sat:
6203void SelectionDAGBuilder::lowerCallToExternalSymbol(
const CallInst &
I,
6204 const char *FunctionName) {
6205 assert(FunctionName &&
"FunctionName must not be nullptr");
6215 assert(cast<CallBase>(PreallocatedSetup)
6218 "expected call_preallocated_setup Value");
6219 for (
const auto *U : PreallocatedSetup->
users()) {
6220 auto *UseCall = cast<CallBase>(U);
6221 const Function *Fn = UseCall->getCalledFunction();
6222 if (!Fn || Fn->
getIntrinsicID() != Intrinsic::call_preallocated_arg) {
6232bool SelectionDAGBuilder::visitEntryValueDbgValue(
6239 const Argument *Arg = cast<Argument>(Values[0]);
6245 dbgs() <<
"Dropping dbg.value: expression is entry_value but "
6246 "couldn't find an associated register for the Argument\n");
6249 Register ArgVReg = ArgIt->getSecond();
6252 if (ArgVReg == VirtReg || ArgVReg == PhysReg) {
6254 Variable, Expr, PhysReg,
false , DbgLoc, SDNodeOrder);
6258 LLVM_DEBUG(
dbgs() <<
"Dropping dbg.value: expression is entry_value but "
6259 "couldn't find a physical register\n");
6264void SelectionDAGBuilder::visitConvergenceControl(
const CallInst &
I,
6265 unsigned Intrinsic) {
6267 switch (Intrinsic) {
6268 case Intrinsic::experimental_convergence_anchor:
6271 case Intrinsic::experimental_convergence_entry:
6274 case Intrinsic::experimental_convergence_loop: {
6276 auto *Token = Bundle->Inputs[0].get();
6284void SelectionDAGBuilder::visitVectorHistogram(
const CallInst &
I,
6285 unsigned IntrinsicID) {
6288 assert(IntrinsicID == Intrinsic::experimental_vector_histogram_add &&
6289 "Tried to lower unsupported histogram type");
6310 unsigned AS =
Ptr->getType()->getScalarType()->getPointerAddressSpace();
6336 Ops, MMO, IndexType);
6343void SelectionDAGBuilder::visitIntrinsicCall(
const CallInst &
I,
6344 unsigned Intrinsic) {
6351 if (
auto *FPOp = dyn_cast<FPMathOperator>(&
I))
6352 Flags.copyFMF(*FPOp);
6354 switch (Intrinsic) {
6357 visitTargetIntrinsic(
I, Intrinsic);
6359 case Intrinsic::vscale: {
6364 case Intrinsic::vastart: visitVAStart(
I);
return;
6365 case Intrinsic::vaend: visitVAEnd(
I);
return;
6366 case Intrinsic::vacopy: visitVACopy(
I);
return;
6367 case Intrinsic::returnaddress:
6372 case Intrinsic::addressofreturnaddress:
6377 case Intrinsic::sponentry:
6382 case Intrinsic::frameaddress:
6387 case Intrinsic::read_volatile_register:
6388 case Intrinsic::read_register: {
6392 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6400 case Intrinsic::write_register: {
6402 Value *RegValue =
I.getArgOperand(1);
6405 DAG.
getMDNode(cast<MDNode>(cast<MetadataAsValue>(Reg)->getMetadata()));
6410 case Intrinsic::memcpy: {
6411 const auto &MCI = cast<MemCpyInst>(
I);
6416 Align DstAlign = MCI.getDestAlign().valueOrOne();
6417 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6418 Align Alignment = std::min(DstAlign, SrcAlign);
6419 bool isVol = MCI.isVolatile();
6425 Root, sdl, Op1, Op2, Op3, Alignment, isVol,
6428 updateDAGForMaybeTailCall(MC);
6431 case Intrinsic::memcpy_inline: {
6432 const auto &MCI = cast<MemCpyInlineInst>(
I);
6436 assert(isa<ConstantSDNode>(
Size) &&
"memcpy_inline needs constant size");
6438 Align DstAlign = MCI.getDestAlign().valueOrOne();
6439 Align SrcAlign = MCI.getSourceAlign().valueOrOne();
6440 Align Alignment = std::min(DstAlign, SrcAlign);
6441 bool isVol = MCI.isVolatile();
6449 updateDAGForMaybeTailCall(MC);
6452 case Intrinsic::memset: {
6453 const auto &MSI = cast<MemSetInst>(
I);
6458 Align Alignment = MSI.getDestAlign().valueOrOne();
6459 bool isVol = MSI.isVolatile();
6463 Root, sdl, Op1, Op2, Op3, Alignment, isVol,
false,
6465 updateDAGForMaybeTailCall(MS);
6468 case Intrinsic::memset_inline: {
6469 const auto &MSII = cast<MemSetInlineInst>(
I);
6473 assert(isa<ConstantSDNode>(
Size) &&
"memset_inline needs constant size");
6475 Align DstAlign = MSII.getDestAlign().valueOrOne();
6476 bool isVol = MSII.isVolatile();
6483 updateDAGForMaybeTailCall(MC);
6486 case Intrinsic::memmove: {
6487 const auto &MMI = cast<MemMoveInst>(
I);
6492 Align DstAlign = MMI.getDestAlign().valueOrOne();
6493 Align SrcAlign = MMI.getSourceAlign().valueOrOne();
6494 Align Alignment = std::min(DstAlign, SrcAlign);
6495 bool isVol = MMI.isVolatile();
6503 I.getAAMetadata(),
AA);
6504 updateDAGForMaybeTailCall(MM);
6507 case Intrinsic::memcpy_element_unordered_atomic: {
6513 Type *LengthTy =
MI.getLength()->getType();
6514 unsigned ElemSz =
MI.getElementSizeInBytes();
6520 updateDAGForMaybeTailCall(MC);
6523 case Intrinsic::memmove_element_unordered_atomic: {
6524 auto &
MI = cast<AtomicMemMoveInst>(
I);
6529 Type *LengthTy =
MI.getLength()->getType();
6530 unsigned ElemSz =
MI.getElementSizeInBytes();
6536 updateDAGForMaybeTailCall(MC);
6539 case Intrinsic::memset_element_unordered_atomic: {
6540 auto &
MI = cast<AtomicMemSetInst>(
I);
6545 Type *LengthTy =
MI.getLength()->getType();
6546 unsigned ElemSz =
MI.getElementSizeInBytes();
6551 updateDAGForMaybeTailCall(MC);
6554 case Intrinsic::call_preallocated_setup: {
6563 case Intrinsic::call_preallocated_arg: {
6578 case Intrinsic::dbg_declare: {
6579 const auto &DI = cast<DbgDeclareInst>(
I);
6582 if (AssignmentTrackingEnabled ||
6585 LLVM_DEBUG(
dbgs() <<
"SelectionDAG visiting dbg_declare: " << DI <<
"\n");
6591 assert(!DI.hasArgList() &&
"Only dbg.value should currently use DIArgList");
6596 case Intrinsic::dbg_label: {
6599 assert(Label &&
"Missing label");
6606 case Intrinsic::dbg_assign: {
6608 if (AssignmentTrackingEnabled)
6614 case Intrinsic::dbg_value: {
6616 if (AssignmentTrackingEnabled)
6636 SDNodeOrder, IsVariadic))
6642 case Intrinsic::eh_typeid_for: {
6651 case Intrinsic::eh_return_i32:
6652 case Intrinsic::eh_return_i64:
6660 case Intrinsic::eh_unwind_init:
6663 case Intrinsic::eh_dwarf_cfa:
6668 case Intrinsic::eh_sjlj_callsite: {
6670 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(0));
6676 case Intrinsic::eh_sjlj_functioncontext: {
6680 cast<AllocaInst>(
I.getArgOperand(0)->stripPointerCasts());
6685 case Intrinsic::eh_sjlj_setjmp: {
6695 case Intrinsic::eh_sjlj_longjmp:
6699 case Intrinsic::eh_sjlj_setup_dispatch:
6703 case Intrinsic::masked_gather:
6704 visitMaskedGather(
I);
6706 case Intrinsic::masked_load:
6709 case Intrinsic::masked_scatter:
6710 visitMaskedScatter(
I);
6712 case Intrinsic::masked_store:
6713 visitMaskedStore(
I);
6715 case Intrinsic::masked_expandload:
6716 visitMaskedLoad(
I,
true );
6718 case Intrinsic::masked_compressstore:
6719 visitMaskedStore(
I,
true );
6721 case Intrinsic::powi:
6725 case Intrinsic::log:
6728 case Intrinsic::log2:
6732 case Intrinsic::log10:
6736 case Intrinsic::exp:
6739 case Intrinsic::exp2:
6743 case Intrinsic::pow:
6747 case Intrinsic::sqrt:
6748 case Intrinsic::fabs:
6749 case Intrinsic::sin:
6750 case Intrinsic::cos:
6751 case Intrinsic::exp10:
6752 case Intrinsic::floor:
6753 case Intrinsic::ceil:
6754 case Intrinsic::trunc:
6755 case Intrinsic::rint:
6756 case Intrinsic::nearbyint:
6757 case Intrinsic::round:
6758 case Intrinsic::roundeven:
6759 case Intrinsic::canonicalize: {
6762 switch (Intrinsic) {
6764 case Intrinsic::sqrt: Opcode =
ISD::FSQRT;
break;
6765 case Intrinsic::fabs: Opcode =
ISD::FABS;
break;
6766 case Intrinsic::sin: Opcode =
ISD::FSIN;
break;
6767 case Intrinsic::cos: Opcode =
ISD::FCOS;
break;
6768 case Intrinsic::exp10: Opcode =
ISD::FEXP10;
break;
6769 case Intrinsic::floor: Opcode =
ISD::FFLOOR;
break;
6770 case Intrinsic::ceil: Opcode =
ISD::FCEIL;
break;
6771 case Intrinsic::trunc: Opcode =
ISD::FTRUNC;
break;
6772 case Intrinsic::rint: Opcode =
ISD::FRINT;
break;
6774 case Intrinsic::round: Opcode =
ISD::FROUND;
break;
6785 case Intrinsic::lround:
6786 case Intrinsic::llround:
6787 case Intrinsic::lrint:
6788 case Intrinsic::llrint: {
6791 switch (Intrinsic) {
6793 case Intrinsic::lround: Opcode =
ISD::LROUND;
break;
6795 case Intrinsic::lrint: Opcode =
ISD::LRINT;
break;
6796 case Intrinsic::llrint: Opcode =
ISD::LLRINT;
break;
6805 case Intrinsic::minnum:
6811 case Intrinsic::maxnum:
6817 case Intrinsic::minimum:
6823 case Intrinsic::maximum:
6829 case Intrinsic::copysign:
6835 case Intrinsic::ldexp:
6841 case Intrinsic::frexp: {
6849 case Intrinsic::arithmetic_fence: {
6855 case Intrinsic::fma:
6861#define INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC) \
6862 case Intrinsic::INTRINSIC:
6863#include "llvm/IR/ConstrainedOps.def"
6864 visitConstrainedFPIntrinsic(cast<ConstrainedFPIntrinsic>(
I));
6866#define BEGIN_REGISTER_VP_INTRINSIC(VPID, ...) case Intrinsic::VPID:
6867#include "llvm/IR/VPIntrinsics.def"
6868 visitVectorPredicationIntrinsic(cast<VPIntrinsic>(
I));
6870 case Intrinsic::fptrunc_round: {
6873 Metadata *MD = cast<MetadataAsValue>(
I.getArgOperand(1))->getMetadata();
6874 std::optional<RoundingMode> RoundMode =
6881 Flags.copyFMF(*cast<FPMathOperator>(&
I));
6893 case Intrinsic::fmuladd: {
6914 case Intrinsic::convert_to_fp16:
6921 case Intrinsic::convert_from_fp16:
6927 case Intrinsic::fptosi_sat: {
6934 case Intrinsic::fptoui_sat: {
6941 case Intrinsic::set_rounding:
6947 case Intrinsic::is_fpclass: {
6952 cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue());
6957 Flags.setNoFPExcept(
6958 !
F.getAttributes().hasFnAttr(llvm::Attribute::StrictFP));
6973 case Intrinsic::get_fpenv: {
6988 int SPFI = cast<FrameIndexSDNode>(Temp.
getNode())->getIndex();
6995 Res =
DAG.
getLoad(EnvVT, sdl, Chain, Temp, MPI);
7001 case Intrinsic::set_fpenv: {
7015 int SPFI = cast<FrameIndexSDNode>(Temp.
getNode())->getIndex();
7018 Chain =
DAG.
getStore(Chain, sdl, Env, Temp, MPI, TempAlign,
7028 case Intrinsic::reset_fpenv:
7031 case Intrinsic::get_fpmode:
7040 case Intrinsic::set_fpmode:
7045 case Intrinsic::reset_fpmode: {
7050 case Intrinsic::pcmarker: {
7055 case Intrinsic::readcyclecounter: {
7063 case Intrinsic::readsteadycounter: {
7071 case Intrinsic::bitreverse:
7076 case Intrinsic::bswap:
7081 case Intrinsic::cttz: {
7083 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(1));
7089 case Intrinsic::ctlz: {
7091 ConstantInt *CI = cast<ConstantInt>(
I.getArgOperand(1));
7097 case Intrinsic::ctpop: {
7103 case Intrinsic::fshl:
7104 case Intrinsic::fshr: {
7105 bool IsFSHL =
Intrinsic == Intrinsic::fshl;
7109 EVT VT =
X.getValueType();
7120 case Intrinsic::sadd_sat: {
7126 case Intrinsic::uadd_sat: {
7132 case Intrinsic::ssub_sat: {
7138 case Intrinsic::usub_sat: {
7144 case Intrinsic::sshl_sat: {
7150 case Intrinsic::ushl_sat: {
7156 case Intrinsic::smul_fix:
7157 case Intrinsic::umul_fix:
7158 case Intrinsic::smul_fix_sat:
7159 case Intrinsic::umul_fix_sat: {
7167 case Intrinsic::sdiv_fix:
7168 case Intrinsic::udiv_fix:
7169 case Intrinsic::sdiv_fix_sat:
7170 case Intrinsic::udiv_fix_sat: {
7175 Op1, Op2, Op3,
DAG, TLI));
7178 case Intrinsic::smax: {
7184 case Intrinsic::smin: {
7190 case Intrinsic::umax: {
7196 case Intrinsic::umin: {
7202 case Intrinsic::abs: {
7208 case Intrinsic::stacksave: {
7216 case Intrinsic::stackrestore:
7220 case Intrinsic::get_dynamic_area_offset: {
7235 case Intrinsic::stackguard: {
7256 case Intrinsic::stackprotector: {
7277 Chain, sdl, Src, FIN,
7284 case Intrinsic::objectsize:
7287 case Intrinsic::is_constant:
7290 case Intrinsic::annotation:
7291 case Intrinsic::ptr_annotation:
7292 case Intrinsic::launder_invariant_group:
7293 case Intrinsic::strip_invariant_group:
7298 case Intrinsic::assume:
7299 case Intrinsic::experimental_noalias_scope_decl:
7300 case Intrinsic::var_annotation:
7301 case Intrinsic::sideeffect:
7306 case Intrinsic::codeview_annotation: {
7311 Metadata *MD = cast<MetadataAsValue>(
I.getArgOperand(0))->getMetadata();
7318 case Intrinsic::init_trampoline: {
7319 const Function *
F = cast<Function>(
I.getArgOperand(1)->stripPointerCasts());
7334 case Intrinsic::adjust_trampoline:
7339 case Intrinsic::gcroot: {
7341 "only valid in functions with gc specified, enforced by Verifier");
7343 const Value *Alloca =
I.getArgOperand(0)->stripPointerCasts();
7344 const Constant *TypeMap = cast<Constant>(
I.getArgOperand(1));
7350 case Intrinsic::gcread:
7351 case Intrinsic::gcwrite:
7353 case Intrinsic::get_rounding:
7359 case Intrinsic::expect:
7364 case Intrinsic::ubsantrap:
7365 case Intrinsic::debugtrap:
7366 case Intrinsic::trap: {
7368 I.getAttributes().getFnAttr(
"trap-func-name").getValueAsString();
7369 if (TrapFuncName.
empty()) {
7370 switch (Intrinsic) {
7371 case Intrinsic::trap:
7374 case Intrinsic::debugtrap:
7377 case Intrinsic::ubsantrap:
7381 cast<ConstantInt>(
I.getArgOperand(0))->getZExtValue(), sdl,
7389 if (Intrinsic == Intrinsic::ubsantrap) {
7391 Args[0].Val =
I.getArgOperand(0);
7393 Args[0].Ty =
Args[0].Val->getType();
7397 CLI.setDebugLoc(sdl).setChain(
getRoot()).setLibCallee(
7408 case Intrinsic::allow_runtime_check:
7409 case Intrinsic::allow_ubsan_check:
7413 case Intrinsic::uadd_with_overflow:
7414 case Intrinsic::sadd_with_overflow:
7415 case Intrinsic::usub_with_overflow:
7416 case Intrinsic::ssub_with_overflow:
7417 case Intrinsic::umul_with_overflow:
7418 case Intrinsic::smul_with_overflow: {
7420 switch (Intrinsic) {
7422 case Intrinsic::uadd_with_overflow:
Op =
ISD::UADDO;
break;
7423 case Intrinsic::sadd_with_overflow:
Op =
ISD::SADDO;
break;
7424 case Intrinsic::usub_with_overflow:
Op =
ISD::USUBO;
break;
7425 case Intrinsic::ssub_with_overflow:
Op =
ISD::SSUBO;
break;
7426 case Intrinsic::umul_with_overflow:
Op =
ISD::UMULO;
break;
7427 case Intrinsic::smul_with_overflow:
Op =
ISD::SMULO;
break;
7433 EVT OverflowVT = MVT::i1;
7442 case Intrinsic::prefetch: {
7444 unsigned rw = cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue();
7457 std::nullopt, Flags);
7466 case Intrinsic::lifetime_start:
7467 case Intrinsic::lifetime_end: {
7468 bool IsStart = (
Intrinsic == Intrinsic::lifetime_start);
7473 const int64_t ObjectSize =
7474 cast<ConstantInt>(
I.getArgOperand(0))->getSExtValue();
7479 for (
const Value *Alloca : Allocas) {
7480 const AllocaInst *LifetimeObject = dyn_cast_or_null<AllocaInst>(Alloca);
7483 if (!LifetimeObject)
7503 case Intrinsic::pseudoprobe: {
7504 auto Guid = cast<ConstantInt>(
I.getArgOperand(0))->getZExtValue();
7505 auto Index = cast<ConstantInt>(
I.getArgOperand(1))->getZExtValue();
7506 auto Attr = cast<ConstantInt>(
I.getArgOperand(2))->getZExtValue();
7511 case Intrinsic::invariant_start:
7516 case Intrinsic::invariant_end:
7519 case Intrinsic::clear_cache:
7522 lowerCallToExternalSymbol(
I, FunctionName);
7524 case Intrinsic::donothing:
7525 case Intrinsic::seh_try_begin:
7526 case Intrinsic::seh_scope_begin:
7527 case Intrinsic::seh_try_end:
7528 case Intrinsic::seh_scope_end:
7531 case Intrinsic::experimental_stackmap:
7534 case Intrinsic::experimental_patchpoint_void:
7535 case Intrinsic::experimental_patchpoint:
7538 case Intrinsic::experimental_gc_statepoint:
7541 case Intrinsic::experimental_gc_result:
7542 visitGCResult(cast<GCResultInst>(
I));
7544 case Intrinsic::experimental_gc_relocate:
7545 visitGCRelocate(cast<GCRelocateInst>(
I));
7547 case Intrinsic::instrprof_cover:
7549 case Intrinsic::instrprof_increment:
7551 case Intrinsic::instrprof_timestamp:
7553 case Intrinsic::instrprof_value_profile:
7555 case Intrinsic::instrprof_mcdc_parameters:
7557 case Intrinsic::instrprof_mcdc_tvbitmap_update:
7559 case Intrinsic::instrprof_mcdc_condbitmap_update:
7561 case Intrinsic::localescape: {
7567 for (
unsigned Idx = 0, E =
I.arg_size();
Idx < E; ++
Idx) {
7568 Value *Arg =
I.getArgOperand(
Idx)->stripPointerCasts();
7569 if (isa<ConstantPointerNull>(Arg))
7573 "can only escape static allocas");
7579 TII->get(TargetOpcode::LOCAL_ESCAPE))
7587 case Intrinsic::localrecover: {
7592 auto *Fn = cast<Function>(
I.getArgOperand(0)->stripPointerCasts());
7593 auto *
Idx = cast<ConstantInt>(
I.getArgOperand(2));
7595 unsigned(
Idx->getLimitedValue(std::numeric_limits<int>::max()));
7617 case Intrinsic::eh_exceptionpointer:
7618 case Intrinsic::eh_exceptioncode: {
7620 const auto *CPI = cast<CatchPadInst>(
I.getArgOperand(0));
7625 if (Intrinsic == Intrinsic::eh_exceptioncode)
7630 case Intrinsic::xray_customevent: {
7659 case Intrinsic::xray_typedevent: {
7686 TargetOpcode::PATCHABLE_TYPED_EVENT_CALL, sdl, NodeTys, Ops);
7692 case Intrinsic::experimental_deoptimize:
7695 case Intrinsic::experimental_stepvector:
7698 case Intrinsic::vector_reduce_fadd:
7699 case Intrinsic::vector_reduce_fmul:
7700 case Intrinsic::vector_reduce_add:
7701 case Intrinsic::vector_reduce_mul:
7702 case Intrinsic::vector_reduce_and:
7703 case Intrinsic::vector_reduce_or:
7704 case Intrinsic::vector_reduce_xor:
7705 case Intrinsic::vector_reduce_smax:
7706 case Intrinsic::vector_reduce_smin:
7707 case Intrinsic::vector_reduce_umax:
7708 case Intrinsic::vector_reduce_umin:
7709 case Intrinsic::vector_reduce_fmax:
7710 case Intrinsic::vector_reduce_fmin:
7711 case Intrinsic::vector_reduce_fmaximum:
7712 case Intrinsic::vector_reduce_fminimum:
7713 visitVectorReduce(
I, Intrinsic);
7716 case Intrinsic::icall_branch_funnel: {
7725 "llvm.icall.branch.funnel operand must be a GlobalValue");
7728 struct BranchFunnelTarget {
7734 for (
unsigned Op = 1,
N =
I.arg_size();
Op !=
N;
Op += 2) {
7737 if (ElemBase !=
Base)
7739 "to the same GlobalValue");
7742 auto *GA = dyn_cast<GlobalAddressSDNode>(Val);
7745 "llvm.icall.branch.funnel operand must be a GlobalValue");
7751 [](
const BranchFunnelTarget &T1,
const BranchFunnelTarget &T2) {
7752 return T1.Offset < T2.Offset;
7755 for (
auto &
T : Targets) {
7770 case Intrinsic::wasm_landingpad_index:
7776 case Intrinsic::aarch64_settag:
7777 case Intrinsic::aarch64_settag_zero: {
7779 bool ZeroMemory =
Intrinsic == Intrinsic::aarch64_settag_zero;
7788 case Intrinsic::amdgcn_cs_chain: {
7789 assert(
I.arg_size() == 5 &&
"Additional args not supported yet");
7790 assert(cast<ConstantInt>(
I.getOperand(4))->isZero() &&
7791 "Non-zero flags not supported yet");
7807 for (
unsigned Idx : {2, 3, 1}) {
7810 Arg.
Ty =
I.getOperand(
Idx)->getType();
7812 Args.push_back(Arg);
7815 assert(Args[0].IsInReg &&
"SGPR args should be marked inreg");
7816 assert(!Args[1].IsInReg &&
"VGPR args should not be marked inreg");
7817 Args[2].IsInReg =
true;
7822 .setCallee(
CC,
RetTy, Callee, std::move(Args))
7825 .setConvergent(
I.isConvergent());
7827 std::pair<SDValue, SDValue>
Result =
7831 "Should've lowered as tail call");
7836 case Intrinsic::ptrmask: {
7840 EVT PtrVT =
Ptr.getValueType();
7842 "Pointers with different index type are not supported by SDAG");
7846 case Intrinsic::threadlocal_address: {
7850 case Intrinsic::get_active_lane_mask: {
7853 EVT ElementVT =
Index.getValueType();
7856 visitTargetIntrinsic(
I, Intrinsic);
7874 case Intrinsic::experimental_get_vector_length: {
7875 assert(cast<ConstantInt>(
I.getOperand(1))->getSExtValue() > 0 &&
7876 "Expected positive VF");
7877 unsigned VF = cast<ConstantInt>(
I.getOperand(1))->getZExtValue();
7878 bool IsScalable = cast<ConstantInt>(
I.getOperand(2))->isOne();
7884 visitTargetIntrinsic(
I, Intrinsic);
7893 if (CountVT.
bitsLT(VT)) {
7908 case Intrinsic::experimental_cttz_elts: {
7911 EVT OpVT =
Op.getValueType();
7914 visitTargetIntrinsic(
I, Intrinsic);
7929 !cast<ConstantSDNode>(
getValue(
I.getOperand(1)))->isZero();
7931 if (isa<ScalableVectorType>(
I.getOperand(0)->getType()))
7959 case Intrinsic::vector_insert: {
7967 if (
Index.getValueType() != VectorIdxTy)
7975 case Intrinsic::vector_extract: {
7983 if (
Index.getValueType() != VectorIdxTy)
7990 case Intrinsic::vector_reverse:
7991 visitVectorReverse(
I);
7993 case Intrinsic::vector_splice:
7994 visitVectorSplice(
I);
7996 case Intrinsic::callbr_landingpad:
7997 visitCallBrLandingPad(
I);
7999 case Intrinsic::vector_interleave2:
8000 visitVectorInterleave(
I);
8002 case Intrinsic::vector_deinterleave2:
8003 visitVectorDeinterleave(
I);
8005 case Intrinsic::experimental_convergence_anchor:
8006 case Intrinsic::experimental_convergence_entry:
8007 case Intrinsic::experimental_convergence_loop:
8008 visitConvergenceControl(
I, Intrinsic);
8010 case Intrinsic::experimental_vector_histogram_add: {
8011 visitVectorHistogram(
I, Intrinsic);
8017void SelectionDAGBuilder::visitConstrainedFPIntrinsic(
8045 PendingConstrainedFP.push_back(OutChain);
8051 PendingConstrainedFPStrict.push_back(OutChain);
8063 Flags.setNoFPExcept(
true);
8065 if (
auto *FPOp = dyn_cast<FPMathOperator>(&FPI))
8066 Flags.copyFMF(*FPOp);
8071#define DAG_INSTRUCTION(NAME, NARG, ROUND_MODE, INTRINSIC, DAGN) \
8072 case Intrinsic::INTRINSIC: \
8073 Opcode = ISD::STRICT_##DAGN; \
8075#include "llvm/IR/ConstrainedOps.def"
8076 case Intrinsic::experimental_constrained_fmuladd: {
8083 pushOutChain(
Mul, EB);
8104 auto *
FPCmp = dyn_cast<ConstrainedFPCmpIntrinsic>(&FPI);
8114 pushOutChain(Result, EB);
8121 std::optional<unsigned> ResOPC;
8123 case Intrinsic::vp_ctlz: {
8124 bool IsZeroUndef = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8125 ResOPC = IsZeroUndef ? ISD::VP_CTLZ_ZERO_UNDEF : ISD::VP_CTLZ;
8128 case Intrinsic::vp_cttz: {
8129 bool IsZeroUndef = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8130 ResOPC = IsZeroUndef ? ISD::VP_CTTZ_ZERO_UNDEF : ISD::VP_CTTZ;
8133 case Intrinsic::vp_cttz_elts: {
8134 bool IsZeroPoison = cast<ConstantInt>(VPIntrin.
getArgOperand(1))->isOne();
8135 ResOPC = IsZeroPoison ? ISD::VP_CTTZ_ELTS_ZERO_UNDEF : ISD::VP_CTTZ_ELTS;
8138#define HELPER_MAP_VPID_TO_VPSD(VPID, VPSD) \
8139 case Intrinsic::VPID: \
8140 ResOPC = ISD::VPSD; \
8142#include "llvm/IR/VPIntrinsics.def"
8147 "Inconsistency: no SDNode available for this VPIntrinsic!");
8149 if (*ResOPC == ISD::VP_REDUCE_SEQ_FADD ||
8150 *ResOPC == ISD::VP_REDUCE_SEQ_FMUL) {
8152 return *ResOPC == ISD::VP_REDUCE_SEQ_FADD ? ISD::VP_REDUCE_FADD
8153 : ISD::VP_REDUCE_FMUL;
8159void SelectionDAGBuilder::visitVPLoad(
8185void SelectionDAGBuilder::visitVPGather(
8221 {DAG.getRoot(), Base, Index, Scale, OpValues[1], OpValues[2]}, MMO,
8227void SelectionDAGBuilder::visitVPStore(
8231 EVT VT = OpValues[0].getValueType();
8249void SelectionDAGBuilder::visitVPScatter(
8254 EVT VT = OpValues[0].getValueType();
8284 {getMemoryRoot(), OpValues[0], Base, Index, Scale,
8285 OpValues[2], OpValues[3]},
8291void SelectionDAGBuilder::visitVPStridedLoad(
8310 OpValues[2], OpValues[3], MMO,
8318void SelectionDAGBuilder::visitVPStridedStore(
8322 EVT VT = OpValues[0].getValueType();
8334 DAG.
getUNDEF(OpValues[1].getValueType()), OpValues[2], OpValues[3],
8342void SelectionDAGBuilder::visitVPCmp(
const VPCmpIntrinsic &VPIntrin) {
8367 "Unexpected target EVL type");
8376void SelectionDAGBuilder::visitVectorPredicationIntrinsic(
8383 if (
const auto *CmpI = dyn_cast<VPCmpIntrinsic>(&VPIntrin))
8384 return visitVPCmp(*CmpI);
8395 "Unexpected target EVL type");
8399 for (
unsigned I = 0;
I < VPIntrin.
arg_size(); ++
I) {
8401 if (
I == EVLParamPos)
8409 if (
auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
8416 visitVPLoad(VPIntrin, ValueVTs[0], OpValues);
8418 case ISD::VP_GATHER:
8419 visitVPGather(VPIntrin, ValueVTs[0], OpValues);
8421 case ISD::EXPERIMENTAL_VP_STRIDED_LOAD:
8422 visitVPStridedLoad(VPIntrin, ValueVTs[0], OpValues);
8425 visitVPStore(VPIntrin, OpValues);
8427 case ISD::VP_SCATTER:
8428 visitVPScatter(VPIntrin, OpValues);
8430 case ISD::EXPERIMENTAL_VP_STRIDED_STORE:
8431 visitVPStridedStore(VPIntrin, OpValues);
8433 case ISD::VP_FMULADD: {
8434 assert(OpValues.
size() == 5 &&
"Unexpected number of operands");
8436 if (
auto *FPMO = dyn_cast<FPMathOperator>(&VPIntrin))
8443 ISD::VP_FMUL,
DL, VTs,
8444 {OpValues[0], OpValues[1], OpValues[3], OpValues[4]}, SDFlags);
8447 {
Mul, OpValues[2], OpValues[3], OpValues[4]}, SDFlags);
8452 case ISD::VP_IS_FPCLASS: {
8455 auto Constant = OpValues[1]->getAsZExtVal();
8458 {OpValues[0],
Check, OpValues[2], OpValues[3]});
8462 case ISD::VP_INTTOPTR: {
8473 case ISD::VP_PTRTOINT: {
8488 case ISD::VP_CTLZ_ZERO_UNDEF:
8490 case ISD::VP_CTTZ_ZERO_UNDEF:
8491 case ISD::VP_CTTZ_ELTS_ZERO_UNDEF:
8492 case ISD::VP_CTTZ_ELTS: {
8494 DAG.
getNode(Opcode,
DL, VTs, {OpValues[0], OpValues[2], OpValues[3]});
8514 if (CallSiteIndex) {
8528 assert(BeginLabel &&
"BeginLabel should've been set");
8543 assert(II &&
"II should've been set");
8554std::pair<SDValue, SDValue>
8568 std::pair<SDValue, SDValue> Result = TLI.
LowerCallTo(CLI);
8571 "Non-null chain expected with non-tail call!");
8572 assert((Result.second.getNode() || !Result.first.getNode()) &&
8573 "Null value expected with tail call!");
8575 if (!Result.second.getNode()) {
8582 PendingExports.clear();
8597 bool isMustTailCall,
8606 const Value *SwiftErrorVal =
nullptr;
8613 if (Caller->getFnAttribute(
"disable-tail-calls").getValueAsString() ==
8614 "true" && !isMustTailCall)
8621 Caller->getAttributes().hasAttrSomewhere(Attribute::SwiftError))
8630 if (V->getType()->isEmptyTy())
8634 Entry.Node = ArgNode; Entry.Ty = V->getType();
8636 Entry.setAttributes(&CB,
I - CB.
arg_begin());
8648 Args.push_back(Entry);
8652 if (Entry.IsSRet && isa<Instruction>(V))
8660 Value *V = Bundle->Inputs[0];
8662 Entry.Node = ArgNode;
8663 Entry.Ty = V->getType();
8664 Entry.IsCFGuardTarget =
true;
8665 Args.push_back(Entry);
8683 "Target doesn't support calls with kcfi operand bundles.");
8684 CFIType = cast<ConstantInt>(Bundle->Inputs[0]);
8691 auto *Token = Bundle->Inputs[0].get();
8692 ConvControlToken =
getValue(Token);
8705 std::pair<SDValue, SDValue> Result =
lowerInvokable(CLI, EHPadBB);
8707 if (Result.first.getNode()) {
8729 if (
const Constant *LoadInput = dyn_cast<Constant>(PtrVal)) {
8748 bool ConstantMemory =
false;
8753 ConstantMemory =
true;
8764 if (!ConstantMemory)
8771void SelectionDAGBuilder::processIntegerCallValue(
const Instruction &
I,
8785bool SelectionDAGBuilder::visitMemCmpBCmpCall(
const CallInst &
I) {
8786 const Value *
LHS =
I.getArgOperand(0), *
RHS =
I.getArgOperand(1);
8800 if (Res.first.getNode()) {
8801 processIntegerCallValue(
I, Res.first,
true);
8815 auto hasFastLoadsAndCompare = [&](
unsigned NumBits) {
8838 switch (NumBitsToCompare) {
8850 LoadVT = hasFastLoadsAndCompare(NumBitsToCompare);
8868 processIntegerCallValue(
I, Cmp,
false);
8877bool SelectionDAGBuilder::visitMemChrCall(
const CallInst &
I) {
8878 const Value *Src =
I.getArgOperand(0);
8883 std::pair<SDValue, SDValue> Res =
8887 if (Res.first.getNode()) {
8901bool SelectionDAGBuilder::visitMemPCpyCall(
const CallInst &
I) {
8909 Align Alignment = std::min(DstAlign, SrcAlign);
8923 "** memcpy should not be lowered as TailCall in mempcpy context **");
8941bool SelectionDAGBuilder::visitStrCpyCall(
const CallInst &
I,
bool isStpcpy) {
8942 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
8945 std::pair<SDValue, SDValue> Res =
8950 if (Res.first.getNode()) {
8964bool SelectionDAGBuilder::visitStrCmpCall(
const CallInst &
I) {
8965 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
8968 std::pair<SDValue, SDValue> Res =
8973 if (Res.first.getNode()) {
8974 processIntegerCallValue(
I, Res.first,
true);
8987bool SelectionDAGBuilder::visitStrLenCall(
const CallInst &
I) {
8988 const Value *Arg0 =
I.getArgOperand(0);
8991 std::pair<SDValue, SDValue> Res =
8994 if (Res.first.getNode()) {
8995 processIntegerCallValue(
I, Res.first,
false);
9008bool SelectionDAGBuilder::visitStrNLenCall(
const CallInst &
I) {
9009 const Value *Arg0 =
I.getArgOperand(0), *Arg1 =
I.getArgOperand(1);
9012 std::pair<SDValue, SDValue> Res =
9016 if (Res.first.getNode()) {
9017 processIntegerCallValue(
I, Res.first,
false);
9030bool SelectionDAGBuilder::visitUnaryFloatCall(
const CallInst &
I,
9033 if (!
I.onlyReadsMemory())
9037 Flags.copyFMF(cast<FPMathOperator>(
I));
9050bool SelectionDAGBuilder::visitBinaryFloatCall(
const CallInst &
I,
9053 if (!
I.onlyReadsMemory())
9057 Flags.copyFMF(cast<FPMathOperator>(
I));
9066void SelectionDAGBuilder::visitCall(
const CallInst &
I) {
9068 if (
I.isInlineAsm()) {
9076 if (
F->isDeclaration()) {
9078 unsigned IID =
F->getIntrinsicID();
9084 visitIntrinsicCall(
I, IID);
9093 if (!
I.isNoBuiltin() && !
I.isStrictFP() && !
F->hasLocalLinkage() &&
9099 if (visitMemCmpBCmpCall(
I))
9102 case LibFunc_copysign:
9103 case LibFunc_copysignf:
9104 case LibFunc_copysignl:
9107 if (
I.onlyReadsMemory()) {
9111 LHS.getValueType(), LHS, RHS));
9148 case LibFunc_sqrt_finite:
9149 case LibFunc_sqrtf_finite:
9150 case LibFunc_sqrtl_finite:
9155 case LibFunc_floorf:
9156 case LibFunc_floorl:
9160 case LibFunc_nearbyint:
9161 case LibFunc_nearbyintf:
9162 case LibFunc_nearbyintl:
9179 case LibFunc_roundf:
9180 case LibFunc_roundl:
9185 case LibFunc_truncf:
9186 case LibFunc_truncl:
9203 case LibFunc_exp10f:
9204 case LibFunc_exp10l:
9209 case LibFunc_ldexpf:
9210 case LibFunc_ldexpl:
9214 case LibFunc_memcmp:
9215 if (visitMemCmpBCmpCall(
I))
9218 case LibFunc_mempcpy:
9219 if (visitMemPCpyCall(
I))
9222 case LibFunc_memchr:
9223 if (visitMemChrCall(
I))
9226 case LibFunc_strcpy:
9227 if (visitStrCpyCall(
I,
false))
9230 case LibFunc_stpcpy:
9231 if (visitStrCpyCall(
I,
true))
9234 case LibFunc_strcmp:
9235 if (visitStrCmpCall(
I))
9238 case LibFunc_strlen:
9239 if (visitStrLenCall(
I))
9242 case LibFunc_strnlen:
9243 if (visitStrNLenCall(
I))
9253 assert(!
I.hasOperandBundlesOtherThan(
9254 {LLVMContext::OB_deopt, LLVMContext::OB_funclet,
9255 LLVMContext::OB_cfguardtarget, LLVMContext::OB_preallocated,
9256 LLVMContext::OB_clang_arc_attachedcall, LLVMContext::OB_kcfi,
9257 LLVMContext::OB_convergencectrl}) &&
9258 "Cannot lower calls with arbitrary operand bundles!");
9262 if (
I.hasDeoptState())
9296 for (
const auto &Code : Codes)
9311 SDISelAsmOperandInfo &MatchingOpInfo,
9313 if (OpInfo.ConstraintVT == MatchingOpInfo.ConstraintVT)
9319 std::pair<unsigned, const TargetRegisterClass *> MatchRC =
9321 OpInfo.ConstraintVT);
9322 std::pair<unsigned, const TargetRegisterClass *> InputRC =
9324 MatchingOpInfo.ConstraintVT);
9325 if ((OpInfo.ConstraintVT.isInteger() !=
9326 MatchingOpInfo.ConstraintVT.isInteger()) ||
9327 (MatchRC.second != InputRC.second)) {
9330 " with a matching output constraint of"
9331 " incompatible type!");
9333 MatchingOpInfo.ConstraintVT = OpInfo.ConstraintVT;
9340 SDISelAsmOperandInfo &OpInfo,
9353 const Value *OpVal = OpInfo.CallOperandVal;
9354 if (isa<ConstantFP>(OpVal) || isa<ConstantInt>(OpVal) ||
9355 isa<ConstantVector>(OpVal) || isa<ConstantDataVector>(OpVal)) {
9367 TySize,
DL.getPrefTypeAlign(Ty),
false);
9369 Chain = DAG.
getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
9372 OpInfo.CallOperand = StackSlot;
9385static std::optional<unsigned>
9387 SDISelAsmOperandInfo &OpInfo,
9388 SDISelAsmOperandInfo &RefOpInfo) {
9399 return std::nullopt;
9403 unsigned AssignedReg;
9406 &
TRI, RefOpInfo.ConstraintCode, RefOpInfo.ConstraintVT);
9409 return std::nullopt;
9414 const MVT RegVT = *
TRI.legalclasstypes_begin(*RC);
9416 if (OpInfo.ConstraintVT != MVT::Other && RegVT != MVT::Untyped) {
9425 !
TRI.isTypeLegalForClass(*RC, OpInfo.ConstraintVT)) {
9430 if (RegVT.
getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
9435 OpInfo.CallOperand =
9437 OpInfo.ConstraintVT = RegVT;
9441 }
else if (RegVT.
isInteger() && OpInfo.ConstraintVT.isFloatingPoint()) {
9444 OpInfo.CallOperand =
9446 OpInfo.ConstraintVT = VT;
9453 if (OpInfo.isMatchingInputConstraint())
9454 return std::nullopt;
9456 EVT ValueVT = OpInfo.ConstraintVT;
9457 if (OpInfo.ConstraintVT == MVT::Other)
9461 unsigned NumRegs = 1;
9462 if (OpInfo.ConstraintVT != MVT::Other)
9477 I = std::find(
I, RC->
end(), AssignedReg);
9478 if (
I == RC->
end()) {
9481 return {AssignedReg};
9485 for (; NumRegs; --NumRegs, ++
I) {
9486 assert(
I != RC->
end() &&
"Ran out of registers to allocate!");
9491 OpInfo.AssignedRegs =
RegsForValue(Regs, RegVT, ValueVT);
9492 return std::nullopt;
9497 const std::vector<SDValue> &AsmNodeOperands) {
9500 for (; OperandNo; --OperandNo) {
9502 unsigned OpFlag = AsmNodeOperands[CurOp]->getAsZExtVal();
9505 (
F.isRegDefKind() ||
F.isRegDefEarlyClobberKind() ||
F.isMemKind()) &&
9506 "Skipped past definitions?");
9507 CurOp +=
F.getNumOperandRegisters() + 1;
9518 explicit ExtraFlags(
const CallBase &Call) {
9520 if (
IA->hasSideEffects())
9522 if (
IA->isAlignStack())
9524 if (
Call.isConvergent())
9545 unsigned get()
const {
return Flags; }
9552 if (
auto *GA = dyn_cast<GlobalAddressSDNode>(
Op)) {
9553 auto Fn = dyn_cast_or_null<Function>(GA->getGlobal());
9568void SelectionDAGBuilder::visitInlineAsm(
const CallBase &Call,
9581 bool HasSideEffect =
IA->hasSideEffects();
9582 ExtraFlags ExtraInfo(Call);
9584 for (
auto &
T : TargetConstraints) {
9585 ConstraintOperands.
push_back(SDISelAsmOperandInfo(
T));
9586 SDISelAsmOperandInfo &OpInfo = ConstraintOperands.
back();
9588 if (OpInfo.CallOperandVal)
9589 OpInfo.CallOperand =
getValue(OpInfo.CallOperandVal);
9592 HasSideEffect = OpInfo.hasMemory(TLI);
9601 OpInfo.CallOperand && !isa<ConstantSDNode>(OpInfo.CallOperand))
9604 return emitInlineAsmError(Call,
"constraint '" +
Twine(
T.ConstraintCode) +
9605 "' expects an integer constant "
9608 ExtraInfo.update(
T);
9615 bool EmitEHLabels = isa<InvokeInst>(Call);
9617 assert(EHPadBB &&
"InvokeInst must have an EHPadBB");
9619 bool IsCallBr = isa<CallBrInst>(Call);
9621 if (IsCallBr || EmitEHLabels) {
9630 Chain = lowerStartEH(Chain, EHPadBB, BeginLabel);
9635 IA->collectAsmStrs(AsmStrs);
9638 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9646 if (OpInfo.hasMatchingInput()) {
9647 SDISelAsmOperandInfo &Input = ConstraintOperands[OpInfo.MatchingInput];
9678 if (OpInfo.isIndirect &&
isFunction(OpInfo.CallOperand) &&
9681 OpInfo.isIndirect =
false;
9688 !OpInfo.isIndirect) {
9689 assert((OpInfo.isMultipleAlternative ||
9691 "Can only indirectify direct input operands!");
9697 OpInfo.CallOperandVal =
nullptr;
9700 OpInfo.isIndirect =
true;
9706 std::vector<SDValue> AsmNodeOperands;
9707 AsmNodeOperands.push_back(
SDValue());
9714 const MDNode *SrcLoc =
Call.getMetadata(
"srcloc");
9724 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
9726 SDISelAsmOperandInfo &RefOpInfo =
9727 OpInfo.isMatchingInputConstraint()
9728 ? ConstraintOperands[OpInfo.getMatchedOperand()]
9730 const auto RegError =
9735 const char *
RegName =
TRI.getName(*RegError);
9736 emitInlineAsmError(Call,
"register '" +
Twine(
RegName) +
9737 "' allocated for constraint '" +
9738 Twine(OpInfo.ConstraintCode) +
9739 "' does not match required type");
9743 auto DetectWriteToReservedRegister = [&]() {
9746 for (
unsigned Reg : OpInfo.AssignedRegs.Regs) {
9748 TRI.isInlineAsmReadOnlyReg(MF, Reg)) {
9750 emitInlineAsmError(Call,
"write to reserved register '" +
9759 !OpInfo.isMatchingInputConstraint())) &&
9760 "Only address as input operand is allowed.");
9762 switch (OpInfo.Type) {
9768 "Failed to convert memory constraint code to constraint id.");
9772 OpFlags.setMemConstraint(ConstraintID);
9775 AsmNodeOperands.push_back(OpInfo.CallOperand);
9780 if (OpInfo.AssignedRegs.Regs.empty()) {
9782 Call,
"couldn't allocate output register for constraint '" +
9783 Twine(OpInfo.ConstraintCode) +
"'");
9787 if (DetectWriteToReservedRegister())
9792 OpInfo.AssignedRegs.AddInlineAsmOperands(
9801 SDValue InOperandVal = OpInfo.CallOperand;
9803 if (OpInfo.isMatchingInputConstraint()) {
9809 if (
Flag.isRegDefKind() ||
Flag.isRegDefEarlyClobberKind()) {
9810 if (OpInfo.isIndirect) {
9812 emitInlineAsmError(Call,
"inline asm not supported yet: "
9813 "don't know how to handle tied "
9814 "indirect register inputs");
9822 auto *
R = cast<RegisterSDNode>(AsmNodeOperands[CurOp+1]);
9824 MVT RegVT =
R->getSimpleValueType(0);
9828 :
TRI.getMinimalPhysRegClass(TiedReg);
9829 for (
unsigned i = 0, e =
Flag.getNumOperandRegisters(); i != e; ++i)
9836 MatchedRegs.getCopyToRegs(InOperandVal,
DAG, dl, Chain, &Glue, &Call);
9838 OpInfo.getMatchedOperand(), dl,
DAG,
9843 assert(
Flag.isMemKind() &&
"Unknown matching constraint!");
9845 "Unexpected number of operands");
9848 Flag.clearMemConstraint();
9849 Flag.setMatchingOp(OpInfo.getMatchedOperand());
9852 AsmNodeOperands.push_back(AsmNodeOperands[CurOp+1]);
9863 std::vector<SDValue> Ops;
9868 if (isa<ConstantSDNode>(InOperandVal)) {
9869 emitInlineAsmError(Call,
"value out of range for constraint '" +
9870 Twine(OpInfo.ConstraintCode) +
"'");
9874 emitInlineAsmError(Call,
9875 "invalid operand for inline asm constraint '" +
9876 Twine(OpInfo.ConstraintCode) +
"'");
9889 assert((OpInfo.isIndirect ||
9891 "Operand must be indirect to be a mem!");
9894 "Memory operands expect pointer values");
9899 "Failed to convert memory constraint code to constraint id.");
9903 ResOpType.setMemConstraint(ConstraintID);
9907 AsmNodeOperands.push_back(InOperandVal);
9915 "Failed to convert memory constraint code to constraint id.");
9921 auto *GA = cast<GlobalAddressSDNode>(InOperandVal);
9929 ResOpType.setMemConstraint(ConstraintID);
9931 AsmNodeOperands.push_back(
9934 AsmNodeOperands.push_back(AsmOp);
9940 "Unknown constraint type!");
9943 if (OpInfo.isIndirect) {
9945 Call,
"Don't know how to handle indirect register inputs yet "
9946 "for constraint '" +
9947 Twine(OpInfo.ConstraintCode) +
"'");
9952 if (OpInfo.AssignedRegs.Regs.empty()) {
9953 emitInlineAsmError(Call,
9954 "couldn't allocate input reg for constraint '" +
9955 Twine(OpInfo.ConstraintCode) +
"'");
9959 if (DetectWriteToReservedRegister())
9964 OpInfo.AssignedRegs.getCopyToRegs(InOperandVal,
DAG, dl, Chain, &Glue,
9968 0, dl,
DAG, AsmNodeOperands);
9974 if (!OpInfo.AssignedRegs.Regs.empty())
9984 if (Glue.
getNode()) AsmNodeOperands.push_back(Glue);
9988 DAG.
getVTList(MVT::Other, MVT::Glue), AsmNodeOperands);
9999 if (
StructType *StructResult = dyn_cast<StructType>(CallResultType))
10000 ResultTypes = StructResult->elements();
10001 else if (!CallResultType->
isVoidTy())
10002 ResultTypes =
ArrayRef(CallResultType);
10004 auto CurResultType = ResultTypes.
begin();
10005 auto handleRegAssign = [&](
SDValue V) {
10006 assert(CurResultType != ResultTypes.
end() &&
"Unexpected value");
10007 assert((*CurResultType)->isSized() &&
"Unexpected unsized type");
10020 if (ResultVT !=
V.getValueType() &&
10023 else if (ResultVT !=
V.getValueType() && ResultVT.
isInteger() &&
10024 V.getValueType().isInteger()) {
10030 assert(ResultVT ==
V.getValueType() &&
"Asm result value mismatch!");
10036 for (SDISelAsmOperandInfo &OpInfo : ConstraintOperands) {
10040 if (OpInfo.AssignedRegs.Regs.empty())
10043 switch (OpInfo.ConstraintType) {
10047 Chain, &Glue, &Call);
10059 assert(
false &&
"Unexpected unknown constraint");
10063 if (OpInfo.isIndirect) {
10064 const Value *
Ptr = OpInfo.CallOperandVal;
10065 assert(
Ptr &&
"Expected value CallOperandVal for indirect asm operand");
10071 assert(!
Call.getType()->isVoidTy() &&
"Bad inline asm!");
10074 handleRegAssign(V);
10076 handleRegAssign(Val);
10082 if (!ResultValues.
empty()) {
10083 assert(CurResultType == ResultTypes.
end() &&
10084 "Mismatch in number of ResultTypes");
10086 "Mismatch in number of output operands in asm result");
10094 if (!OutChains.
empty())
10097 if (EmitEHLabels) {
10098 Chain = lowerEndEH(Chain, cast<InvokeInst>(&Call), EHPadBB, BeginLabel);
10102 if (ResultValues.
empty() || HasSideEffect || !OutChains.
empty() || IsCallBr ||
10107void SelectionDAGBuilder::emitInlineAsmError(
const CallBase &Call,
10108 const Twine &Message) {
10117 if (ValueVTs.
empty())
10121 for (
unsigned i = 0, e = ValueVTs.
size(); i != e; ++i)
10127void SelectionDAGBuilder::visitVAStart(
const CallInst &
I) {
10134void SelectionDAGBuilder::visitVAArg(
const VAArgInst &
I) {
10140 DL.getABITypeAlign(
I.getType()).value());
10143 if (
I.getType()->isPointerTy())
10149void SelectionDAGBuilder::visitVAEnd(
const CallInst &
I) {
10156void SelectionDAGBuilder::visitVACopy(
const CallInst &
I) {
10177 if (!
Lo.isMinValue())
10181 unsigned Bits = std::max(
Hi.getActiveBits(),
10190 unsigned NumVals =
Op.getNode()->getNumValues();
10197 for (
unsigned I = 1;
I != NumVals; ++
I)
10211 unsigned ArgIdx,
unsigned NumArgs,
SDValue Callee,
Type *ReturnTy,
10214 Args.reserve(NumArgs);
10218 for (
unsigned ArgI = ArgIdx, ArgE = ArgIdx + NumArgs;
10219 ArgI != ArgE; ++ArgI) {
10220 const Value *V = Call->getOperand(ArgI);
10222 assert(!V->getType()->isEmptyTy() &&
"Empty type passed to intrinsic.");
10226 Entry.Ty = V->getType();
10227 Entry.setAttributes(Call, ArgI);
10228 Args.push_back(Entry);
10233 .
setCallee(Call->getCallingConv(), ReturnTy, Callee, std::move(Args),
10262 for (
unsigned I = StartIdx;
I < Call.arg_size();
I++) {
10277void SelectionDAGBuilder::visitStackmap(
const CallInst &CI) {
10311 assert(
ID.getValueType() == MVT::i64);
10342void SelectionDAGBuilder::visitPatchpoint(
const CallBase &CB,
10358 if (
auto* ConstCallee = dyn_cast<ConstantSDNode>(Callee))
10361 else if (
auto* SymbolicCallee = dyn_cast<GlobalAddressSDNode>(Callee))
10363 SDLoc(SymbolicCallee),
10364 SymbolicCallee->getValueType(0));
10374 "Not enough arguments provided to the patchpoint intrinsic");
10377 unsigned NumCallArgs = IsAnyRegCC ? 0 : NumArgs;
10393 "Expected a callseq node.");
10395 bool HasGlue =
Call->getGluedNode();
10425 unsigned NumCallRegArgs =
Call->getNumOperands() - (HasGlue ? 4 : 3);
10426 NumCallRegArgs = IsAnyRegCC ? NumArgs : NumCallRegArgs;
10435 for (
unsigned i = NumMetaOpers, e = NumMetaOpers + NumArgs; i !=
e; ++i)
10446 if (IsAnyRegCC && HasDef) {
10451 assert(ValueVTs.
size() == 1 &&
"Expected only one return value type.");
10475 if (IsAnyRegCC && HasDef) {
10487void SelectionDAGBuilder::visitVectorReduce(
const CallInst &
I,
10488 unsigned Intrinsic) {
10492 if (
I.arg_size() > 1)
10498 if (
auto *FPMO = dyn_cast<FPMathOperator>(&
I))
10501 switch (Intrinsic) {
10502 case Intrinsic::vector_reduce_fadd:
10510 case Intrinsic::vector_reduce_fmul:
10518 case Intrinsic::vector_reduce_add:
10521 case Intrinsic::vector_reduce_mul:
10524 case Intrinsic::vector_reduce_and:
10527 case Intrinsic::vector_reduce_or:
10530 case Intrinsic::vector_reduce_xor:
10533 case Intrinsic::vector_reduce_smax:
10536 case Intrinsic::vector_reduce_smin:
10539 case Intrinsic::vector_reduce_umax:
10542 case Intrinsic::vector_reduce_umin:
10545 case Intrinsic::vector_reduce_fmax:
10548 case Intrinsic::vector_reduce_fmin:
10551 case Intrinsic::vector_reduce_fmaximum:
10554 case Intrinsic::vector_reduce_fminimum:
10568 Attrs.push_back(Attribute::SExt);
10570 Attrs.push_back(Attribute::ZExt);
10572 Attrs.push_back(Attribute::InReg);
10582std::pair<SDValue, SDValue>
10596 RetTys.
swap(OldRetTys);
10597 Offsets.swap(OldOffsets);
10599 for (
size_t i = 0, e = OldRetTys.
size(); i != e; ++i) {
10600 EVT RetVT = OldRetTys[i];
10604 unsigned RegisterVTByteSZ = RegisterVT.
getSizeInBits() / 8;
10605 RetTys.
append(NumRegs, RegisterVT);
10606 for (
unsigned j = 0; j != NumRegs; ++j)
10619 int DemoteStackIdx = -100;
10630 DL.getAllocaAddrSpace());
10634 Entry.Node = DemoteStackSlot;
10635 Entry.Ty = StackSlotPtrType;
10636 Entry.IsSExt =
false;
10637 Entry.IsZExt =
false;
10638 Entry.IsInReg =
false;
10639 Entry.IsSRet =
true;
10640 Entry.IsNest =
false;
10641 Entry.IsByVal =
false;
10642 Entry.IsByRef =
false;
10643 Entry.IsReturned =
false;
10644 Entry.IsSwiftSelf =
false;
10645 Entry.IsSwiftAsync =
false;
10646 Entry.IsSwiftError =
false;
10647 Entry.IsCFGuardTarget =
false;
10648 Entry.Alignment = Alignment;
10660 for (
unsigned I = 0, E = RetTys.
size();
I != E; ++
I) {
10662 if (NeedsRegBlock) {
10663 Flags.setInConsecutiveRegs();
10664 if (
I == RetTys.
size() - 1)
10665 Flags.setInConsecutiveRegsLast();
10667 EVT VT = RetTys[
I];
10672 for (
unsigned i = 0; i != NumRegs; ++i) {
10674 MyFlags.
Flags = Flags;
10675 MyFlags.
VT = RegisterVT;
10676 MyFlags.
ArgVT = VT;
10681 cast<PointerType>(CLI.
RetTy)->getAddressSpace());
10689 CLI.
Ins.push_back(MyFlags);
10703 CLI.
Ins.push_back(MyFlags);
10711 for (
unsigned i = 0, e = Args.size(); i != e; ++i) {
10715 Type *FinalType = Args[i].Ty;
10716 if (Args[i].IsByVal)
10717 FinalType = Args[i].IndirectType;
10720 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
Value != NumValues;
10725 Args[i].Node.getResNo() +
Value);
10732 Flags.setOrigAlign(OriginalAlignment);
10734 if (Args[i].Ty->isPointerTy()) {
10735 Flags.setPointer();
10736 Flags.setPointerAddrSpace(
10737 cast<PointerType>(Args[i].Ty)->getAddressSpace());
10739 if (Args[i].IsZExt)
10741 if (Args[i].IsSExt)
10743 if (Args[i].IsInReg) {
10747 isa<StructType>(FinalType)) {
10750 Flags.setHvaStart();
10756 if (Args[i].IsSRet)
10758 if (Args[i].IsSwiftSelf)
10759 Flags.setSwiftSelf();
10760 if (Args[i].IsSwiftAsync)
10761 Flags.setSwiftAsync();
10762 if (Args[i].IsSwiftError)
10763 Flags.setSwiftError();
10764 if (Args[i].IsCFGuardTarget)
10765 Flags.setCFGuardTarget();
10766 if (Args[i].IsByVal)
10768 if (Args[i].IsByRef)
10770 if (Args[i].IsPreallocated) {
10771 Flags.setPreallocated();
10779 if (Args[i].IsInAlloca) {
10780 Flags.setInAlloca();
10789 if (Args[i].IsByVal || Args[i].IsInAlloca || Args[i].IsPreallocated) {
10790 unsigned FrameSize =
DL.getTypeAllocSize(Args[i].IndirectType);
10791 Flags.setByValSize(FrameSize);
10794 if (
auto MA = Args[i].Alignment)
10798 }
else if (
auto MA = Args[i].Alignment) {
10801 MemAlign = OriginalAlignment;
10803 Flags.setMemAlign(MemAlign);
10804 if (Args[i].IsNest)
10807 Flags.setInConsecutiveRegs();
10816 if (Args[i].IsSExt)
10818 else if (Args[i].IsZExt)
10823 if (Args[i].IsReturned && !
Op.getValueType().isVector() &&
10828 Args[i].Ty->getPointerAddressSpace())) &&
10829 RetTys.
size() == NumValues &&
"unexpected use of 'returned'");
10842 CLI.
RetZExt == Args[i].IsZExt))
10843 Flags.setReturned();
10849 for (
unsigned j = 0; j != NumParts; ++j) {
10856 j * Parts[j].getValueType().getStoreSize().getKnownMinValue());
10857 if (NumParts > 1 && j == 0)
10861 if (j == NumParts - 1)
10865 CLI.
Outs.push_back(MyFlags);
10866 CLI.
OutVals.push_back(Parts[j]);
10869 if (NeedsRegBlock &&
Value == NumValues - 1)
10870 CLI.
Outs[CLI.
Outs.size() - 1].Flags.setInConsecutiveRegsLast();
10882 "LowerCall didn't return a valid chain!");
10884 "LowerCall emitted a return value for a tail call!");
10886 "LowerCall didn't emit the correct number of values!");
10898 for (
unsigned i = 0, e = CLI.
Ins.size(); i != e; ++i) {
10899 assert(InVals[i].getNode() &&
"LowerCall emitted a null value!");
10900 assert(
EVT(CLI.
Ins[i].VT) == InVals[i].getValueType() &&
10901 "LowerCall emitted a value with the wrong type!");
10914 assert(PVTs.
size() == 1 &&
"Pointers should fit in one register");
10915 EVT PtrVT = PVTs[0];
10917 unsigned NumValues = RetTys.
size();
10918 ReturnValues.
resize(NumValues);
10924 Flags.setNoUnsignedWrap(
true);
10928 for (
unsigned i = 0; i < NumValues; ++i) {
10935 DemoteStackIdx, Offsets[i]),
10937 ReturnValues[i] = L;
10938 Chains[i] = L.getValue(1);
10945 std::optional<ISD::NodeType> AssertOp;
10950 unsigned CurReg = 0;
10951 for (
EVT VT : RetTys) {
10958 CLI.
DAG, CLI.
DL, &InVals[CurReg], NumRegs, RegisterVT, VT,
nullptr,
10966 if (ReturnValues.
empty())
10972 return std::make_pair(Res, CLI.
Chain);
10989 if (
N->getNumValues() == 1) {
10997 "Lowering returned the wrong number of results!");
11000 for (
unsigned I = 0, E =
N->getNumValues();
I != E; ++
I)
11013 cast<RegisterSDNode>(
Op.getOperand(1))->getReg() != Reg) &&
11014 "Copy from a reg to the same reg!");
11028 ExtendType = PreferredExtendIt->second;
11031 PendingExports.push_back(Chain);
11043 return A->use_empty();
11045 const BasicBlock &Entry =
A->getParent()->front();
11046 for (
const User *U :
A->users())
11047 if (cast<Instruction>(U)->
getParent() != &Entry || isa<SwitchInst>(U))
11055 std::pair<const AllocaInst *, const StoreInst *>>;
11067 enum StaticAllocaInfo {
Unknown, Clobbered, Elidable };
11069 unsigned NumArgs = FuncInfo->
Fn->
arg_size();
11070 StaticAllocas.
reserve(NumArgs * 2);
11072 auto GetInfoIfStaticAlloca = [&](
const Value *V) -> StaticAllocaInfo * {
11075 V = V->stripPointerCasts();
11076 const auto *AI = dyn_cast<AllocaInst>(V);
11077 if (!AI || !AI->isStaticAlloca() || !FuncInfo->
StaticAllocaMap.count(AI))
11080 return &Iter.first->second;
11090 const auto *SI = dyn_cast<StoreInst>(&
I);
11097 if (
I.isDebugOrPseudoInst())
11101 for (
const Use &U :
I.operands()) {
11102 if (StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(U))
11103 *
Info = StaticAllocaInfo::Clobbered;
11109 if (StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(SI->getValueOperand()))
11110 *
Info = StaticAllocaInfo::Clobbered;
11113 const Value *Dst = SI->getPointerOperand()->stripPointerCasts();
11114 StaticAllocaInfo *
Info = GetInfoIfStaticAlloca(Dst);
11117 const AllocaInst *AI = cast<AllocaInst>(Dst);
11120 if (*
Info != StaticAllocaInfo::Unknown)
11128 const Value *Val = SI->getValueOperand()->stripPointerCasts();
11129 const auto *Arg = dyn_cast<Argument>(Val);
11130 if (!Arg || Arg->hasPassPointeeByValueCopyAttr() ||
11131 Arg->getType()->isEmptyTy() ||
11132 DL.getTypeStoreSize(Arg->getType()) !=
11134 !
DL.typeSizeEqualsStoreSize(Arg->getType()) ||
11135 ArgCopyElisionCandidates.
count(Arg)) {
11136 *
Info = StaticAllocaInfo::Clobbered;
11140 LLVM_DEBUG(
dbgs() <<
"Found argument copy elision candidate: " << *AI
11144 *
Info = StaticAllocaInfo::Elidable;
11145 ArgCopyElisionCandidates.
insert({Arg, {AI, SI}});
11150 if (ArgCopyElisionCandidates.
size() == NumArgs)
11164 auto *LNode = dyn_cast<LoadSDNode>(ArgVals[0]);
11167 auto *FINode = dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode());
11174 auto ArgCopyIter = ArgCopyElisionCandidates.
find(&Arg);
11175 assert(ArgCopyIter != ArgCopyElisionCandidates.
end());
11176 const AllocaInst *AI = ArgCopyIter->second.first;
11177 int FixedIndex = FINode->getIndex();
11179 int OldIndex = AllocaIndex;
11183 dbgs() <<
" argument copy elision failed due to bad fixed stack "
11189 LLVM_DEBUG(
dbgs() <<
" argument copy elision failed: alignment of alloca "
11190 "greater than stack argument alignment ("
11191 <<
DebugStr(RequiredAlignment) <<
" vs "
11199 dbgs() <<
"Eliding argument copy from " << Arg <<
" to " << *AI <<
'\n'
11200 <<
" Replacing frame index " << OldIndex <<
" with " << FixedIndex
11206 AllocaIndex = FixedIndex;
11207 ArgCopyElisionFrameIndexMap.
insert({OldIndex, FixedIndex});
11208 for (
SDValue ArgVal : ArgVals)
11212 const StoreInst *SI = ArgCopyIter->second.second;
11213 ElidedArgCopyInstrs.
insert(SI);
11225void SelectionDAGISel::LowerArguments(
const Function &
F) {
11232 if (
F.hasFnAttribute(Attribute::Naked))
11250 Ins.push_back(RetArg);
11258 ArgCopyElisionCandidates);
11262 unsigned ArgNo = Arg.getArgNo();
11265 bool isArgValueUsed = !Arg.use_empty();
11266 unsigned PartBase = 0;
11267 Type *FinalType = Arg.getType();
11268 if (Arg.hasAttribute(Attribute::ByVal))
11269 FinalType = Arg.getParamByValType();
11271 FinalType,
F.getCallingConv(),
F.isVarArg(),
DL);
11272 for (
unsigned Value = 0, NumValues = ValueVTs.
size();
11279 if (Arg.getType()->isPointerTy()) {
11280 Flags.setPointer();
11281 Flags.setPointerAddrSpace(
11282 cast<PointerType>(Arg.getType())->getAddressSpace());
11284 if (Arg.hasAttribute(Attribute::ZExt))
11286 if (Arg.hasAttribute(Attribute::SExt))
11288 if (Arg.hasAttribute(Attribute::InReg)) {
11292 isa<StructType>(Arg.getType())) {
11295 Flags.setHvaStart();
11301 if (Arg.hasAttribute(Attribute::StructRet))
11303 if (Arg.hasAttribute(Attribute::SwiftSelf))
11304 Flags.setSwiftSelf();
11305 if (Arg.hasAttribute(Attribute::SwiftAsync))
11306 Flags.setSwiftAsync();
11307 if (Arg.hasAttribute(Attribute::SwiftError))
11308 Flags.setSwiftError();
11309 if (Arg.hasAttribute(Attribute::ByVal))
11311 if (Arg.hasAttribute(Attribute::ByRef))
11313 if (Arg.hasAttribute(Attribute::InAlloca)) {
11314 Flags.setInAlloca();
11322 if (Arg.hasAttribute(Attribute::Preallocated)) {
11323 Flags.setPreallocated();
11335 const Align OriginalAlignment(
11337 Flags.setOrigAlign(OriginalAlignment);
11340 Type *ArgMemTy =
nullptr;
11341 if (
Flags.isByVal() ||
Flags.isInAlloca() ||
Flags.isPreallocated() ||
11344 ArgMemTy = Arg.getPointeeInMemoryValueType();
11346 uint64_t MemSize =
DL.getTypeAllocSize(ArgMemTy);
11351 if (
auto ParamAlign = Arg.getParamStackAlign())
11352 MemAlign = *ParamAlign;
11353 else if ((ParamAlign = Arg.getParamAlign()))
11354 MemAlign = *ParamAlign;
11357 if (
Flags.isByRef())
11358 Flags.setByRefSize(MemSize);
11360 Flags.setByValSize(MemSize);
11361 }
else if (
auto ParamAlign = Arg.getParamStackAlign()) {
11362 MemAlign = *ParamAlign;
11364 MemAlign = OriginalAlignment;
11366 Flags.setMemAlign(MemAlign);
11368 if (Arg.hasAttribute(Attribute::Nest))
11371 Flags.setInConsecutiveRegs();
11372 if (ArgCopyElisionCandidates.
count(&Arg))
11373 Flags.setCopyElisionCandidate();
11374 if (Arg.hasAttribute(Attribute::Returned))
11375 Flags.setReturned();
11381 for (
unsigned i = 0; i != NumRegs; ++i) {
11386 Flags, RegisterVT, VT, isArgValueUsed, ArgNo,
11388 if (NumRegs > 1 && i == 0)
11389 MyFlags.Flags.setSplit();
11392 MyFlags.Flags.setOrigAlign(
Align(1));
11393 if (i == NumRegs - 1)
11394 MyFlags.Flags.setSplitEnd();
11396 Ins.push_back(MyFlags);
11398 if (NeedsRegBlock &&
Value == NumValues - 1)
11399 Ins[
Ins.size() - 1].Flags.setInConsecutiveRegsLast();
11407 DAG.
getRoot(),
F.getCallingConv(),
F.isVarArg(), Ins, dl, DAG, InVals);
11411 "LowerFormalArguments didn't return a valid chain!");
11413 "LowerFormalArguments didn't emit the correct number of values!");
11415 for (
unsigned i = 0, e =
Ins.size(); i != e; ++i) {
11416 assert(InVals[i].getNode() &&
11417 "LowerFormalArguments emitted a null value!");
11418 assert(EVT(Ins[i].VT) == InVals[i].getValueType() &&
11419 "LowerFormalArguments emitted a value with the wrong type!");
11436 MVT VT = ValueVTs[0].getSimpleVT();
11438 std::optional<ISD::NodeType> AssertOp;
11441 F.getCallingConv(), AssertOp);
11447 FuncInfo->DemoteRegister = SRetReg;
11449 SDB->DAG.getCopyToReg(NewRoot,
SDB->getCurSDLoc(), SRetReg, ArgValue);
11462 unsigned NumValues = ValueVTs.
size();
11463 if (NumValues == 0)
11466 bool ArgHasUses = !Arg.use_empty();
11470 if (Ins[i].
Flags.isCopyElisionCandidate()) {
11471 unsigned NumParts = 0;
11472 for (
EVT VT : ValueVTs)
11474 F.getCallingConv(), VT);
11478 ArrayRef(&InVals[i], NumParts), ArgHasUses);
11483 bool isSwiftErrorArg =
11485 Arg.hasAttribute(Attribute::SwiftError);
11486 if (!ArgHasUses && !isSwiftErrorArg) {
11487 SDB->setUnusedArgValue(&Arg, InVals[i]);
11491 dyn_cast<FrameIndexSDNode>(InVals[i].getNode()))
11492 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11495 for (
unsigned Val = 0; Val != NumValues; ++Val) {
11496 EVT VT = ValueVTs[Val];
11498 F.getCallingConv(), VT);
11505 if (ArgHasUses || isSwiftErrorArg) {
11506 std::optional<ISD::NodeType> AssertOp;
11507 if (Arg.hasAttribute(Attribute::SExt))
11509 else if (Arg.hasAttribute(Attribute::ZExt))
11513 PartVT, VT,
nullptr, NewRoot,
11514 F.getCallingConv(), AssertOp));
11521 if (ArgValues.
empty())
11526 dyn_cast<FrameIndexSDNode>(ArgValues[0].getNode()))
11527 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11530 SDB->getCurSDLoc());
11532 SDB->setValue(&Arg, Res);
11545 dyn_cast<FrameIndexSDNode>(LNode->getBasePtr().getNode()))
11546 FuncInfo->setArgumentFrameIndex(&Arg, FI->getIndex());
11555 unsigned Reg = cast<RegisterSDNode>(Res.
getOperand(1))->getReg();
11567 unsigned Reg = cast<RegisterSDNode>(Res.
getOperand(1))->getReg();
11574 FuncInfo->InitializeRegForValue(&Arg);
11575 SDB->CopyToExportRegsIfNeeded(&Arg);
11579 if (!Chains.
empty()) {
11586 assert(i == InVals.
size() &&
"Argument register count mismatch!");
11590 if (!ArgCopyElisionFrameIndexMap.
empty()) {
11593 auto I = ArgCopyElisionFrameIndexMap.
find(
VI.getStackSlot());
11594 if (
I != ArgCopyElisionFrameIndexMap.
end())
11595 VI.updateStackSlot(
I->second);
11610SelectionDAGBuilder::HandlePHINodesInSuccessorBlocks(
const BasicBlock *LLVMBB) {
11618 if (!isa<PHINode>(SuccBB->begin()))
continue;
11623 if (!SuccsHandled.
insert(SuccMBB).second)
11631 for (
const PHINode &PN : SuccBB->phis()) {
11633 if (PN.use_empty())
11637 if (PN.getType()->isEmptyTy())
11641 const Value *PHIOp = PN.getIncomingValueForBlock(LLVMBB);
11643 if (
const auto *
C = dyn_cast<Constant>(PHIOp)) {
11650 if (
auto *CI = dyn_cast<ConstantInt>(
C))
11662 assert(isa<AllocaInst>(PHIOp) &&
11664 "Didn't codegen value into a register!??");
11674 for (
EVT VT : ValueVTs) {
11676 for (
unsigned i = 0; i != NumRegisters; ++i)
11678 std::make_pair(&*
MBBI++, Reg + i));
11679 Reg += NumRegisters;
11699void SelectionDAGBuilder::updateDAGForMaybeTailCall(
SDValue MaybeTC) {
11701 if (MaybeTC.
getNode() !=
nullptr)
11716 unsigned Size =
W.LastCluster -
W.FirstCluster + 1;
11720 if (
Size == 2 &&
W.MBB == SwitchMBB) {
11733 const APInt &SmallValue =
Small.Low->getValue();
11734 const APInt &BigValue =
Big.Low->getValue();
11737 APInt CommonBit = BigValue ^ SmallValue;
11752 addSuccessorWithProb(SwitchMBB,
Small.MBB,
Small.Prob +
Big.Prob);
11754 addSuccessorWithProb(
11755 SwitchMBB, DefaultMBB,
11759 addSuccessorWithProb(SwitchMBB, DefaultMBB);
11782 return a.Prob != b.Prob ?
11784 a.Low->getValue().slt(b.Low->getValue());
11791 if (
I->Prob >
W.LastCluster->Prob)
11793 if (
I->Kind ==
CC_Range &&
I->MBB == NextMBB) {
11804 UnhandledProbs +=
I->Prob;
11808 bool FallthroughUnreachable =
false;
11810 if (
I ==
W.LastCluster) {
11812 Fallthrough = DefaultMBB;
11813 FallthroughUnreachable = isa<UnreachableInst>(
11817 CurMF->
insert(BBI, Fallthrough);
11821 UnhandledProbs -=
I->Prob;
11831 CurMF->
insert(BBI, JumpMBB);
11833 auto JumpProb =
I->Prob;
11834 auto FallthroughProb = UnhandledProbs;
11842 if (*SI == DefaultMBB) {
11843 JumpProb += DefaultProb / 2;
11844 FallthroughProb -= DefaultProb / 2;
11862 if (FallthroughUnreachable) {
11864 bool HasBranchTargetEnforcement =
false;
11866 HasBranchTargetEnforcement =
11870 HasBranchTargetEnforcement =
11872 "branch-target-enforcement");
11874 if (!HasBranchTargetEnforcement)
11879 addSuccessorWithProb(CurMBB, Fallthrough, FallthroughProb);
11880 addSuccessorWithProb(CurMBB, JumpMBB, JumpProb);
11886 JT->Default = Fallthrough;
11889 if (CurMBB == SwitchMBB) {
11912 BTB->
Prob += DefaultProb / 2;
11916 if (FallthroughUnreachable)
11920 if (CurMBB == SwitchMBB) {
11929 if (
I->Low ==
I->High) {
11944 if (FallthroughUnreachable)
11948 CaseBlock CB(
CC, LHS, RHS, MHS,
I->MBB, Fallthrough, CurMBB,
11951 if (CurMBB == SwitchMBB)
11954 SL->SwitchCases.push_back(CB);
11959 CurMBB = Fallthrough;
11963void SelectionDAGBuilder::splitWorkItem(
SwitchWorkList &WorkList,
11967 assert(
W.FirstCluster->Low->getValue().slt(
W.LastCluster->Low->getValue()) &&
11968 "Clusters not sorted?");
11969 assert(
W.LastCluster -
W.FirstCluster + 1 >= 2 &&
"Too small to split!");
11971 auto [LastLeft, FirstRight, LeftProb, RightProb] =
11972 SL->computeSplitWorkItemInfo(W);
11977 assert(PivotCluster >
W.FirstCluster);
11978 assert(PivotCluster <=
W.LastCluster);
11993 if (FirstLeft == LastLeft && FirstLeft->Kind ==
CC_Range &&
11994 FirstLeft->Low ==
W.GE &&
11995 (FirstLeft->High->getValue() + 1LL) == Pivot->
getValue()) {
11996 LeftMBB = FirstLeft->MBB;
12001 {LeftMBB, FirstLeft, LastLeft,
W.GE, Pivot,
W.DefaultProb / 2});
12010 if (FirstRight == LastRight && FirstRight->Kind ==
CC_Range &&
12011 W.LT && (FirstRight->High->getValue() + 1ULL) ==
W.LT->getValue()) {
12012 RightMBB = FirstRight->MBB;
12017 {RightMBB, FirstRight, LastRight, Pivot,
W.LT,
W.DefaultProb / 2});
12026 if (
W.MBB == SwitchMBB)
12029 SL->SwitchCases.push_back(CB);
12062 unsigned PeeledCaseIndex = 0;
12063 bool SwitchPeeled =
false;
12066 if (
CC.Prob < TopCaseProb)
12068 TopCaseProb =
CC.Prob;
12069 PeeledCaseIndex =
Index;
12070 SwitchPeeled =
true;
12075 LLVM_DEBUG(
dbgs() <<
"Peeled one top case in switch stmt, prob: "
12076 << TopCaseProb <<
"\n");
12086 auto PeeledCaseIt = Clusters.begin() + PeeledCaseIndex;
12088 nullptr,
nullptr, TopCaseProb.
getCompl()};
12089 lowerWorkItem(W,
SI.getCondition(), SwitchMBB, PeeledSwitchMBB);
12091 Clusters.erase(PeeledCaseIt);
12094 dbgs() <<
"Scale the probablity for one cluster, before scaling: "
12095 <<
CC.Prob <<
"\n");
12099 PeeledCaseProb = TopCaseProb;
12100 return PeeledSwitchMBB;
12103void SelectionDAGBuilder::visitSwitch(
const SwitchInst &SI) {
12107 Clusters.reserve(
SI.getNumCases());
12108 for (
auto I :
SI.cases()) {
12127 peelDominantCaseCluster(SI, Clusters, PeeledCaseProb);
12131 if (Clusters.empty()) {
12132 assert(PeeledSwitchMBB == SwitchMBB);
12134 if (DefaultMBB != NextBlock(SwitchMBB)) {
12143 SL->findBitTestClusters(Clusters, &SI);
12146 dbgs() <<
"Case clusters: ";
12153 C.Low->getValue().print(
dbgs(),
true);
12154 if (
C.Low !=
C.High) {
12156 C.High->getValue().print(
dbgs(),
true);
12163 assert(!Clusters.empty());
12167 auto DefaultProb = getEdgeProbability(PeeledSwitchMBB, DefaultMBB);
12174 {PeeledSwitchMBB,
First,
Last,
nullptr,
nullptr, DefaultProb});
12176 while (!WorkList.
empty()) {
12178 unsigned NumClusters =
W.LastCluster -
W.FirstCluster + 1;
12183 splitWorkItem(WorkList, W,
SI.getCondition(), SwitchMBB);
12187 lowerWorkItem(W,
SI.getCondition(), SwitchMBB, DefaultMBB);
12191void SelectionDAGBuilder::visitStepVector(
const CallInst &
I) {
12198void SelectionDAGBuilder::visitVectorReverse(
const CallInst &
I) {
12204 assert(VT ==
V.getValueType() &&
"Malformed vector.reverse!");
12215 for (
unsigned i = 0; i != NumElts; ++i)
12216 Mask.push_back(NumElts - 1 - i);
12221void SelectionDAGBuilder::visitVectorDeinterleave(
const CallInst &
I) {
12252void SelectionDAGBuilder::visitVectorInterleave(
const CallInst &
I) {
12277void SelectionDAGBuilder::visitFreeze(
const FreezeInst &
I) {
12281 unsigned NumValues = ValueVTs.
size();
12282 if (NumValues == 0)
return;
12287 for (
unsigned i = 0; i != NumValues; ++i)
12295void SelectionDAGBuilder::visitVectorSplice(
const CallInst &
I) {
12302 int64_t
Imm = cast<ConstantInt>(
I.getOperand(2))->getSExtValue();
12317 for (
unsigned i = 0; i < NumElts; ++i)
12346 assert(
MI->getOpcode() == TargetOpcode::COPY &&
12347 "start of copy chain MUST be COPY");
12348 Reg =
MI->getOperand(1).getReg();
12349 MI =
MRI.def_begin(Reg)->getParent();
12351 if (
MI->getOpcode() == TargetOpcode::COPY) {
12352 assert(Reg.isVirtual() &&
"expected COPY of virtual register");
12353 Reg =
MI->getOperand(1).getReg();
12354 assert(Reg.isPhysical() &&
"expected COPY of physical register");
12355 MI =
MRI.def_begin(Reg)->getParent();
12358 assert(
MI->getOpcode() == TargetOpcode::INLINEASM_BR &&
12359 "end of copy chain MUST be INLINEASM_BR");
12367void SelectionDAGBuilder::visitCallBrLandingPad(
const CallInst &
I) {
12371 cast<CallBrInst>(
I.getParent()->getUniquePredecessor()->getTerminator());
12383 for (
auto &
T : TargetConstraints) {
12384 SDISelAsmOperandInfo OpInfo(
T);
12392 switch (OpInfo.ConstraintType) {
12400 for (
size_t i = 0, e = OpInfo.AssignedRegs.Regs.size(); i != e; ++i) {
12405 OpInfo.AssignedRegs.Regs[i] = OriginalDef;
12408 SDValue V = OpInfo.AssignedRegs.getCopyFromRegs(
12411 ResultVTs.
push_back(OpInfo.ConstraintVT);
12420 ResultVTs.
push_back(OpInfo.ConstraintVT);
unsigned const MachineRegisterInfo * MRI
static unsigned getIntrinsicID(const SDNode *N)
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
MachineBasicBlock MachineBasicBlock::iterator MBBI
This file declares a class to represent arbitrary precision floating point values and provide a varie...
This file implements a class to represent arbitrary precision integral constant values and operations...
Function Alias Analysis Results
Atomic ordering constants.
This file contains the simple types necessary to represent the attributes associated with functions a...
static const Function * getParent(const Value *V)
This file implements the BitVector class.
BlockVerifier::State From
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
static GCMetadataPrinterRegistry::Add< ErlangGCPrinter > X("erlang", "erlang-compatible garbage collector")
static AttributeList getReturnAttrs(FastISel::CallLoweringInfo &CLI)
Returns an AttributeList representing the attributes applied to the return value of the given call.
const HexagonInstrInfo * TII
This file provides various utilities for inspecting and working with the control flow graph in LLVM I...
static void getRegistersForValue(MachineFunction &MF, MachineIRBuilder &MIRBuilder, GISelAsmOperandInfo &OpInfo, GISelAsmOperandInfo &RefOpInfo)
Assign virtual/physical registers for the specified register operand.
This file defines an InstructionCost class that is used when calculating the cost of an instruction,...
unsigned const TargetRegisterInfo * TRI
static const Function * getCalledFunction(const Value *V, bool &IsNoBuiltin)
This file provides utility analysis objects describing memory locations.
This file provides utility for Memory Model Relaxation Annotations (MMRAs).
static unsigned getReg(const MCDisassembler *D, unsigned RC, unsigned RegNo)
Module.h This file contains the declarations for the Module class.
static GCMetadataPrinterRegistry::Add< OcamlGCMetadataPrinter > Y("ocaml", "ocaml 3.10-compatible collector")
const SmallVectorImpl< MachineOperand > MachineBasicBlock * TBB
const SmallVectorImpl< MachineOperand > & Cond
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
static bool hasOnlySelectUsers(const Value *Cond)
static SDValue getLoadStackGuard(SelectionDAG &DAG, const SDLoc &DL, SDValue &Chain)
Create a LOAD_STACK_GUARD node, and let it carry the target specific global variable if there exists ...
static void addStackMapLiveVars(const CallBase &Call, unsigned StartIdx, const SDLoc &DL, SmallVectorImpl< SDValue > &Ops, SelectionDAGBuilder &Builder)
Add a stack map intrinsic call's live variable operands to a stackmap or patchpoint target node's ope...
static const unsigned MaxParallelChains
static void getUnderlyingArgRegs(SmallVectorImpl< std::pair< unsigned, TypeSize > > &Regs, const SDValue &N)
static SDValue expandPow(const SDLoc &dl, SDValue LHS, SDValue RHS, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
visitPow - Lower a pow intrinsic.
static bool getUniformBase(const Value *Ptr, SDValue &Base, SDValue &Index, ISD::MemIndexType &IndexType, SDValue &Scale, SelectionDAGBuilder *SDB, const BasicBlock *CurBB, uint64_t ElemSize)
static const CallBase * FindPreallocatedCall(const Value *PreallocatedSetup)
Given a @llvm.call.preallocated.setup, return the corresponding preallocated call.
static cl::opt< unsigned > SwitchPeelThreshold("switch-peel-threshold", cl::Hidden, cl::init(66), cl::desc("Set the case probability threshold for peeling the case from a " "switch statement. A value greater than 100 will void this " "optimization"))
static cl::opt< bool > InsertAssertAlign("insert-assert-align", cl::init(true), cl::desc("Insert the experimental `assertalign` node."), cl::ReallyHidden)
static unsigned getISDForVPIntrinsic(const VPIntrinsic &VPIntrin)
static bool handleDanglingVariadicDebugInfo(SelectionDAG &DAG, DILocalVariable *Variable, DebugLoc DL, unsigned Order, SmallVectorImpl< Value * > &Values, DIExpression *Expression)
static unsigned findMatchingInlineAsmOperand(unsigned OperandNo, const std::vector< SDValue > &AsmNodeOperands)
static void patchMatchingInput(const SDISelAsmOperandInfo &OpInfo, SDISelAsmOperandInfo &MatchingOpInfo, SelectionDAG &DAG)
Make sure that the output operand OpInfo and its corresponding input operand MatchingOpInfo have comp...
static void findUnwindDestinations(FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability > > &UnwindDests)
When an invoke or a cleanupret unwinds to the next EH pad, there are many places it could ultimately ...
static unsigned FixedPointIntrinsicToOpcode(unsigned Intrinsic)
static BranchProbability scaleCaseProbality(BranchProbability CaseProb, BranchProbability PeeledCaseProb)
static SDValue expandExp2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandExp2 - Lower an exp2 intrinsic.
static SDValue expandDivFix(unsigned Opcode, const SDLoc &DL, SDValue LHS, SDValue RHS, SDValue Scale, SelectionDAG &DAG, const TargetLowering &TLI)
static SDValue getF32Constant(SelectionDAG &DAG, unsigned Flt, const SDLoc &dl)
getF32Constant - Get 32-bit floating point constant.
static SDValue widenVectorToPartType(SelectionDAG &DAG, SDValue Val, const SDLoc &DL, EVT PartVT)
static SDValue expandLog10(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog10 - Lower a log10 intrinsic.
static void getCopyToPartsVector(SelectionDAG &DAG, const SDLoc &dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, std::optional< CallingConv::ID > CallConv)
getCopyToPartsVector - Create a series of nodes that contain the specified value split into legal par...
static void getCopyToParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, const Value *V, std::optional< CallingConv::ID > CallConv=std::nullopt, ISD::NodeType ExtendKind=ISD::ANY_EXTEND)
getCopyToParts - Create a series of nodes that contain the specified value split into legal parts.
static SDValue getMemCmpLoad(const Value *PtrVal, MVT LoadVT, SelectionDAGBuilder &Builder)
static SDValue expandLog2(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog2 - Lower a log2 intrinsic.
static SDValue getAddressForMemoryInput(SDValue Chain, const SDLoc &Location, SDISelAsmOperandInfo &OpInfo, SelectionDAG &DAG)
Get a direct memory input to behave well as an indirect operand.
static bool isOnlyUsedInEntryBlock(const Argument *A, bool FastISel)
isOnlyUsedInEntryBlock - If the specified argument is only used in the entry block,...
static void diagnosePossiblyInvalidConstraint(LLVMContext &Ctx, const Value *V, const Twine &ErrMsg)
static bool collectInstructionDeps(SmallMapVector< const Instruction *, bool, 8 > *Deps, const Value *V, SmallMapVector< const Instruction *, bool, 8 > *Necessary=nullptr, unsigned Depth=0)
static void findArgumentCopyElisionCandidates(const DataLayout &DL, FunctionLoweringInfo *FuncInfo, ArgCopyElisionMapTy &ArgCopyElisionCandidates)
Scan the entry block of the function in FuncInfo for arguments that look like copies into a local all...
static bool isFunction(SDValue Op)
static SDValue GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI, const SDLoc &dl)
GetExponent - Get the exponent:
static Register FollowCopyChain(MachineRegisterInfo &MRI, Register Reg)
static SDValue ExpandPowI(const SDLoc &DL, SDValue LHS, SDValue RHS, SelectionDAG &DAG)
ExpandPowI - Expand a llvm.powi intrinsic.
static void findWasmUnwindDestinations(FunctionLoweringInfo &FuncInfo, const BasicBlock *EHPadBB, BranchProbability Prob, SmallVectorImpl< std::pair< MachineBasicBlock *, BranchProbability > > &UnwindDests)
static SDValue expandLog(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandLog - Lower a log intrinsic.
static SDValue getCopyFromParts(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, SDValue InChain, std::optional< CallingConv::ID > CC=std::nullopt, std::optional< ISD::NodeType > AssertOp=std::nullopt)
getCopyFromParts - Create a value that contains the specified legal parts combined into the value the...
static SDValue getLimitedPrecisionExp2(SDValue t0, const SDLoc &dl, SelectionDAG &DAG)
static SDValue GetSignificand(SelectionDAG &DAG, SDValue Op, const SDLoc &dl)
GetSignificand - Get the significand and build it into a floating-point number with exponent of 1:
static SDValue expandExp(const SDLoc &dl, SDValue Op, SelectionDAG &DAG, const TargetLowering &TLI, SDNodeFlags Flags)
expandExp - Lower an exp intrinsic.
static const MDNode * getRangeMetadata(const Instruction &I)
static cl::opt< unsigned, true > LimitFPPrecision("limit-float-precision", cl::desc("Generate low-precision inline sequences " "for some float libcalls"), cl::location(LimitFloatPrecision), cl::Hidden, cl::init(0))
static void tryToElideArgumentCopy(FunctionLoweringInfo &FuncInfo, SmallVectorImpl< SDValue > &Chains, DenseMap< int, int > &ArgCopyElisionFrameIndexMap, SmallPtrSetImpl< const Instruction * > &ElidedArgCopyInstrs, ArgCopyElisionMapTy &ArgCopyElisionCandidates, const Argument &Arg, ArrayRef< SDValue > ArgVals, bool &ArgHasUses)
Try to elide argument copies from memory into a local alloca.
static unsigned LimitFloatPrecision
LimitFloatPrecision - Generate low-precision inline sequences for some float libcalls (6,...
static SDValue getCopyFromPartsVector(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, const Value *V, SDValue InChain, std::optional< CallingConv::ID > CC)
getCopyFromPartsVector - Create a value that contains the specified legal parts combined into the val...
static bool InBlock(const Value *V, const BasicBlock *BB)
This file defines the SmallPtrSet class.
This file defines the SmallSet class.
static SymbolRef::Type getType(const Symbol *Sym)
support::ulittle16_t & Lo
support::ulittle16_t & Hi
bool pointsToConstantMemory(const MemoryLocation &Loc, bool OrLocal=false)
Checks whether the given location points to constant memory, or if OrLocal is true whether it points ...
Class for arbitrary precision integers.
APInt sextOrTrunc(unsigned width) const
Sign extend or truncate to width.
bool isNonNegative() const
Determine if this APInt Value is non-negative (>= 0)
bool isPowerOf2() const
Check if this APInt's value is a power of two greater than zero.
an instruction to allocate memory on the stack
Align getAlign() const
Return the alignment of the memory that is being allocated by the instruction.
Type * getAllocatedType() const
Return the type that is being allocated by the instruction.
This class represents an incoming formal argument to a Function.
bool hasAttribute(Attribute::AttrKind Kind) const
Check if an argument has a given attribute.
unsigned getArgNo() const
Return the index of this formal argument in its containing function.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
size_t size() const
size - Get the array size.
bool empty() const
empty - Check if the array is empty.
A cache of @llvm.assume calls within a function.
An instruction that atomically checks whether a specified value is in a memory location,...
This class represents the atomic memcpy intrinsic i.e.
an instruction that atomically reads a memory location, combines it with another value,...
@ Min
*p = old <signed v ? old : v
@ UIncWrap
Increment one up to a maximum value.
@ Max
*p = old >signed v ? old : v
@ UMin
*p = old <unsigned v ? old : v
@ FMin
*p = minnum(old, v) minnum matches the behavior of llvm.minnum.
@ UMax
*p = old >unsigned v ? old : v
@ FMax
*p = maxnum(old, v) maxnum matches the behavior of llvm.maxnum.
@ UDecWrap
Decrement one until a minimum value or zero.
static AttributeList get(LLVMContext &C, ArrayRef< std::pair< unsigned, Attribute > > Attrs)
Create an AttributeList with the specified parameters in it.
AttributeSet getRetAttrs() const
The attributes for the ret value are returned.
bool hasFnAttr(Attribute::AttrKind Kind) const
Return true if the attribute exists for the function.
bool getValueAsBool() const
Return the attribute's value as a boolean.
LLVM Basic Block Representation.
const Instruction * getFirstNonPHI() const
Returns a pointer to the first instruction in this block that is not a PHINode instruction.
bool isEntryBlock() const
Return true if this is the entry block of the containing function.
const Function * getParent() const
Return the enclosing method, or null if none.
const Instruction * getFirstNonPHIOrDbg(bool SkipPseudoOp=true) const
Returns a pointer to the first instruction in this block that is not a PHINode or a debug intrinsic,...
const Instruction * getTerminator() const LLVM_READONLY
Returns the terminator instruction if the block is well formed or null if the block is not well forme...
const Instruction & back() const
This class represents a no-op cast from one type to another.
bool test(unsigned Idx) const
void resize(unsigned N, bool t=false)
resize - Grow or shrink the bitvector.
size_type size() const
size - Returns the number of bits in this bitvector.
The address of a basic block.
Conditional or Unconditional Branch instruction.
Analysis providing branch probability information.
BranchProbability getEdgeProbability(const BasicBlock *Src, unsigned IndexInSuccessors) const
Get an edge's probability, relative to other out-edges of the Src.
bool isEdgeHot(const BasicBlock *Src, const BasicBlock *Dst) const
Test if an edge is hot relative to other out-edges of the Src.
static uint32_t getDenominator()
static BranchProbability getOne()
uint32_t getNumerator() const
uint64_t scale(uint64_t Num) const
Scale a large integer.
BranchProbability getCompl() const
static BranchProbability getZero()
static void normalizeProbabilities(ProbabilityIter Begin, ProbabilityIter End)
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
std::optional< OperandBundleUse > getOperandBundle(StringRef Name) const
Return an operand bundle by name, if present.
CallingConv::ID getCallingConv() const
User::op_iterator arg_begin()
Return the iterator pointing to the beginning of the argument list.
bool isIndirectCall() const
Return true if the callsite is an indirect call.
unsigned countOperandBundlesOfType(StringRef Name) const
Return the number of operand bundles with the tag Name attached to this instruction.
Value * getCalledOperand() const
Value * getArgOperand(unsigned i) const
User::op_iterator arg_end()
Return the iterator pointing to the end of the argument list.
bool isConvergent() const
Determine if the invoke is convergent.
FunctionType * getFunctionType() const
Intrinsic::ID getIntrinsicID() const
Returns the intrinsic ID of the intrinsic called or Intrinsic::not_intrinsic if the called function i...
unsigned arg_size() const
AttributeList getAttributes() const
Return the parameter attributes for this call.
CallBr instruction, tracking function calls that may not return control but instead transfer it to a ...
This class represents a function call, abstracting a target machine's calling convention.
This class is the base class for the comparison instructions.
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
ConstantDataSequential - A vector or array constant whose element type is a simple 1/2/4/8-byte integ...
A constant value that is initialized with an expression using other constant values.
static Constant * getBitCast(Constant *C, Type *Ty, bool OnlyIfReduced=false)
ConstantFP - Floating Point Values [float, double].
This is the shared class of boolean and integer constants.
static ConstantInt * getTrue(LLVMContext &Context)
bool isZero() const
This is just a convenience method to make client code smaller for a common code.
static ConstantInt * getFalse(LLVMContext &Context)
uint64_t getZExtValue() const
Return the constant as a 64-bit unsigned integer value after it has been zero extended as appropriate...
const APInt & getValue() const
Return the constant as an APInt value reference.
This class represents a range of values.
APInt getUnsignedMin() const
Return the smallest unsigned value contained in the ConstantRange.
bool isFullSet() const
Return true if this set contains all of the elements possible for this data-type.
bool isEmptySet() const
Return true if this set contains no members.
bool isUpperWrapped() const
Return true if the exclusive upper bound wraps around the unsigned domain.
APInt getUnsignedMax() const
Return the largest unsigned value contained in the ConstantRange.
uint64_t getZExtValue() const
Constant Vector Declarations.
This is an important base class in LLVM.
This is the common base class for constrained floating point intrinsics.
std::optional< fp::ExceptionBehavior > getExceptionBehavior() const
unsigned getNonMetadataArgCount() const
bool isEntryValue() const
Check if the expression consists of exactly one entry value operand.
static bool fragmentsOverlap(const FragmentInfo &A, const FragmentInfo &B)
Check if fragments overlap between a pair of FragmentInfos.
static DIExpression * appendOpsToArg(const DIExpression *Expr, ArrayRef< uint64_t > Ops, unsigned ArgNo, bool StackValue=false)
Create a copy of Expr by appending the given list of Ops to each instance of the operand DW_OP_LLVM_a...
static std::optional< FragmentInfo > getFragmentInfo(expr_op_iterator Start, expr_op_iterator End)
Retrieve the details of this fragment expression.
uint64_t getNumLocationOperands() const
Return the number of unique location operands referred to (via DW_OP_LLVM_arg) in this expression; th...
static std::optional< DIExpression * > createFragmentExpression(const DIExpression *Expr, unsigned OffsetInBits, unsigned SizeInBits)
Create a DIExpression to describe one part of an aggregate variable that is fragmented across multipl...
static const DIExpression * convertToUndefExpression(const DIExpression *Expr)
Removes all elements from Expr that do not apply to an undef debug value, which includes every operat...
static DIExpression * prepend(const DIExpression *Expr, uint8_t Flags, int64_t Offset=0)
Prepend DIExpr with a deref and offset operation and optionally turn it into a stack value or/and an ...
static DIExpression * prependOpcodes(const DIExpression *Expr, SmallVectorImpl< uint64_t > &Ops, bool StackValue=false, bool EntryValue=false)
Prepend DIExpr with the given opcodes and optionally turn it into a stack value.
bool isValidLocationForIntrinsic(const DILocation *DL) const
Check that a location is valid for this variable.
Base class for variables.
std::optional< uint64_t > getSizeInBits() const
Determines the size of the variable's type.
This class represents an Operation in the Expression.
A parsed version of the target data layout string in and methods for querying it.
const StructLayout * getStructLayout(StructType *Ty) const
Returns a StructLayout object, indicating the alignment of the struct, its size, and the offsets of i...
unsigned getAllocaAddrSpace() const
unsigned getIndexSizeInBits(unsigned AS) const
Size in bits of index used for address calculation in getelementptr.
TypeSize getTypeStoreSize(Type *Ty) const
Returns the maximum number of bytes that may be overwritten by storing the specified type.
Align getPrefTypeAlign(Type *Ty) const
Returns the preferred stack/global alignment for the specified type.
This represents the llvm.dbg.label instruction.
DILabel * getLabel() const
Records a position in IR for a source label (DILabel).
Base class for non-instruction debug metadata records that have positions within IR.
DebugLoc getDebugLoc() const
This represents the llvm.dbg.value instruction.
iterator_range< location_op_iterator > getValues() const
DILocalVariable * getVariable() const
DIExpression * getExpression() const
bool isKillLocation() const
Record of a variable value-assignment, aka a non instruction representation of the dbg....
LocationType getType() const
DIExpression * getExpression() const
Value * getVariableLocationOp(unsigned OpIdx) const
DILocalVariable * getVariable() const
iterator_range< location_op_iterator > location_ops() const
Get the locations corresponding to the variable referenced by the debug info intrinsic.
DILocation * getInlinedAt() const
iterator find(const_arg_type_t< KeyT > Val)
size_type count(const_arg_type_t< KeyT > Val) const
Return 1 if the specified key is in the map, 0 otherwise.
std::pair< iterator, bool > insert(const std::pair< KeyT, ValueT > &KV)
void reserve(size_type NumEntries)
Grow the densemap so that it can contain at least NumEntries items before resizing again.
static constexpr ElementCount getFixed(ScalarTy MinVal)
static constexpr ElementCount get(ScalarTy MinVal, bool Scalable)
constexpr bool isScalar() const
Exactly one element.
Class representing an expression and its matching format.
This instruction compares its operands according to the predicate given to the constructor.
This is a fast-path instruction selection class that generates poor code and doesn't support illegal ...
bool allowReassoc() const
Flag queries.
An instruction for ordering other memory operations.
static FixedVectorType * get(Type *ElementType, unsigned NumElts)
This class represents a freeze function that returns random concrete value if an operand is either a ...
FunctionLoweringInfo - This contains information that is global to a function that is used when lower...
BranchProbabilityInfo * BPI
Register CreateRegs(const Value *V)
SmallPtrSet< const DbgVariableRecord *, 8 > PreprocessedDVRDeclares
Register DemoteRegister
DemoteRegister - if CanLowerReturn is false, DemoteRegister is a vreg allocated to hold a pointer to ...
BitVector DescribedArgs
Bitvector with a bit set if corresponding argument is described in ArgDbgValues.
DenseMap< const AllocaInst *, int > StaticAllocaMap
StaticAllocaMap - Keep track of frame indices for fixed sized allocas in the entry block.
int getArgumentFrameIndex(const Argument *A)
getArgumentFrameIndex - Get frame index for the byval argument.
DenseMap< const BasicBlock *, MachineBasicBlock * > MBBMap
MBBMap - A mapping from LLVM basic blocks to their machine code entry.
bool isExportedInst(const Value *V) const
isExportedInst - Return true if the specified value is an instruction exported from its block.
const LiveOutInfo * GetLiveOutRegInfo(Register Reg)
GetLiveOutRegInfo - Gets LiveOutInfo for a register, returning NULL if the register is a PHI destinat...
Register InitializeRegForValue(const Value *V)
unsigned ExceptionPointerVirtReg
If the current MBB is a landing pad, the exception pointer and exception selector registers are copie...
SmallPtrSet< const DbgDeclareInst *, 8 > PreprocessedDbgDeclares
Collection of dbg.declare instructions handled after argument lowering and before ISel proper.
DenseMap< const Value *, Register > ValueMap
ValueMap - Since we emit code for the function a basic block at a time, we must remember which virtua...
MachineBasicBlock::iterator InsertPt
MBB - The current insert position inside the current block.
MachineBasicBlock * MBB
MBB - The current block.
std::vector< std::pair< MachineInstr *, unsigned > > PHINodesToUpdate
PHINodesToUpdate - A list of phi instructions whose operand list will be updated after processing the...
unsigned ExceptionSelectorVirtReg
SmallVector< MachineInstr *, 8 > ArgDbgValues
ArgDbgValues - A list of DBG_VALUE instructions created during isel for function arguments that are i...
MachineRegisterInfo * RegInfo
Register CreateReg(MVT VT, bool isDivergent=false)
CreateReg - Allocate a single virtual register for the given type.
bool CanLowerReturn
CanLowerReturn - true iff the function's return value can be lowered to registers.
DenseMap< const Value *, ISD::NodeType > PreferredExtendType
Record the preferred extend type (ISD::SIGN_EXTEND or ISD::ZERO_EXTEND) for a value.
Register getCatchPadExceptionPointerVReg(const Value *CPI, const TargetRegisterClass *RC)
Class to represent function types.
unsigned getNumParams() const
Return the number of fixed parameters this function type requires.
Type * getParamType(unsigned i) const
Parameter type accessors.
Type * getReturnType() const
Data structure describing the variable locations in a function.
const BasicBlock & getEntryBlock() const
Attribute getFnAttribute(Attribute::AttrKind Kind) const
Return the attribute for the given attribute kind.
Intrinsic::ID getIntrinsicID() const LLVM_READONLY
getIntrinsicID - This method returns the ID number of the specified function, or Intrinsic::not_intri...
bool hasMinSize() const
Optimize this function for minimum size (-Oz).
bool hasGC() const
hasGC/getGC/setGC/clearGC - The name of the garbage collection algorithm to use during code generatio...
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
Constant * getPersonalityFn() const
Get the personality function associated with this function.
AttributeList getAttributes() const
Return the attribute list for this Function.
bool isIntrinsic() const
isIntrinsic - Returns true if the function's name starts with "llvm.".
bool isVarArg() const
isVarArg - Return true if this function takes a variable number of arguments.
bool hasFnAttribute(Attribute::AttrKind Kind) const
Return true if the function has the attribute.
Garbage collection metadata for a single function.
void addStackRoot(int Num, const Constant *Metadata)
addStackRoot - Registers a root that lives on the stack.
an instruction for type-safe pointer arithmetic to access elements of arrays and structs
static StringRef dropLLVMManglingEscape(StringRef Name)
If the given string begins with the GlobalValue name mangling escape character '\1',...
bool hasDLLImportStorageClass() const
Module * getParent()
Get the module that this global value is contained inside of...
This instruction compares its operands according to the predicate given to the constructor.
Indirect Branch Instruction.
This instruction inserts a struct field of array element value into an aggregate value.
const DebugLoc & getDebugLoc() const
Return the debug location for this node as a DebugLoc.
const BasicBlock * getParent() const
FastMathFlags getFastMathFlags() const LLVM_READONLY
Convenience function for getting all the fast-math flags, which must be an operator which supports th...
AAMDNodes getAAMetadata() const
Returns the AA metadata for this instruction.
@ MIN_INT_BITS
Minimum number of bits that can be specified.
Intrinsic::ID getIntrinsicID() const
Return the intrinsic ID of this intrinsic.
This is an important class for using LLVM in a threaded context.
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
The landingpad instruction holds all of the information necessary to generate correct exception handl...
An instruction for reading from memory.
This class is used to represent ISD::LOAD nodes.
static LocationSize precise(uint64_t Value)
static constexpr LocationSize beforeOrAfterPointer()
Any location before or after the base pointer (but still within the underlying object).
MCSymbol * createTempSymbol()
Create a temporary symbol with a unique name.
MCSymbol * getOrCreateFrameAllocSymbol(const Twine &FuncName, unsigned Idx)
Gets a symbol that will be defined to the final stack offset of a local variable after codegen.
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
uint64_t getScalarSizeInBits() const
@ INVALID_SIMPLE_VALUE_TYPE
unsigned getVectorNumElements() const
bool isVector() const
Return true if this is a vector value type.
bool isInteger() const
Return true if this is an integer or a vector integer type.
TypeSize getSizeInBits() const
Returns the size of the specified MVT in bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
ElementCount getVectorElementCount() const
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
bool bitsGE(MVT VT) const
Return true if this has no less bits than VT.
bool isScalarInteger() const
Return true if this is an integer, not including vectors.
static MVT getVectorVT(MVT VT, unsigned NumElements)
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
static MVT getIntegerVT(unsigned BitWidth)
void normalizeSuccProbs()
Normalize probabilities of all successors so that the sum of them becomes one.
bool isEHPad() const
Returns true if the block is a landing pad.
void setIsEHCatchretTarget(bool V=true)
Indicates if this is a target block of a catchret.
void setIsCleanupFuncletEntry(bool V=true)
Indicates if this is the entry block of a cleanup funclet.
const BasicBlock * getBasicBlock() const
Return the LLVM basic block that this instance corresponded to originally.
void setSuccProbability(succ_iterator I, BranchProbability Prob)
Set successor probability of a given iterator.
succ_iterator succ_begin()
std::vector< MachineBasicBlock * >::iterator succ_iterator
void addSuccessor(MachineBasicBlock *Succ, BranchProbability Prob=BranchProbability::getUnknown())
Add Succ as a successor of this MachineBasicBlock.
void addLiveIn(MCRegister PhysReg, LaneBitmask LaneMask=LaneBitmask::getAll())
Adds the specified register as a live in.
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
void setIsEHFuncletEntry(bool V=true)
Indicates if this is the entry block of an EH funclet.
void setIsEHScopeEntry(bool V=true)
Indicates if this is the entry block of an EH scope, i.e., the block that that used to have a catchpa...
void setMachineBlockAddressTaken()
Set this block to indicate that its address is used as something other than the target of a terminato...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
bool hasVarSizedObjects() const
This method may be called any time after instruction selection is complete to determine if the stack ...
void setIsImmutableObjectIndex(int ObjectIdx, bool IsImmutable)
Marks the immutability of an object.
int CreateStackObject(uint64_t Size, Align Alignment, bool isSpillSlot, const AllocaInst *Alloca=nullptr, uint8_t ID=0)
Create a new statically sized stack object, returning a nonnegative identifier to represent it.
void setHasPatchPoint(bool s=true)
void setHasStackMap(bool s=true)
bool hasOpaqueSPAdjustment() const
Returns true if the function contains opaque dynamic stack adjustments.
int getStackProtectorIndex() const
Return the index for the stack protector object.
void setStackProtectorIndex(int I)
void setIsAliasedObjectIndex(int ObjectIdx, bool IsAliased)
Set "maybe pointed to by an LLVM IR value" for an object.
Align getObjectAlign(int ObjectIdx) const
Return the alignment of the specified stack object.
int64_t getObjectSize(int ObjectIdx) const
Return the size of the specified object.
void RemoveStackObject(int ObjectIdx)
Remove or mark dead a statically sized stack object.
void setFunctionContextIndex(int I)
Description of the location of a variable whose Address is valid and unchanging during function execu...
const WinEHFuncInfo * getWinEHFuncInfo() const
getWinEHFuncInfo - Return information about how the current function uses Windows exception handling.
void setCallsUnwindInit(bool b)
bool useDebugInstrRef() const
Returns true if the function's variable locations are tracked with instruction referencing.
void setCallSiteBeginLabel(MCSymbol *BeginLabel, unsigned Site)
Map the begin label for a call site.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void setHasEHCatchret(bool V)
void setCallsEHReturn(bool b)
MachineMemOperand * getMachineMemOperand(MachinePointerInfo PtrInfo, MachineMemOperand::Flags f, LLT MemTy, Align base_alignment, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr, SyncScope::ID SSID=SyncScope::System, AtomicOrdering Ordering=AtomicOrdering::NotAtomic, AtomicOrdering FailureOrdering=AtomicOrdering::NotAtomic)
getMachineMemOperand - Allocate a new MachineMemOperand.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
unsigned getTypeIDFor(const GlobalValue *TI)
Return the type id for the specified typeinfo. This is function wide.
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
auto getInStackSlotVariableDbgInfo()
Returns the collection of variables for which we have debug info and that have been assigned a stack ...
void addCodeViewAnnotation(MCSymbol *Label, MDNode *MD)
Record annotations associated with a particular label.
Function & getFunction()
Return the LLVM function that this machine code represents.
MachineModuleInfo & getMMI() const
const MachineBasicBlock & front() const
bool hasEHFunclets() const
void addInvoke(MachineBasicBlock *LandingPad, MCSymbol *BeginLabel, MCSymbol *EndLabel)
Provide the begin and end labels of an invoke style call and associate it with a try landing pad bloc...
MachineBasicBlock * CreateMachineBasicBlock(const BasicBlock *BB=nullptr, std::optional< UniqueBBID > BBID=std::nullopt)
CreateMachineBasicBlock - Allocate a new MachineBasicBlock.
void erase(iterator MBBI)
void insert(iterator MBBI, MachineBasicBlock *MBB)
const MachineInstrBuilder & addSym(MCSymbol *Sym, unsigned char TargetFlags=0) const
const MachineInstrBuilder & addFrameIndex(int Idx) const
Representation of each machine instruction.
A description of a memory reference used in the backend.
Flags
Flags values. These may be or'd together.
@ MOVolatile
The memory access is volatile.
@ MODereferenceable
The memory access is dereferenceable (i.e., doesn't trap).
@ MOLoad
The memory access reads data.
@ MONonTemporal
The memory access is non-temporal.
@ MOInvariant
The memory access always returns the same value (or traps).
@ MOStore
The memory access writes data.
This class contains meta information specific to a module.
const MCContext & getContext() const
const Module * getModule() const
void setCurrentCallSite(unsigned Site)
Set the call site currently being processed.
unsigned getCurrentCallSite()
Get the call site currently being processed, if any.
static MachineOperand CreateReg(Register Reg, bool isDef, bool isImp=false, bool isKill=false, bool isDead=false, bool isUndef=false, bool isEarlyClobber=false, unsigned SubReg=0, bool isDebug=false, bool isInternalRead=false, bool isRenamable=false)
static MachineOperand CreateFI(int Idx)
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
ArrayRef< std::pair< MCRegister, Register > > liveins() const
An SDNode that represents everything that will be needed to construct a MachineInstr.
bool contains(const KeyT &Key) const
std::pair< iterator, bool > try_emplace(const KeyT &Key, Ts &&...Args)
Representation for a specific memory location.
static MemoryLocation getAfter(const Value *Ptr, const AAMDNodes &AATags=AAMDNodes())
Return a location that may access any location after Ptr, while remaining within the underlying objec...
A Module instance is used to store all the information related to an LLVM module.
Metadata * getModuleFlag(StringRef Key) const
Return the corresponding value if Key appears in module flags, otherwise return null.
Utility class for integer operators which may exhibit overflow - Add, Sub, Mul, and Shl.
static PointerType * get(Type *ElementType, unsigned AddressSpace)
This constructs a pointer to an object of the specified type in a numbered address space.
static PointerType * getUnqual(Type *ElementType)
This constructs a pointer to an object of the specified type in the default address space (address sp...
static PoisonValue * get(Type *T)
Static factory methods - Return an 'poison' object of the specified type.
A udiv or sdiv instruction, which can be marked as "exact", indicating that no bits are destroyed.
Wrapper class representing virtual and physical registers.
constexpr bool isVirtual() const
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isVirtualRegister(unsigned Reg)
Return true if the specified register number is in the virtual register namespace.
static constexpr bool isPhysicalRegister(unsigned Reg)
Return true if the specified register number is in the physical register namespace.
Resume the propagation of an exception.
Return a value (possibly void), from a function.
Holds the information from a dbg_label node through SDISel.
static SDDbgOperand fromNode(SDNode *Node, unsigned ResNo)
static SDDbgOperand fromFrameIdx(unsigned FrameIdx)
static SDDbgOperand fromVReg(unsigned VReg)
static SDDbgOperand fromConst(const Value *Const)
Holds the information from a dbg_value node through SDISel.
Wrapper class for IR location info (IR ordering and DebugLoc) to be passed into SDNode creation funct...
Represents one node in the SelectionDAG.
unsigned getOpcode() const
Return the SelectionDAG opcode value for this node.
iterator_range< value_op_iterator > op_values() const
unsigned getIROrder() const
Return the node ordering.
uint64_t getAsZExtVal() const
Helper method returns the zero-extended integer value of a ConstantSDNode.
unsigned getNumValues() const
Return the number of values defined/returned by this operator.
const SDValue & getOperand(unsigned Num) const
EVT getValueType(unsigned ResNo) const
Return the type of a specified result.
Represents a use of a SDNode.
Unlike LLVM values, Selection DAG nodes may return multiple values as the result of a computation.
SDNode * getNode() const
get the SDNode which holds the desired result
SDValue getValue(unsigned R) const
EVT getValueType() const
Return the ValueType of the referenced return value.
TypeSize getValueSizeInBits() const
Returns the size of the value in bits.
const SDValue & getOperand(unsigned i) const
unsigned getResNo() const
get the index which selects a specific result in the SDNode
MVT getSimpleValueType() const
Return the simple ValueType of the referenced return value.
unsigned getOpcode() const
SelectionDAGBuilder - This is the common target-independent lowering implementation that is parameter...
SDValue getValue(const Value *V)
getValue - Return an SDValue for the given Value.
void addDanglingDebugInfo(SmallVectorImpl< Value * > &Values, DILocalVariable *Var, DIExpression *Expr, bool IsVariadic, DebugLoc DL, unsigned Order)
Register a dbg_value which relies on a Value which we have not yet seen.
void visitDbgInfo(const Instruction &I)
void clearDanglingDebugInfo()
Clear the dangling debug information map.
void clear()
Clear out the current SelectionDAG and the associated state and prepare this SelectionDAGBuilder obje...
void visitBitTestHeader(SwitchCG::BitTestBlock &B, MachineBasicBlock *SwitchBB)
visitBitTestHeader - This function emits necessary code to produce value suitable for "bit tests"
void LowerStatepoint(const GCStatepointInst &I, const BasicBlock *EHPadBB=nullptr)
std::unique_ptr< SDAGSwitchLowering > SL
SDValue lowerRangeToAssertZExt(SelectionDAG &DAG, const Instruction &I, SDValue Op)
bool HasTailCall
This is set to true if a call in the current block has been translated as a tail call.
bool ShouldEmitAsBranches(const std::vector< SwitchCG::CaseBlock > &Cases)
If the set of cases should be emitted as a series of branches, return true.
void EmitBranchForMergedCondition(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
EmitBranchForMergedCondition - Helper method for FindMergedConditions.
void LowerDeoptimizeCall(const CallInst *CI)
void LowerCallSiteWithDeoptBundle(const CallBase *Call, SDValue Callee, const BasicBlock *EHPadBB)
SwiftErrorValueTracking & SwiftError
Information about the swifterror values used throughout the function.
SDValue getNonRegisterValue(const Value *V)
getNonRegisterValue - Return an SDValue for the given Value, but don't look in FuncInfo....
void CopyValueToVirtualRegister(const Value *V, unsigned Reg, ISD::NodeType ExtendType=ISD::ANY_EXTEND)
DenseMap< MachineBasicBlock *, SmallVector< unsigned, 4 > > LPadToCallSiteMap
Map a landing pad to the call site indexes.
void handleDebugDeclare(Value *Address, DILocalVariable *Variable, DIExpression *Expression, DebugLoc DL)
void visitBitTestCase(SwitchCG::BitTestBlock &BB, MachineBasicBlock *NextMBB, BranchProbability BranchProbToNext, unsigned Reg, SwitchCG::BitTestCase &B, MachineBasicBlock *SwitchBB)
visitBitTestCase - this function produces one "bit test"
bool shouldKeepJumpConditionsTogether(const FunctionLoweringInfo &FuncInfo, const BranchInst &I, Instruction::BinaryOps Opc, const Value *Lhs, const Value *Rhs, TargetLoweringBase::CondMergingParams Params) const
void LowerCallTo(const CallBase &CB, SDValue Callee, bool IsTailCall, bool IsMustTailCall, const BasicBlock *EHPadBB=nullptr)
StatepointLoweringState StatepointLowering
State used while lowering a statepoint sequence (gc_statepoint, gc_relocate, and gc_result).
void init(GCFunctionInfo *gfi, AAResults *AA, AssumptionCache *AC, const TargetLibraryInfo *li)
DenseMap< const Constant *, unsigned > ConstantsOut
void populateCallLoweringInfo(TargetLowering::CallLoweringInfo &CLI, const CallBase *Call, unsigned ArgIdx, unsigned NumArgs, SDValue Callee, Type *ReturnTy, AttributeSet RetAttrs, bool IsPatchPoint)
Populate a CallLowerinInfo (into CLI) based on the properties of the call being lowered.
void salvageUnresolvedDbgValue(const Value *V, DanglingDebugInfo &DDI)
For the given dangling debuginfo record, perform last-ditch efforts to resolve the debuginfo to somet...
SmallVector< SDValue, 8 > PendingLoads
Loads are not emitted to the program immediately.
GCFunctionInfo * GFI
Garbage collection metadata for the function.
SDValue getRoot()
Similar to getMemoryRoot, but also flushes PendingConstrainedFP(Strict) items.
void ExportFromCurrentBlock(const Value *V)
ExportFromCurrentBlock - If this condition isn't known to be exported from the current basic block,...
DebugLoc getCurDebugLoc() const
void resolveOrClearDbgInfo()
Evict any dangling debug information, attempting to salvage it first.
std::pair< SDValue, SDValue > lowerInvokable(TargetLowering::CallLoweringInfo &CLI, const BasicBlock *EHPadBB=nullptr)
SDValue getMemoryRoot()
Return the current virtual root of the Selection DAG, flushing any PendingLoad items.
void resolveDanglingDebugInfo(const Value *V, SDValue Val)
If we saw an earlier dbg_value referring to V, generate the debug data structures now that we've seen...
SDLoc getCurSDLoc() const
void visit(const Instruction &I)
void dropDanglingDebugInfo(const DILocalVariable *Variable, const DIExpression *Expr)
If we have dangling debug info that describes Variable, or an overlapping part of variable considerin...
SDValue getCopyFromRegs(const Value *V, Type *Ty)
If there was virtual register allocated for the value V emit CopyFromReg of the specified type Ty.
void CopyToExportRegsIfNeeded(const Value *V)
CopyToExportRegsIfNeeded - If the given value has virtual registers created for it,...
void handleKillDebugValue(DILocalVariable *Var, DIExpression *Expr, DebugLoc DbgLoc, unsigned Order)
Create a record for a kill location debug intrinsic.
void visitJumpTable(SwitchCG::JumpTable &JT)
visitJumpTable - Emit JumpTable node in the current MBB
void visitJumpTableHeader(SwitchCG::JumpTable &JT, SwitchCG::JumpTableHeader &JTH, MachineBasicBlock *SwitchBB)
visitJumpTableHeader - This function emits necessary code to produce index in the JumpTable from swit...
static const unsigned LowestSDNodeOrder
Lowest valid SDNodeOrder.
void LowerDeoptimizingReturn()
FunctionLoweringInfo & FuncInfo
Information about the function as a whole.
void setValue(const Value *V, SDValue NewN)
void FindMergedConditions(const Value *Cond, MachineBasicBlock *TBB, MachineBasicBlock *FBB, MachineBasicBlock *CurBB, MachineBasicBlock *SwitchBB, Instruction::BinaryOps Opc, BranchProbability TProb, BranchProbability FProb, bool InvertCond)
const TargetLibraryInfo * LibInfo
bool isExportableFromCurrentBlock(const Value *V, const BasicBlock *FromBB)
void visitSPDescriptorParent(StackProtectorDescriptor &SPD, MachineBasicBlock *ParentBB)
Codegen a new tail for a stack protector check ParentMBB which has had its tail spliced into a stack ...
bool handleDebugValue(ArrayRef< const Value * > Values, DILocalVariable *Var, DIExpression *Expr, DebugLoc DbgLoc, unsigned Order, bool IsVariadic)
For a given list of Values, attempt to create and record a SDDbgValue in the SelectionDAG.
SDValue getControlRoot()
Similar to getRoot, but instead of flushing all the PendingLoad items, flush all the PendingExports (...
void UpdateSplitBlock(MachineBasicBlock *First, MachineBasicBlock *Last)
When an MBB was split during scheduling, update the references that need to refer to the last resulti...
SDValue getValueImpl(const Value *V)
getValueImpl - Helper function for getValue and getNonRegisterValue.
void visitSwitchCase(SwitchCG::CaseBlock &CB, MachineBasicBlock *SwitchBB)
visitSwitchCase - Emits the necessary code to represent a single node in the binary search tree resul...
void visitSPDescriptorFailure(StackProtectorDescriptor &SPD)
Codegen the failure basic block for a stack protector check.
std::unique_ptr< FunctionLoweringInfo > FuncInfo
SmallPtrSet< const Instruction *, 4 > ElidedArgCopyInstrs
const TargetLowering * TLI
virtual void emitFunctionEntryCode()
SwiftErrorValueTracking * SwiftError
std::unique_ptr< SelectionDAGBuilder > SDB
Targets can subclass this to parameterize the SelectionDAG lowering and instruction selection process...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrnlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, SDValue MaxLength, MachinePointerInfo SrcPtrInfo) const
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, SDValue Op3, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
Emit target-specific code that performs a memcmp/bcmp, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcpy(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Dest, SDValue Src, MachinePointerInfo DestPtrInfo, MachinePointerInfo SrcPtrInfo, bool isStpcpy) const
Emit target-specific code that performs a strcpy or stpcpy, in cases where that is faster than a libc...
virtual std::pair< SDValue, SDValue > EmitTargetCodeForMemchr(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Src, SDValue Char, SDValue Length, MachinePointerInfo SrcPtrInfo) const
Emit target-specific code that performs a memchr, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrcmp(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Op1, SDValue Op2, MachinePointerInfo Op1PtrInfo, MachinePointerInfo Op2PtrInfo) const
Emit target-specific code that performs a strcmp, in cases where that is faster than a libcall.
virtual std::pair< SDValue, SDValue > EmitTargetCodeForStrlen(SelectionDAG &DAG, const SDLoc &DL, SDValue Chain, SDValue Src, MachinePointerInfo SrcPtrInfo) const
virtual SDValue EmitTargetCodeForSetTag(SelectionDAG &DAG, const SDLoc &dl, SDValue Chain, SDValue Addr, SDValue Size, MachinePointerInfo DstPtrInfo, bool ZeroData) const
Help to insert SDNodeFlags automatically in transforming.
This is used to represent a portion of an LLVM function in a low-level Data Dependence DAG representa...
SDValue getTargetGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, unsigned TargetFlags=0)
SDValue getExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT, unsigned Opcode)
Convert Op, which must be of integer type, to the integer type VT, by either any/sign/zero-extending ...
SDValue getLabelNode(unsigned Opcode, const SDLoc &dl, SDValue Root, MCSymbol *Label)
const SDValue & getRoot() const
Return the root tag of the SelectionDAG.
SDValue getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
SDValue getMaskedGather(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, ISD::LoadExtType ExtTy)
SDValue getAddrSpaceCast(const SDLoc &dl, EVT VT, SDValue Ptr, unsigned SrcAS, unsigned DestAS)
Return an AddrSpaceCastSDNode.
const TargetSubtargetInfo & getSubtarget() const
SDValue getMergeValues(ArrayRef< SDValue > Ops, const SDLoc &dl)
Create a MERGE_VALUES node from the given operands.
SDVTList getVTList(EVT VT)
Return an SDVTList that represents the list of values specified.
BlockFrequencyInfo * getBFI() const
MachineSDNode * getMachineNode(unsigned Opcode, const SDLoc &dl, EVT VT)
These are used for target selectors to create a new node with specified return type(s),...
void ExtractVectorElements(SDValue Op, SmallVectorImpl< SDValue > &Args, unsigned Start=0, unsigned Count=0, EVT EltVT=EVT())
Append the extracted elements from Start to Count out of the vector Op in Args.
SDValue getAtomicMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Value, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo)
SDValue getVScale(const SDLoc &DL, EVT VT, APInt MulImm, bool ConstantFold=true)
Return a node that represents the runtime scaling 'MulImm * RuntimeVL'.
SDValue getPseudoProbeNode(const SDLoc &Dl, SDValue Chain, uint64_t Guid, uint64_t Index, uint32_t Attr)
Creates a PseudoProbeSDNode with function GUID Guid and the index of the block Index it is probing,...
SDValue getConstantPool(const Constant *C, EVT VT, MaybeAlign Align=std::nullopt, int Offs=0, bool isT=false, unsigned TargetFlags=0)
SDValue getStridedLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &DL, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, bool IsExpanding=false)
SDValue getAtomicCmpSwap(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDVTList VTs, SDValue Chain, SDValue Ptr, SDValue Cmp, SDValue Swp, MachineMemOperand *MMO)
Gets a node for an atomic cmpxchg op.
SDDbgValue * getVRegDbgValue(DIVariable *Var, DIExpression *Expr, unsigned VReg, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a VReg SDDbgValue node.
void ReplaceAllUsesOfValuesWith(const SDValue *From, const SDValue *To, unsigned Num)
Like ReplaceAllUsesOfValueWith, but for multiple values at once.
SDValue getSetCC(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Chain=SDValue(), bool IsSignaling=false)
Helper function to make it easier to build SetCC's if you just have an ISD::CondCode instead of an SD...
void addMMRAMetadata(const SDNode *Node, MDNode *MMRA)
Set MMRAMetadata to be associated with Node.
SDValue getConstantFP(double Val, const SDLoc &DL, EVT VT, bool isTarget=false)
Create a ConstantFPSDNode wrapping a constant value.
SDValue getElementCount(const SDLoc &DL, EVT VT, ElementCount EC, bool ConstantFold=true)
SDValue getGetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getAssertAlign(const SDLoc &DL, SDValue V, Align A)
Return an AssertAlignSDNode.
SDValue getLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, MachinePointerInfo PtrInfo, MaybeAlign Alignment=MaybeAlign(), MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes(), const MDNode *Ranges=nullptr)
Loads are not normal binary operators: their result type is not determined by their operands,...
SDValue getStepVector(const SDLoc &DL, EVT ResVT, const APInt &StepVal)
Returns a vector of type ResVT whose elements contain the linear sequence <0, Step,...
SDValue getAtomic(unsigned Opcode, const SDLoc &dl, EVT MemVT, SDValue Chain, SDValue Ptr, SDValue Val, MachineMemOperand *MMO)
Gets a node for an atomic op, produces result (if relevant) and chain and takes 2 operands.
Align getEVTAlign(EVT MemoryVT) const
Compute the default alignment value for the given type.
bool shouldOptForSize() const
SDValue getVPZExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be an integer vector, to the vector-type VT,...
const TargetLowering & getTargetLoweringInfo() const
static constexpr unsigned MaxRecursionDepth
SDValue getStridedStoreVP(SDValue Chain, const SDLoc &DL, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Stride, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
void AddDbgValue(SDDbgValue *DB, bool isParameter)
Add a dbg_value SDNode.
SDValue getUNDEF(EVT VT)
Return an UNDEF node. UNDEF does not have a useful SDLoc.
SDValue getCALLSEQ_END(SDValue Chain, SDValue Op1, SDValue Op2, SDValue InGlue, const SDLoc &DL)
Return a new CALLSEQ_END node, which always must have a glue result (to ensure it's not CSE'd).
SDValue getGatherVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getBuildVector(EVT VT, const SDLoc &DL, ArrayRef< SDValue > Ops)
Return an ISD::BUILD_VECTOR node.
SDValue getMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo, const AAMDNodes &AAInfo=AAMDNodes(), AAResults *AA=nullptr)
void DeleteNode(SDNode *N)
Remove the specified node from the system.
SDValue getBitcast(EVT VT, SDValue V)
Return a bitcast using the SDLoc of the value operand, and casting to the provided type.
SDDbgValue * getDbgValueList(DIVariable *Var, DIExpression *Expr, ArrayRef< SDDbgOperand > Locs, ArrayRef< SDNode * > Dependencies, bool IsIndirect, const DebugLoc &DL, unsigned O, bool IsVariadic)
Creates a SDDbgValue node from a list of locations.
SDValue getNegative(SDValue Val, const SDLoc &DL, EVT VT)
Create negative operation as (SUB 0, Val).
void setNodeMemRefs(MachineSDNode *N, ArrayRef< MachineMemOperand * > NewMemRefs)
Mutate the specified machine node's memory references to the provided list.
const DataLayout & getDataLayout() const
ProfileSummaryInfo * getPSI() const
SDValue getTargetFrameIndex(int FI, EVT VT)
SDValue getTokenFactor(const SDLoc &DL, SmallVectorImpl< SDValue > &Vals)
Creates a new TokenFactor containing Vals.
const SelectionDAGTargetInfo & getSelectionDAGInfo() const
SDValue getMaskedHistogram(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDDbgLabel * getDbgLabel(DILabel *Label, const DebugLoc &DL, unsigned O)
Creates a SDDbgLabel node.
SDValue getStoreVP(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue getConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isTarget=false, bool isOpaque=false)
Create a ConstantSDNode wrapping a constant value.
SDValue getMemBasePlusOffset(SDValue Base, TypeSize Offset, const SDLoc &DL, const SDNodeFlags Flags=SDNodeFlags())
Returns sum of the base pointer and offset.
SDValue getGlobalAddress(const GlobalValue *GV, const SDLoc &DL, EVT VT, int64_t offset=0, bool isTargetGA=false, unsigned TargetFlags=0)
SDValue getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Align Alignment, bool isVol, bool AlwaysInline, bool isTailCall, MachinePointerInfo DstPtrInfo, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getVAArg(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue SV, unsigned Align)
VAArg produces a result and token chain, and takes a pointer and a source value as input.
SDValue getTruncStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, EVT SVT, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
SDValue getMDNode(const MDNode *MD)
Return an MDNodeSDNode which holds an MDNode.
void ReplaceAllUsesWith(SDValue From, SDValue To)
Modify anything using 'From' to use 'To' instead.
SDValue getStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Ptr, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags MMOFlags=MachineMemOperand::MONone, const AAMDNodes &AAInfo=AAMDNodes())
Helper function to build ISD::STORE nodes.
SDValue getSrcValue(const Value *v)
Construct a node to track a Value* through the backend.
SDValue getSplatVector(EVT VT, const SDLoc &DL, SDValue Op)
SDValue getAtomicMemcpy(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
MaybeAlign InferPtrAlign(SDValue Ptr) const
Infer alignment of a load / store address.
SDValue getCALLSEQ_START(SDValue Chain, uint64_t InSize, uint64_t OutSize, const SDLoc &DL)
Return a new CALLSEQ_START node, that starts new call frame, in which InSize bytes are set up inside ...
SDValue getRegister(unsigned Reg, EVT VT)
void AddDbgLabel(SDDbgLabel *DB)
Add a dbg_label SDNode.
SDValue getBasicBlock(MachineBasicBlock *MBB)
SDValue getSExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either sign-extending or trunca...
SDValue getEHLabel(const SDLoc &dl, SDValue Root, MCSymbol *Label)
SDValue getSetFPEnv(SDValue Chain, const SDLoc &dl, SDValue Ptr, EVT MemVT, MachineMemOperand *MMO)
SDValue getMaskedStore(SDValue Chain, const SDLoc &dl, SDValue Val, SDValue Base, SDValue Offset, SDValue Mask, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, bool IsTruncating=false, bool IsCompressing=false)
SDValue getExternalSymbol(const char *Sym, EVT VT)
const TargetMachine & getTarget() const
SDValue getPtrExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either truncating it or perform...
SDValue getAnyExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either any-extending or truncat...
SDValue getCopyToReg(SDValue Chain, const SDLoc &dl, unsigned Reg, SDValue N)
SDValue getBlockAddress(const BlockAddress *BA, EVT VT, int64_t Offset=0, bool isTarget=false, unsigned TargetFlags=0)
SDValue getLoadVP(ISD::MemIndexedMode AM, ISD::LoadExtType ExtType, EVT VT, const SDLoc &dl, SDValue Chain, SDValue Ptr, SDValue Offset, SDValue Mask, SDValue EVL, MachinePointerInfo PtrInfo, EVT MemVT, Align Alignment, MachineMemOperand::Flags MMOFlags, const AAMDNodes &AAInfo, const MDNode *Ranges=nullptr, bool IsExpanding=false)
SDValue getIntPtrConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
SDDbgValue * getConstantDbgValue(DIVariable *Var, DIExpression *Expr, const Value *C, const DebugLoc &DL, unsigned O)
Creates a constant SDDbgValue node.
SDValue getScatterVP(SDVTList VTs, EVT VT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType)
SDValue getValueType(EVT)
SDValue getTargetConstantFP(double Val, const SDLoc &DL, EVT VT)
SDValue getNode(unsigned Opcode, const SDLoc &DL, EVT VT, ArrayRef< SDUse > Ops)
Gets or creates the specified node.
SDValue getFPExtendOrRound(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of float type, to the float type VT, by either extending or rounding (by tr...
SDValue getAtomicMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst, SDValue Src, SDValue Size, Type *SizeTy, unsigned ElemSz, bool isTailCall, MachinePointerInfo DstPtrInfo, MachinePointerInfo SrcPtrInfo)
SDValue getTargetConstant(uint64_t Val, const SDLoc &DL, EVT VT, bool isOpaque=false)
SDDbgValue * getFrameIndexDbgValue(DIVariable *Var, DIExpression *Expr, unsigned FI, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a FrameIndex SDDbgValue node.
SDValue getJumpTable(int JTI, EVT VT, bool isTarget=false, unsigned TargetFlags=0)
SDValue getVPPtrExtOrTrunc(const SDLoc &DL, EVT VT, SDValue Op, SDValue Mask, SDValue EVL)
Convert a vector-predicated Op, which must be of integer type, to the vector-type integer type VT,...
SDValue getVectorIdxConstant(uint64_t Val, const SDLoc &DL, bool isTarget=false)
MachineFunction & getMachineFunction() const
SDValue getCopyFromReg(SDValue Chain, const SDLoc &dl, unsigned Reg, EVT VT)
SDValue getPtrExtendInReg(SDValue Op, const SDLoc &DL, EVT VT)
Return the expression required to extend the Op as a pointer value assuming it was the smaller SrcTy ...
SDValue getFrameIndex(int FI, EVT VT, bool isTarget=false)
const FunctionVarLocs * getFunctionVarLocs() const
Returns the result of the AssignmentTrackingAnalysis pass if it's available, otherwise return nullptr...
SDValue getZExtOrTrunc(SDValue Op, const SDLoc &DL, EVT VT)
Convert Op, which must be of integer type, to the integer type VT, by either zero-extending or trunca...
SDValue getCondCode(ISD::CondCode Cond)
SDValue getLifetimeNode(bool IsStart, const SDLoc &dl, SDValue Chain, int FrameIndex, int64_t Size, int64_t Offset=-1)
Creates a LifetimeSDNode that starts (IsStart==true) or ends (IsStart==false) the lifetime of the por...
SDValue getObjectPtrOffset(const SDLoc &SL, SDValue Ptr, TypeSize Offset)
Create an add instruction with appropriate flags when used for addressing some offset of an object.
LLVMContext * getContext() const
const SDValue & setRoot(SDValue N)
Set the current root tag of the SelectionDAG.
void addPCSections(const SDNode *Node, MDNode *MD)
Set PCSections to be associated with Node.
SDValue getShiftAmountConstant(uint64_t Val, EVT VT, const SDLoc &DL, bool LegalTypes=true)
SDValue getMemIntrinsicNode(unsigned Opcode, const SDLoc &dl, SDVTList VTList, ArrayRef< SDValue > Ops, EVT MemVT, MachinePointerInfo PtrInfo, Align Alignment, MachineMemOperand::Flags Flags=MachineMemOperand::MOLoad|MachineMemOperand::MOStore, LocationSize Size=0, const AAMDNodes &AAInfo=AAMDNodes())
Creates a MemIntrinsicNode that may produce a result and takes a list of operands.
SDValue getTargetExternalSymbol(const char *Sym, EVT VT, unsigned TargetFlags=0)
SDValue getMCSymbol(MCSymbol *Sym, EVT VT)
SDValue getSetCCVP(const SDLoc &DL, EVT VT, SDValue LHS, SDValue RHS, ISD::CondCode Cond, SDValue Mask, SDValue EVL)
Helper function to make it easier to build VP_SETCCs if you just have an ISD::CondCode instead of an ...
SDValue CreateStackTemporary(TypeSize Bytes, Align Alignment)
Create a stack temporary based on the size in bytes and the alignment.
SDValue getEntryNode() const
Return the token chain corresponding to the entry of the function.
SDDbgValue * getDbgValue(DIVariable *Var, DIExpression *Expr, SDNode *N, unsigned R, bool IsIndirect, const DebugLoc &DL, unsigned O)
Creates a SDDbgValue node.
SDValue getMaskedLoad(EVT VT, const SDLoc &dl, SDValue Chain, SDValue Base, SDValue Offset, SDValue Mask, SDValue Src0, EVT MemVT, MachineMemOperand *MMO, ISD::MemIndexedMode AM, ISD::LoadExtType, bool IsExpanding=false)
SDValue getSplat(EVT VT, const SDLoc &DL, SDValue Op)
Returns a node representing a splat of one value into all lanes of the provided vector type.
SDValue getVectorShuffle(EVT VT, const SDLoc &dl, SDValue N1, SDValue N2, ArrayRef< int > Mask)
Return an ISD::VECTOR_SHUFFLE node.
SDValue getMaskedScatter(SDVTList VTs, EVT MemVT, const SDLoc &dl, ArrayRef< SDValue > Ops, MachineMemOperand *MMO, ISD::MemIndexType IndexType, bool IsTruncating=false)
A templated base class for SmallPtrSet which provides the typesafe interface that is common across al...
std::pair< iterator, bool > insert(PtrType Ptr)
Inserts Ptr if and only if there is no element in the container equal to Ptr.
SmallPtrSet - This class implements a set which is optimized for holding SmallSize or less elements.
SmallSet - This maintains a set of unique values, optimizing for the case when the set is small (less...
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
reference emplace_back(ArgTypes &&... Args)
void append(ItTy in_start, ItTy in_end)
Add the specified range to the end of the SmallVector.
void swap(SmallVectorImpl &RHS)
void push_back(const T &Elt)
pointer data()
Return a pointer to the vector's buffer, even if empty().
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Encapsulates all of the information needed to generate a stack protector check, and signals to isel w...
MachineBasicBlock * getSuccessMBB()
MachineBasicBlock * getFailureMBB()
void clear()
Clear the memory usage of this object.
An instruction for storing to memory.
StringRef - Represent a constant reference to a string, i.e.
constexpr bool empty() const
empty - Check if the string is empty.
constexpr const char * data() const
data - Get a pointer to the start of the string (which may not be null terminated).
TypeSize getElementOffset(unsigned Idx) const
Class to represent struct types.
void setCurrentVReg(const MachineBasicBlock *MBB, const Value *, Register)
Set the swifterror virtual register in the VRegDefMap for this basic block.
Register getOrCreateVRegUseAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a use of a swifterror by an instruction.
Register getOrCreateVRegDefAt(const Instruction *, const MachineBasicBlock *, const Value *)
Get or create the swifterror value virtual register for a def of a swifterror by an instruction.
const Value * getFunctionArg() const
Get the (unique) function argument that was marked swifterror, or nullptr if this function has no swi...
Align getStackAlign() const
getStackAlignment - This method returns the number of bytes to which the stack pointer must be aligne...
TargetInstrInfo - Interface to description of machine instruction set.
TargetIntrinsicInfo - Interface to description of machine instruction set.
Provides information about what library functions are available for the current target.
bool hasOptimizedCodeGen(LibFunc F) const
Tests if the function is both available and a candidate for optimized code generation.
bool getLibFunc(StringRef funcName, LibFunc &F) const
Searches for a particular function name.
void setAttributes(const CallBase *Call, unsigned ArgIdx)
Set CallLoweringInfo attribute flags based on a call instruction and called function attributes.
virtual bool isFMAFasterThanFMulAndFAdd(const MachineFunction &MF, EVT) const
Return true if an FMA operation is faster than a pair of fmul and fadd instructions.
EVT getMemValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
EVT getValueType(const DataLayout &DL, Type *Ty, bool AllowUnknown=false) const
Return the EVT corresponding to this LLVM type.
LegalizeAction
This enum indicates whether operations are valid for a target, and if not, what action should be used...
virtual bool useStackGuardXorFP() const
If this function returns true, stack protection checks should XOR the frame pointer (or whichever poi...
virtual const TargetRegisterClass * getRegClassFor(MVT VT, bool isDivergent=false) const
Return the register class that should be used for the specified value type.
virtual bool isLegalScaleForGatherScatter(uint64_t Scale, uint64_t ElemSize) const
virtual bool isSExtCheaperThanZExt(EVT FromTy, EVT ToTy) const
Return true if sign-extension from FromTy to ToTy is cheaper than zero-extension.
virtual MVT getVectorIdxTy(const DataLayout &DL) const
Returns the type to be used for the index operand of: ISD::INSERT_VECTOR_ELT, ISD::EXTRACT_VECTOR_ELT...
virtual CondMergingParams getJumpConditionMergingParams(Instruction::BinaryOps, const Value *, const Value *) const
const TargetMachine & getTargetMachine() const
virtual unsigned getNumRegistersForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain targets require unusual breakdowns of certain types.
virtual bool isZExtFree(Type *FromTy, Type *ToTy) const
Return true if any actual instruction that defines a value of type FromTy implicitly zero-extends the...
virtual MVT getRegisterTypeForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT) const
Certain combinations of ABIs, Targets and features require that types are legal for some operations a...
virtual Value * getSDagStackGuard(const Module &M) const
Return the variable that's previously inserted by insertSSPDeclarations, if any, otherwise return nul...
virtual unsigned getNumRegisters(LLVMContext &Context, EVT VT, std::optional< MVT > RegisterVT=std::nullopt) const
Return the number of registers that this ValueType will eventually require.
bool isJumpExpensive() const
Return true if Flow Control is an expensive operation that should be avoided.
unsigned getBitWidthForCttzElements(Type *RetTy, ElementCount EC, bool ZeroIsPoison, const ConstantRange *VScaleRange) const
Return the minimum number of bits required to hold the maximum possible number of trailing zero vecto...
virtual bool shouldExtendGSIndex(EVT VT, EVT &EltTy) const
Returns true if the index type for a masked gather/scatter requires extending.
virtual unsigned getVectorTypeBreakdownForCallingConv(LLVMContext &Context, CallingConv::ID CC, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Certain targets such as MIPS require that some types such as vectors are always broken down into scal...
virtual Function * getSSPStackGuardCheck(const Module &M) const
If the target has a standard stack protection check function that performs validation and error handl...
Register getStackPointerRegisterToSaveRestore() const
If a physical register, this specifies the register that llvm.savestack/llvm.restorestack should save...
LegalizeAction getFixedPointOperationAction(unsigned Op, EVT VT, unsigned Scale) const
Some fixed point operations may be natively supported by the target but only for specific scales.
MachineMemOperand::Flags getAtomicMemOperandFlags(const Instruction &AI, const DataLayout &DL) const
virtual bool getTgtMemIntrinsic(IntrinsicInfo &, const CallInst &, MachineFunction &, unsigned) const
Given an intrinsic, checks if on the target the intrinsic will need to map to a MemIntrinsicNode (tou...
virtual bool allowsMisalignedMemoryAccesses(EVT, unsigned AddrSpace=0, Align Alignment=Align(1), MachineMemOperand::Flags Flags=MachineMemOperand::MONone, unsigned *=nullptr) const
Determine if the target supports unaligned memory accesses.
bool hasBigEndianPartOrdering(EVT VT, const DataLayout &DL) const
When splitting a value of the specified type into parts, does the Lo or Hi part come first?...
virtual Align getABIAlignmentForCallingConv(Type *ArgTy, const DataLayout &DL) const
Certain targets have context sensitive alignment requirements, where one type has the alignment requi...
virtual bool shouldExpandGetActiveLaneMask(EVT VT, EVT OpVT) const
Return true if the @llvm.get.active.lane.mask intrinsic should be expanded using generic code in Sele...
virtual EVT getSetCCResultType(const DataLayout &DL, LLVMContext &Context, EVT VT) const
Return the ValueType of the result of SETCC operations.
EVT getShiftAmountTy(EVT LHSTy, const DataLayout &DL, bool LegalTypes=true) const
Returns the type for the shift amount of a shift opcode.
MachineMemOperand::Flags getLoadMemOperandFlags(const LoadInst &LI, const DataLayout &DL, AssumptionCache *AC=nullptr, const TargetLibraryInfo *LibInfo=nullptr) const
virtual EVT getTypeToTransformTo(LLVMContext &Context, EVT VT) const
For types supported by the target, this is an identity function.
bool isTypeLegal(EVT VT) const
Return true if the target has native support for the specified value type.
MVT getProgramPointerTy(const DataLayout &DL) const
Return the type for code pointers, which is determined by the program address space specified through...
virtual MVT getPointerTy(const DataLayout &DL, uint32_t AS=0) const
Return the pointer type for the given address space, defaults to the pointer type from the data layou...
virtual MVT getFenceOperandTy(const DataLayout &DL) const
Return the type for operands of fence.
virtual bool shouldExpandGetVectorLength(EVT CountVT, unsigned VF, bool IsScalable) const
bool isOperationLegalOrCustom(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
virtual uint64_t getByValTypeAlignment(Type *Ty, const DataLayout &DL) const
Return the desired alignment for ByVal or InAlloca aggregate function arguments in the caller paramet...
virtual MVT hasFastEqualityCompare(unsigned NumBits) const
Return the preferred operand type if the target has a quick way to compare integer values of the give...
MachineMemOperand::Flags getStoreMemOperandFlags(const StoreInst &SI, const DataLayout &DL) const
virtual bool shouldExpandCttzElements(EVT VT) const
Return true if the @llvm.experimental.cttz.elts intrinsic should be expanded using generic code in Se...
virtual bool signExtendConstant(const ConstantInt *C) const
Return true if this constant should be sign extended when promoting to a larger type.
LegalizeTypeAction getTypeAction(LLVMContext &Context, EVT VT) const
Return how we should legalize values of this type, either it is already legal (return 'Legal') or we ...
virtual Register getExceptionPointerRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception address on entry to an ...
bool supportsUnalignedAtomics() const
Whether the target supports unaligned atomic operations.
std::vector< ArgListEntry > ArgListTy
bool isBeneficialToExpandPowI(int64_t Exponent, bool OptForSize) const
Return true if it is beneficial to expand an @llvm.powi.
MVT getFrameIndexTy(const DataLayout &DL) const
Return the type for frame index, which is determined by the alloca address space specified through th...
virtual Register getExceptionSelectorRegister(const Constant *PersonalityFn) const
If a physical register, this returns the register that receives the exception typeid on entry to a la...
virtual MVT getPointerMemTy(const DataLayout &DL, uint32_t AS=0) const
Return the in-memory pointer type for the given address space, defaults to the pointer type from the ...
MVT getRegisterType(MVT VT) const
Return the type of registers that this ValueType will eventually require.
bool isOperationLegalOrCustomOrPromote(unsigned Op, EVT VT, bool LegalOnly=false) const
Return true if the specified operation is legal on this target or can be made legal with custom lower...
unsigned getVectorTypeBreakdown(LLVMContext &Context, EVT VT, EVT &IntermediateVT, unsigned &NumIntermediates, MVT &RegisterVT) const
Vector types are broken down into some number of legal first class types.
virtual MVT getVPExplicitVectorLengthTy() const
Returns the type to be used for the EVL/AVL operand of VP nodes: ISD::VP_ADD, ISD::VP_SUB,...
This class defines information used to lower LLVM code to legal SelectionDAG operators that the targe...
virtual bool supportKCFIBundles() const
Return true if the target supports kcfi operand bundles.
virtual bool supportSwiftError() const
Return true if the target supports swifterror attribute.
virtual SDValue emitStackGuardXorFP(SelectionDAG &DAG, SDValue Val, const SDLoc &DL) const
virtual bool useLoadStackGuardNode() const
If this function returns true, SelectionDAGBuilder emits a LOAD_STACK_GUARD node when it is lowering ...
virtual EVT getTypeForExtReturn(LLVMContext &Context, EVT VT, ISD::NodeType) const
Return the type that should be used to zero or sign extend a zeroext/signext integer return value.
std::pair< SDValue, SDValue > makeLibCall(SelectionDAG &DAG, RTLIB::Libcall LC, EVT RetVT, ArrayRef< SDValue > Ops, MakeLibCallOptions CallOptions, const SDLoc &dl, SDValue Chain=SDValue()) const
Returns a pair of (return value, chain).
virtual InlineAsm::ConstraintCode getInlineAsmMemConstraint(StringRef ConstraintCode) const
std::vector< AsmOperandInfo > AsmOperandInfoVector
SDValue expandIS_FPCLASS(EVT ResultVT, SDValue Op, FPClassTest Test, SDNodeFlags Flags, const SDLoc &DL, SelectionDAG &DAG) const
Expand check for floating point class.
virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, const SDLoc &DL, SelectionDAG &DAG) const
This callback is used to prepare for a volatile or atomic load.
virtual ConstraintType getConstraintType(StringRef Constraint) const
Given a constraint, return the type of constraint it is for this target.
virtual bool splitValueIntoRegisterParts(SelectionDAG &DAG, const SDLoc &DL, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, std::optional< CallingConv::ID > CC) const
Target-specific splitting of values into parts that fit a register storing a legal type.
virtual SDValue joinRegisterPartsIntoValue(SelectionDAG &DAG, const SDLoc &DL, const SDValue *Parts, unsigned NumParts, MVT PartVT, EVT ValueVT, std::optional< CallingConv::ID > CC) const
Target-specific combining of register parts into its original value.
virtual SDValue LowerCall(CallLoweringInfo &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower calls into the specified DAG.
std::pair< SDValue, SDValue > LowerCallTo(CallLoweringInfo &CLI) const
This function lowers an abstract call to a function into an actual call.
virtual const char * getClearCacheBuiltinName() const
Return the builtin name for the __builtin___clear_cache intrinsic Default is to invoke the clear cach...
virtual SDValue LowerAsmOutputForConstraint(SDValue &Chain, SDValue &Glue, const SDLoc &DL, const AsmOperandInfo &OpInfo, SelectionDAG &DAG) const
virtual std::pair< unsigned, const TargetRegisterClass * > getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const
Given a physical register constraint (e.g.
virtual SDValue LowerFormalArguments(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::InputArg > &, const SDLoc &, SelectionDAG &, SmallVectorImpl< SDValue > &) const
This hook must be implemented to lower the incoming (formal) arguments, described by the Ins array,...
virtual AsmOperandInfoVector ParseConstraints(const DataLayout &DL, const TargetRegisterInfo *TRI, const CallBase &Call) const
Split up the constraint string from the inline assembly value into the specific constraints and their...
virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const
This callback is invoked for operations that are unsupported by the target, which are registered to u...
virtual SDValue LowerReturn(SDValue, CallingConv::ID, bool, const SmallVectorImpl< ISD::OutputArg > &, const SmallVectorImpl< SDValue > &, const SDLoc &, SelectionDAG &) const
This hook must be implemented to lower outgoing return values, described by the Outs array,...
virtual bool functionArgumentNeedsConsecutiveRegisters(Type *Ty, CallingConv::ID CallConv, bool isVarArg, const DataLayout &DL) const
For some targets, an LLVM struct type must be broken down into multiple simple types,...
virtual void ComputeConstraintToUse(AsmOperandInfo &OpInfo, SDValue Op, SelectionDAG *DAG=nullptr) const
Determines the constraint code and constraint type to use for the specific AsmOperandInfo,...
virtual void CollectTargetIntrinsicOperands(const CallInst &I, SmallVectorImpl< SDValue > &Ops, SelectionDAG &DAG) const
virtual void LowerAsmOperandForConstraint(SDValue Op, StringRef Constraint, std::vector< SDValue > &Ops, SelectionDAG &DAG) const
Lower the specified operand into the Ops vector.
virtual bool CanLowerReturn(CallingConv::ID, MachineFunction &, bool, const SmallVectorImpl< ISD::OutputArg > &, LLVMContext &) const
This hook should be implemented to check whether the return values described by the Outs array can fi...
virtual void LowerOperationWrapper(SDNode *N, SmallVectorImpl< SDValue > &Results, SelectionDAG &DAG) const
This callback is invoked by the type legalizer to legalize nodes with an illegal operand type but leg...
virtual bool isInlineAsmTargetBranch(const SmallVectorImpl< StringRef > &AsmStrs, unsigned OpNo) const
On x86, return true if the operand with index OpNo is a CALL or JUMP instruction, which can use eithe...
virtual const TargetIntrinsicInfo * getIntrinsicInfo() const
If intrinsic information is available, return it. If not, return null.
virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const
Returns true if a cast between SrcAS and DestAS is a noop.
const Triple & getTargetTriple() const
virtual TargetTransformInfo getTargetTransformInfo(const Function &F) const
Return a TargetTransformInfo for a given function.
CodeModel::Model getCodeModel() const
Returns the code model.
CodeGenOptLevel getOptLevel() const
Returns the optimization level: None, Less, Default, or Aggressive.
unsigned NoNaNsFPMath
NoNaNsFPMath - This flag is enabled when the -enable-no-nans-fp-math flag is specified on the command...
unsigned EnableFastISel
EnableFastISel - This flag enables fast-path instruction selection which trades away generated code q...
unsigned NoTrapAfterNoreturn
Do not emit a trap instruction for 'unreachable' IR instructions behind noreturn calls,...
unsigned TrapUnreachable
Emit target-specific trap instruction for 'unreachable' IR instructions.
FPOpFusion::FPOpFusionMode AllowFPOpFusion
AllowFPOpFusion - This flag is set by the -fp-contract=xxx option.
unsigned getID() const
Return the register class ID number.
iterator begin() const
begin/end - Return all of the registers in this class.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
virtual const TargetFrameLowering * getFrameLowering() const
virtual const TargetInstrInfo * getInstrInfo() const
Target - Wrapper for Target specific information.
Triple - Helper class for working with autoconf configuration names.
ArchType getArch() const
Get the parsed architecture type of this triple.
bool isPS() const
Tests whether the target is the PS4 or PS5 platform.
bool isWasm() const
Tests whether the target is wasm (32- and 64-bit).
bool isAArch64() const
Tests whether the target is AArch64 (little and big endian).
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
static constexpr TypeSize getFixed(ScalarTy ExactSize)
The instances of the Type class are immutable: once they are created, they are never changed.
bool isVectorTy() const
True if this is an instance of VectorType.
bool isPointerTy() const
True if this is an instance of PointerType.
static IntegerType * getInt1Ty(LLVMContext &C)
unsigned getPointerAddressSpace() const
Get the address space of this pointer or pointer vector type.
TypeID
Definitions of all of the base types for the Type system.
static IntegerType * getIntNTy(LLVMContext &C, unsigned N)
static Type * getVoidTy(LLVMContext &C)
LLVMContext & getContext() const
Return the LLVMContext in which this type was uniqued.
bool isIntegerTy() const
True if this is an instance of IntegerType.
bool isTokenTy() const
Return true if this is 'token'.
bool isFPOrFPVectorTy() const
Return true if this is a FP type or a vector of FP.
bool isVoidTy() const
Return true if this is 'void'.
Type * getScalarType() const
If this is a vector type, return the element type, otherwise return 'this'.
static UndefValue * get(Type *T)
Static factory methods - Return an 'undef' object of the specified type.
This function has undefined behavior.
A Use represents the edge between a Value definition and its users.
Value * getOperand(unsigned i) const
This class represents the va_arg llvm instruction, which returns an argument of the specified type gi...
CmpInst::Predicate getPredicate() const
This is the common base class for vector predication intrinsics.
static std::optional< unsigned > getVectorLengthParamPos(Intrinsic::ID IntrinsicID)
MaybeAlign getPointerAlignment() const
LLVM Value Representation.
Type * getType() const
All values are typed, get the type of this value.
bool hasOneUse() const
Return true if there is exactly one use of this value.
iterator_range< user_iterator > users()
LLVMContext & getContext() const
All values hold a context through their type.
StringRef getName() const
Return a constant reference to the value's name.
Base class of all SIMD vector types.
Type * getElementType() const
constexpr ScalarTy getFixedValue() const
constexpr bool isScalable() const
Returns whether the quantity is scaled by a runtime quantity (vscale).
constexpr ScalarTy getKnownMinValue() const
Returns the minimum value this quantity can represent.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
constexpr char Args[]
Key for Kernel::Metadata::mArgs.
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
@ AnyReg
OBSOLETED - Used for stack based JavaScript calls.
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
@ X86_VectorCall
MSVC calling convention that passes vectors and vector aggregates in SSE registers.
@ C
The default llvm calling convention, compatible with C.
NodeType
ISD::NodeType enum - This enum defines the target-independent operators for a SelectionDAG.
@ MERGE_VALUES
MERGE_VALUES - This node takes multiple discrete operands and returns them all as its individual resu...
@ STACKRESTORE
STACKRESTORE has two operands, an input chain and a pointer to restore to it returns an output chain.
@ STACKSAVE
STACKSAVE - STACKSAVE has one operand, an input chain.
@ STRICT_FSETCC
STRICT_FSETCC/STRICT_FSETCCS - Constrained versions of SETCC, used for floating-point operands only.
@ DELETED_NODE
DELETED_NODE - This is an illegal value that is used to catch errors.
@ SET_FPENV
Sets the current floating-point environment.
@ VECREDUCE_SEQ_FADD
Generic reduction nodes.
@ EH_SJLJ_LONGJMP
OUTCHAIN = EH_SJLJ_LONGJMP(INCHAIN, buffer) This corresponds to the eh.sjlj.longjmp intrinsic.
@ INSERT_SUBVECTOR
INSERT_SUBVECTOR(VECTOR1, VECTOR2, IDX) - Returns a vector with VECTOR2 inserted into VECTOR1.
@ BSWAP
Byte Swap and Counting operators.
@ SMULFIX
RESULT = [US]MULFIX(LHS, RHS, SCALE) - Perform fixed point multiplication on 2 integers with the same...
@ VAEND
VAEND, VASTART - VAEND and VASTART have three operands: an input chain, pointer, and a SRCVALUE.
@ ATOMIC_STORE
OUTCHAIN = ATOMIC_STORE(INCHAIN, ptr, val) This corresponds to "store atomic" instruction.
@ RESET_FPENV
Set floating-point environment to default state.
@ ADD
Simple integer binary arithmetic operators.
@ SMULFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ SET_FPMODE
Sets the current dynamic floating-point control modes.
@ ANY_EXTEND
ANY_EXTEND - Used for integer types. The high bits are undefined.
@ FMA
FMA - Perform a * b + c with no intermediate rounding step.
@ INTRINSIC_VOID
OUTCHAIN = INTRINSIC_VOID(INCHAIN, INTRINSICID, arg1, arg2, ...) This node represents a target intrin...
@ EH_SJLJ_SETUP_DISPATCH
OUTCHAIN = EH_SJLJ_SETUP_DISPATCH(INCHAIN) The target initializes the dispatch table here.
@ ATOMIC_CMP_SWAP_WITH_SUCCESS
Val, Success, OUTCHAIN = ATOMIC_CMP_SWAP_WITH_SUCCESS(INCHAIN, ptr, cmp, swap) N.b.
@ SINT_TO_FP
[SU]INT_TO_FP - These operators convert integers (whose interpreted sign depends on the first letter)...
@ CONCAT_VECTORS
CONCAT_VECTORS(VECTOR0, VECTOR1, ...) - Given a number of values of vector type with the same length ...
@ VECREDUCE_FMAX
FMIN/FMAX nodes can have flags, for NaN/NoNaN variants.
@ FADD
Simple binary floating point operators.
@ VECREDUCE_FMAXIMUM
FMINIMUM/FMAXIMUM nodes propatate NaNs and signed zeroes using the llvm.minimum and llvm....
@ ABS
ABS - Determine the unsigned absolute value of a signed integer value of the same bitwidth.
@ ATOMIC_FENCE
OUTCHAIN = ATOMIC_FENCE(INCHAIN, ordering, scope) This corresponds to the fence instruction.
@ RESET_FPMODE
Sets default dynamic floating-point control modes.
@ BITCAST
BITCAST - This operator converts between integer, vector and FP values, as if the value was stored to...
@ BUILD_PAIR
BUILD_PAIR - This is the opposite of EXTRACT_ELEMENT in some ways.
@ INIT_TRAMPOLINE
INIT_TRAMPOLINE - This corresponds to the init_trampoline intrinsic.
@ FLDEXP
FLDEXP - ldexp, inspired by libm (op0 * 2**op1).
@ SDIVFIX
RESULT = [US]DIVFIX(LHS, RHS, SCALE) - Perform fixed point division on 2 integers with the same width...
@ EH_RETURN
OUTCHAIN = EH_RETURN(INCHAIN, OFFSET, HANDLER) - This node represents 'eh_return' gcc dwarf builtin,...
@ ANNOTATION_LABEL
ANNOTATION_LABEL - Represents a mid basic block label used by annotations.
@ SET_ROUNDING
Set rounding mode.
@ SIGN_EXTEND
Conversion operators.
@ READSTEADYCOUNTER
READSTEADYCOUNTER - This corresponds to the readfixedcounter intrinsic.
@ ADDROFRETURNADDR
ADDROFRETURNADDR - Represents the llvm.addressofreturnaddress intrinsic.
@ BR
Control flow instructions. These all have token chains.
@ VECREDUCE_FADD
These reductions have relaxed evaluation order semantics, and have a single vector operand.
@ CTTZ_ZERO_UNDEF
Bit counting operators with an undefined result for zero inputs.
@ PREFETCH
PREFETCH - This corresponds to a prefetch intrinsic.
@ SSUBO
Same for subtraction.
@ BRIND
BRIND - Indirect branch.
@ BR_JT
BR_JT - Jumptable branch.
@ VECTOR_INTERLEAVE
VECTOR_INTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the same...
@ FCANONICALIZE
Returns platform specific canonical encoding of a floating point number.
@ IS_FPCLASS
Performs a check of floating point class property, defined by IEEE-754.
@ SSUBSAT
RESULT = [US]SUBSAT(LHS, RHS) - Perform saturation subtraction on 2 integers with the same bit width ...
@ SELECT
Select(COND, TRUEVAL, FALSEVAL).
@ ATOMIC_LOAD
Val, OUTCHAIN = ATOMIC_LOAD(INCHAIN, ptr) This corresponds to "load atomic" instruction.
@ EXTRACT_ELEMENT
EXTRACT_ELEMENT - This is used to get the lower or upper (determined by a Constant,...
@ SPLAT_VECTOR
SPLAT_VECTOR(VAL) - Returns a vector with the scalar value VAL duplicated in all lanes.
@ VACOPY
VACOPY - VACOPY has 5 operands: an input chain, a destination pointer, a source pointer,...
@ CopyFromReg
CopyFromReg - This node indicates that the input value is a virtual or physical register that is defi...
@ SADDO
RESULT, BOOL = [SU]ADDO(LHS, RHS) - Overflow-aware nodes for addition.
@ ARITH_FENCE
ARITH_FENCE - This corresponds to a arithmetic fence intrinsic.
@ VECREDUCE_ADD
Integer reductions may have a result type larger than the vector element type.
@ GET_ROUNDING
Returns current rounding mode: -1 Undefined 0 Round to 0 1 Round to nearest, ties to even 2 Round to ...
@ CLEANUPRET
CLEANUPRET - Represents a return from a cleanup block funclet.
@ GET_FPMODE
Reads the current dynamic floating-point control modes.
@ GET_FPENV
Gets the current floating-point environment.
@ SHL
Shift and rotation operations.
@ EXTRACT_SUBVECTOR
EXTRACT_SUBVECTOR(VECTOR, IDX) - Returns a subvector from VECTOR.
@ EntryToken
EntryToken - This is the marker used to indicate the start of a region.
@ READ_REGISTER
READ_REGISTER, WRITE_REGISTER - This node represents llvm.register on the DAG, which implements the n...
@ EXTRACT_VECTOR_ELT
EXTRACT_VECTOR_ELT(VECTOR, IDX) - Returns a single element from VECTOR identified by the (potentially...
@ ZERO_EXTEND
ZERO_EXTEND - Used for integer types, zeroing the new bits.
@ DEBUGTRAP
DEBUGTRAP - Trap intended to get the attention of a debugger.
@ VSCALE
VSCALE(IMM) - Returns the runtime scaling factor used to calculate the number of elements within a sc...
@ LOCAL_RECOVER
LOCAL_RECOVER - Represents the llvm.localrecover intrinsic.
@ FMINNUM
FMINNUM/FMAXNUM - Perform floating-point minimum or maximum on two values.
@ UBSANTRAP
UBSANTRAP - Trap with an immediate describing the kind of sanitizer failure.
@ SSHLSAT
RESULT = [US]SHLSAT(LHS, RHS) - Perform saturation left shift.
@ SMULO
Same for multiplication.
@ DYNAMIC_STACKALLOC
DYNAMIC_STACKALLOC - Allocate some number of bytes on the stack aligned to a specified boundary.
@ SMIN
[US]{MIN/MAX} - Binary minimum or maximum of signed or unsigned integers.
@ VECTOR_REVERSE
VECTOR_REVERSE(VECTOR) - Returns a vector, of the same type as VECTOR, whose elements are shuffled us...
@ SDIVFIXSAT
Same as the corresponding unsaturated fixed point instructions, but the result is clamped between the...
@ FP_EXTEND
X = FP_EXTEND(Y) - Extend a smaller FP type into a larger FP type.
@ VSELECT
Select with a vector condition (op #0) and two vector operands (ops #1 and #2), returning a vector re...
@ PCMARKER
PCMARKER - This corresponds to the pcmarker intrinsic.
@ INLINEASM_BR
INLINEASM_BR - Branching version of inline asm. Used by asm-goto.
@ EH_DWARF_CFA
EH_DWARF_CFA - This node represents the pointer to the DWARF Canonical Frame Address (CFA),...
@ FRAMEADDR
FRAMEADDR, RETURNADDR - These nodes represent llvm.frameaddress and llvm.returnaddress on the DAG.
@ STRICT_FP_ROUND
X = STRICT_FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision ...
@ FMINIMUM
FMINIMUM/FMAXIMUM - NaN-propagating minimum/maximum that also treat -0.0 as less than 0....
@ FP_TO_SINT
FP_TO_[US]INT - Convert a floating point value to a signed or unsigned integer.
@ READCYCLECOUNTER
READCYCLECOUNTER - This corresponds to the readcyclecounter intrinsic.
@ AND
Bitwise operators - logical and, logical or, logical xor.
@ TRAP
TRAP - Trapping instruction.
@ INTRINSIC_WO_CHAIN
RESULT = INTRINSIC_WO_CHAIN(INTRINSICID, arg1, arg2, ...) This node represents a target intrinsic fun...
@ STRICT_FADD
Constrained versions of the binary floating point operators.
@ INSERT_VECTOR_ELT
INSERT_VECTOR_ELT(VECTOR, VAL, IDX) - Returns VECTOR with the element at IDX replaced with VAL.
@ TokenFactor
TokenFactor - This node takes multiple tokens as input and produces a single token result.
@ VECTOR_SPLICE
VECTOR_SPLICE(VEC1, VEC2, IMM) - Returns a subvector of the same type as VEC1/VEC2 from CONCAT_VECTOR...
@ ATOMIC_SWAP
Val, OUTCHAIN = ATOMIC_SWAP(INCHAIN, ptr, amt) Val, OUTCHAIN = ATOMIC_LOAD_[OpName](INCHAIN,...
@ FFREXP
FFREXP - frexp, extract fractional and exponent component of a floating-point value.
@ FP_ROUND
X = FP_ROUND(Y, TRUNC) - Rounding 'Y' from a larger floating point type down to the precision of the ...
@ SPONENTRY
SPONENTRY - Represents the llvm.sponentry intrinsic.
@ INLINEASM
INLINEASM - Represents an inline asm block.
@ FP_TO_SINT_SAT
FP_TO_[US]INT_SAT - Convert floating point value in operand 0 to a signed or unsigned scalar integer ...
@ EH_SJLJ_SETJMP
RESULT, OUTCHAIN = EH_SJLJ_SETJMP(INCHAIN, buffer) This corresponds to the eh.sjlj....
@ TRUNCATE
TRUNCATE - Completely drop the high bits.
@ BRCOND
BRCOND - Conditional branch.
@ CATCHRET
CATCHRET - Represents a return from a catch block funclet.
@ AssertSext
AssertSext, AssertZext - These nodes record if a register contains a value that has already been zero...
@ FCOPYSIGN
FCOPYSIGN(X, Y) - Return the value of X with the sign of Y.
@ SADDSAT
RESULT = [US]ADDSAT(LHS, RHS) - Perform saturation addition on 2 integers with the same bit width (W)...
@ VECTOR_DEINTERLEAVE
VECTOR_DEINTERLEAVE(VEC1, VEC2) - Returns two vectors with all input and output vectors having the sa...
@ GET_DYNAMIC_AREA_OFFSET
GET_DYNAMIC_AREA_OFFSET - get offset from native SP to the address of the most recent dynamic alloca.
@ ADJUST_TRAMPOLINE
ADJUST_TRAMPOLINE - This corresponds to the adjust_trampoline intrinsic.
@ INTRINSIC_W_CHAIN
RESULT,OUTCHAIN = INTRINSIC_W_CHAIN(INCHAIN, INTRINSICID, arg1, ...) This node represents a target in...
@ BUILD_VECTOR
BUILD_VECTOR(ELT0, ELT1, ELT2, ELT3,...) - Return a fixed-width vector with the specified,...
MemIndexType
MemIndexType enum - This enum defines how to interpret MGATHER/SCATTER's index parameter when calcula...
CondCode
ISD::CondCode enum - These are ordered carefully to make the bitfields below work out,...
Flag
These should be considered private to the implementation of the MCInstrDesc class.
bool match(Val *V, const Pattern &P)
specificval_ty m_Specific(const Value *V)
Match if we have a specific specified value.
TwoOps_match< Val_t, Idx_t, Instruction::ExtractElement > m_ExtractElt(const Val_t &Val, const Idx_t &Idx)
Matches ExtractElementInst.
OneUse_match< T > m_OneUse(const T &SubPattern)
auto m_LogicalOr()
Matches L || R where L and R are arbitrary values.
VScaleVal_match m_VScale()
class_match< Value > m_Value()
Match an arbitrary value and ignore it.
auto m_LogicalAnd()
Matches L && R where L and R are arbitrary values.
BinaryOp_match< cst_pred_ty< is_all_ones >, ValTy, Instruction::Xor, true > m_Not(const ValTy &V)
Matches a 'Not' as 'xor V, -1' or 'xor -1, V'.
std::vector< CaseCluster > CaseClusterVector
void sortAndRangeify(CaseClusterVector &Clusters)
Sort Clusters and merge adjacent cases.
CaseClusterVector::iterator CaseClusterIt
std::pair< JumpTableHeader, JumpTable > JumpTableBlock
@ CC_Range
A cluster of adjacent case labels with the same destination, or just one case.
@ CC_JumpTable
A cluster of cases suitable for jump table lowering.
@ CC_BitTests
A cluster of cases suitable for bit test lowering.
Reg
All possible values of the reg field in the ModR/M byte.
initializer< Ty > init(const Ty &Val)
LocationClass< Ty > location(Ty &L)
@ DW_OP_LLVM_arg
Only used in LLVM metadata.
ExceptionBehavior
Exception behavior used for floating point operations.
@ ebStrict
This corresponds to "fpexcept.strict".
@ ebMayTrap
This corresponds to "fpexcept.maytrap".
@ ebIgnore
This corresponds to "fpexcept.ignore".
NodeAddr< FuncNode * > Func
This is an optimization pass for GlobalISel generic memory operations.
@ Low
Lower the current thread's priority such that it does not affect foreground tasks significantly.
unsigned Log2_32_Ceil(uint32_t Value)
Return the ceil log base 2 of the specified value, 32 if the value is zero.
ISD::CondCode getICmpCondCode(ICmpInst::Predicate Pred)
getICmpCondCode - Return the ISD condition code corresponding to the given LLVM IR integer condition ...
bool all_of(R &&range, UnaryPredicate P)
Provide wrappers to std::all_of which take ranges instead of having to pass begin/end explicitly.
int popcount(T Value) noexcept
Count the number of set bits in a value.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
void GetReturnInfo(CallingConv::ID CC, Type *ReturnType, AttributeList attr, SmallVectorImpl< ISD::OutputArg > &Outs, const TargetLowering &TLI, const DataLayout &DL)
Given an LLVM IR type and return type attributes, compute the return value EVTs and flags,...
MachineInstrBuilder BuildMI(MachineFunction &MF, const MIMetadata &MIMD, const MCInstrDesc &MCID)
Builder interface. Specify how to create the initial instruction itself.
bool isUIntN(unsigned N, uint64_t x)
Checks if an unsigned integer fits into the given (dynamic) bit width.
bool isOnlyUsedInZeroEqualityComparison(const Instruction *CxtI)
SDValue peekThroughBitcasts(SDValue V)
Return the non-bitcasted source operand of V if it exists.
int countr_one(T Value)
Count the number of ones from the least significant bit to the first zero bit.
void diagnoseDontCall(const CallInst &CI)
auto successors(const MachineBasicBlock *BB)
bool isIntOrFPConstant(SDValue V)
Return true if V is either a integer or FP constant.
void append_range(Container &C, Range &&R)
Wrapper function to append range R to container C.
Value * GetPointerBaseWithConstantOffset(Value *Ptr, int64_t &Offset, const DataLayout &DL, bool AllowNonInbounds=true)
Analyze the specified pointer to see if it can be expressed as a base pointer plus a constant offset.
gep_type_iterator gep_type_end(const User *GEP)
ConstantRange getConstantRangeFromMetadata(const MDNode &RangeMD)
Parse out a conservative ConstantRange from !range metadata.
bool isScopedEHPersonality(EHPersonality Pers)
Returns true if this personality uses scope-style EH IR instructions: catchswitch,...
int countr_zero(T Val)
Count number of 0's from the least significant bit to the most stopping at the first 1.
bool any_of(R &&range, UnaryPredicate P)
Provide wrappers to std::any_of which take ranges instead of having to pass begin/end explicitly.
llvm::SmallVector< int, 16 > createStrideMask(unsigned Start, unsigned Stride, unsigned VF)
Create a stride shuffle mask.
@ SPF_ABS
Floating point maxnum.
@ SPF_NABS
Absolute value.
@ SPF_FMAXNUM
Floating point minnum.
@ SPF_UMIN
Signed minimum.
@ SPF_UMAX
Signed maximum.
@ SPF_SMAX
Unsigned minimum.
@ SPF_FMINNUM
Unsigned maximum.
decltype(auto) get(const PointerIntPair< PointerTy, IntBits, IntType, PtrTraits, Info > &Pair)
detail::zippy< detail::zip_first, T, U, Args... > zip_first(T &&t, U &&u, Args &&...args)
zip iterator that, for the sake of efficiency, assumes the first iteratee to be the shortest.
void sort(IteratorTy Start, IteratorTy End)
FPClassTest
Floating-point class tests, supported by 'is_fpclass' intrinsic.
SelectPatternResult matchSelectPattern(Value *V, Value *&LHS, Value *&RHS, Instruction::CastOps *CastOp=nullptr, unsigned Depth=0)
Pattern match integer [SU]MIN, [SU]MAX and ABS idioms, returning the kind and providing the out param...
raw_ostream & dbgs()
dbgs() - This returns a reference to a raw_ostream for debugging messages.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
bool hasSingleElement(ContainerTy &&C)
Returns true if the given container only contains a single element.
ConstantRange getVScaleRange(const Function *F, unsigned BitWidth)
Determine the possible constant range of vscale with the given bit width, based on the vscale_range f...
ISD::CondCode getFCmpCondCode(FCmpInst::Predicate Pred)
getFCmpCondCode - Return the ISD condition code corresponding to the given LLVM IR floating-point con...
EHPersonality classifyEHPersonality(const Value *Pers)
See if the given exception handling personality function is one that we understand.
Value * salvageDebugInfoImpl(Instruction &I, uint64_t CurrentLocOps, SmallVectorImpl< uint64_t > &Ops, SmallVectorImpl< Value * > &AdditionalValues)
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
@ Global
Append to llvm.global_dtors.
AtomicOrdering
Atomic ordering for LLVM's memory model.
@ First
Helpers to iterate all locations in the MemoryEffectsBase class.
bool isFuncletEHPersonality(EHPersonality Pers)
Returns true if this is a personality function that invokes handler funclets (which must return to it...
void getUnderlyingObjects(const Value *V, SmallVectorImpl< const Value * > &Objects, LoopInfo *LI=nullptr, unsigned MaxLookup=6)
This method is similar to getUnderlyingObject except that it can look through phi and select instruct...
bool isAssignmentTrackingEnabled(const Module &M)
Return true if assignment tracking is enabled for module M.
llvm::SmallVector< int, 16 > createInterleaveMask(unsigned VF, unsigned NumVecs)
Create an interleave shuffle mask.
@ UMin
Unsigned integer min implemented in terms of select(cmp()).
@ Or
Bitwise or logical OR of integers.
@ Mul
Product of integers.
@ And
Bitwise or logical AND of integers.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
@ SPNB_RETURNS_NAN
NaN behavior not applicable.
@ SPNB_RETURNS_OTHER
Given one NaN input, returns the NaN.
@ SPNB_RETURNS_ANY
Given one NaN input, returns the non-NaN.
DWARFExpression::Operation Op
ISD::CondCode getFCmpCodeWithoutNaN(ISD::CondCode CC)
getFCmpCodeWithoutNaN - Given an ISD condition code comparing floats, return the equivalent code if w...
void ComputeValueVTs(const TargetLowering &TLI, const DataLayout &DL, Type *Ty, SmallVectorImpl< EVT > &ValueVTs, SmallVectorImpl< EVT > *MemVTs, SmallVectorImpl< TypeSize > *Offsets=nullptr, TypeSize StartingOffset=TypeSize::getZero())
ComputeValueVTs - Given an LLVM IR type, compute a sequence of EVTs that represent all the individual...
bool isAsynchronousEHPersonality(EHPersonality Pers)
Returns true if this personality function catches asynchronous exceptions.
std::optional< RoundingMode > convertStrToRoundingMode(StringRef)
Returns a valid RoundingMode enumerator when given a string that is valid as input in constrained int...
gep_type_iterator gep_type_begin(const User *GEP)
void erase_if(Container &C, UnaryPredicate P)
Provide a container algorithm similar to C++ Library Fundamentals v2's erase_if which is equivalent t...
GlobalValue * ExtractTypeInfo(Value *V)
ExtractTypeInfo - Returns the type info, possibly bitcast, encoded in V.
Align commonAlignment(Align A, uint64_t Offset)
Returns the alignment that satisfies both alignments.
bool isInTailCallPosition(const CallBase &Call, const TargetMachine &TM)
Test if the given instruction is in a position to be optimized with a tail-call.
bool all_equal(std::initializer_list< T > Values)
Returns true if all Values in the initializer lists are equal or the list.
Constant * ConstantFoldLoadFromConstPtr(Constant *C, Type *Ty, APInt Offset, const DataLayout &DL)
Return the value that a load from C with offset Offset would produce if it is constant and determinab...
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
unsigned succ_size(const MachineBasicBlock *BB)
unsigned ComputeLinearIndex(Type *Ty, const unsigned *Indices, const unsigned *IndicesEnd, unsigned CurIndex=0)
Compute the linearized index of a member in a nested aggregate/struct/array.
T bit_floor(T Value)
Returns the largest integral power of two no greater than Value if Value is nonzero.
void swap(llvm::BitVector &LHS, llvm::BitVector &RHS)
Implement std::swap in terms of BitVector swap.
A collection of metadata nodes that might be associated with a memory access used by the alias-analys...
static const fltSemantics & IEEEsingle() LLVM_READNONE
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
TypeSize getStoreSize() const
Return the number of bytes overwritten by a store of the specified value type.
static EVT getVectorVT(LLVMContext &Context, EVT VT, unsigned NumElements, bool IsScalable=false)
Returns the EVT that represents a vector NumElements in length, where each element is of type VT.
uint64_t getScalarStoreSize() const
bool bitsGT(EVT VT) const
Return true if this has more bits than VT.
bool bitsLT(EVT VT) const
Return true if this has less bits than VT.
bool isFloatingPoint() const
Return true if this is a FP or a vector FP type.
ElementCount getVectorElementCount() const
TypeSize getSizeInBits() const
Return the size of the specified value type in bits.
unsigned getVectorMinNumElements() const
Given a vector type, return the minimum number of elements it contains.
uint64_t getScalarSizeInBits() const
MVT getSimpleVT() const
Return the SimpleValueType held in the specified simple EVT.
static EVT getIntegerVT(LLVMContext &Context, unsigned BitWidth)
Returns the EVT that represents an integer with the given number of bits.
uint64_t getFixedSizeInBits() const
Return the size of the specified fixed width value type in bits.
bool isFixedLengthVector() const
bool isVector() const
Return true if this is a vector value type.
EVT getScalarType() const
If this is a vector type, return the element type, otherwise return this.
bool bitsGE(EVT VT) const
Return true if this has no less bits than VT.
Type * getTypeForEVT(LLVMContext &Context) const
This method returns an LLVM type corresponding to the specified EVT.
bool isScalableVector() const
Return true if this is a vector type where the runtime length is machine dependent.
EVT getVectorElementType() const
Given a vector type, return the type of each element.
bool isScalarInteger() const
Return true if this is an integer, but not a vector.
EVT changeVectorElementType(EVT EltVT) const
Return a VT for a vector type whose attributes match ourselves with the exception of the element type...
unsigned getVectorNumElements() const
Given a vector type, return the number of elements it contains.
EVT getHalfNumVectorElementsVT(LLVMContext &Context) const
bool isInteger() const
Return true if this is an integer or a vector integer type.
void setPointerAddrSpace(unsigned AS)
void setOrigAlign(Align A)
OutputArg - This struct carries flags and a value for a single outgoing (actual) argument or outgoing...
ConstraintPrefix Type
Type - The basic type of the constraint: input/output/clobber/label.
unsigned countMinLeadingZeros() const
Returns the minimum number of leading zero bits.
This class contains a discriminated union of information about pointers in memory operands,...
static MachinePointerInfo getUnknownStack(MachineFunction &MF)
Stack memory without other information.
static MachinePointerInfo getFixedStack(MachineFunction &MF, int FI, int64_t Offset=0)
Return a MachinePointerInfo record that refers to the specified FrameIndex.
This struct is a compact representation of a valid (power of two) or undefined (0) alignment.
Align valueOrOne() const
For convenience, returns a valid alignment or 1 if undefined.
This struct represents the registers (physical or virtual) that a particular set of values is assigne...
SmallVector< unsigned, 4 > Regs
This list holds the registers assigned to the values.
SmallVector< unsigned, 4 > RegCount
This list holds the number of registers for each value.
bool isABIMangled() const
SmallVector< EVT, 4 > ValueVTs
The value types of the values, which may not be legal, and may need be promoted or synthesized from o...
SmallVector< std::pair< unsigned, TypeSize >, 4 > getRegsAndSizes() const
Return a list of registers and their sizes.
void AddInlineAsmOperands(InlineAsm::Kind Code, bool HasMatching, unsigned MatchingIdx, const SDLoc &dl, SelectionDAG &DAG, std::vector< SDValue > &Ops) const
Add this value to the specified inlineasm node operand list.
SDValue getCopyFromRegs(SelectionDAG &DAG, FunctionLoweringInfo &FuncInfo, const SDLoc &dl, SDValue &Chain, SDValue *Glue, const Value *V=nullptr) const
Emit a series of CopyFromReg nodes that copies from this value and returns the result as a ValueVTs v...
SmallVector< MVT, 4 > RegVTs
The value types of the registers.
void getCopyToRegs(SDValue Val, SelectionDAG &DAG, const SDLoc &dl, SDValue &Chain, SDValue *Glue, const Value *V=nullptr, ISD::NodeType PreferredExtendType=ISD::ANY_EXTEND) const
Emit a series of CopyToReg nodes that copies the specified value into the registers specified by this...
std::optional< CallingConv::ID > CallConv
Records if this value needs to be treated in an ABI dependant manner, different to normal type legali...
bool occupiesMultipleRegs() const
Check if the total RegCount is greater than one.
These are IR-level optimization flags that may be propagated to SDNodes.
void copyFMF(const FPMathOperator &FPMO)
Propagate the fast-math-flags from an IR FPMathOperator.
bool hasAllowReassociation() const
This represents a list of ValueType's that has been intern'd by a SelectionDAG.
A MapVector that performs no allocations if smaller than a certain size.
MachineBasicBlock * Default
BranchProbability DefaultProb
MachineBasicBlock * Parent
bool FallthroughUnreachable
MachineBasicBlock * ThisBB
This structure is used to communicate between SelectionDAGBuilder and SDISel for the code generation ...
BranchProbability TrueProb
BranchProbability FalseProb
MachineBasicBlock * TrueBB
MachineBasicBlock * FalseBB
SDLoc DL
The debug location of the instruction this CaseBlock was produced from.
A cluster of case labels.
static CaseCluster range(const ConstantInt *Low, const ConstantInt *High, MachineBasicBlock *MBB, BranchProbability Prob)
This contains information for each constraint that we are lowering.
TargetLowering::ConstraintType ConstraintType
Information about the constraint code, e.g.
This structure contains all information that is necessary for lowering calls.
CallLoweringInfo & setConvergent(bool Value=true)
CallLoweringInfo & setCFIType(const ConstantInt *Type)
SmallVector< ISD::InputArg, 32 > Ins
bool IsPostTypeLegalization
SmallVector< SDValue, 4 > InVals
CallLoweringInfo & setDiscardResult(bool Value=true)
CallLoweringInfo & setIsPatchPoint(bool Value=true)
CallLoweringInfo & setDebugLoc(const SDLoc &dl)
CallLoweringInfo & setTailCall(bool Value=true)
CallLoweringInfo & setIsPreallocated(bool Value=true)
CallLoweringInfo & setConvergenceControlToken(SDValue Token)
SmallVector< ISD::OutputArg, 32 > Outs
SmallVector< SDValue, 32 > OutVals
CallLoweringInfo & setChain(SDValue InChain)
CallLoweringInfo & setCallee(CallingConv::ID CC, Type *ResultType, SDValue Target, ArgListTy &&ArgsList, AttributeSet ResultAttrs={})
This structure is used to pass arguments to makeLibCall function.
MakeLibCallOptions & setDiscardResult(bool Value=true)
void addIPToStateRange(const InvokeInst *II, MCSymbol *InvokeBegin, MCSymbol *InvokeEnd)