79 std::unique_ptr<MCStreamer> &&Streamer) {
91 std::unique_ptr<MCStreamer> Streamer)
97 return "AMDGPU Assembly Printer";
114void AMDGPUAsmPrinter::initTargetStreamer(
Module &M) {
120 initializeTargetID(M);
140 if (!
Value->evaluateAsAbsolute(Val)) {
150 initTargetStreamer(M);
158 HSAMetadataStream->end();
173 STM.getCPU() +
" is only available on code object version 6 or better",
180 initializeTargetID(*
F.getParent());
182 const auto &FunctionTargetID = STM.getTargetID();
185 if (FunctionTargetID.isXnackSupported() &&
186 FunctionTargetID.getXnackSetting() != IsaInfo::TargetIDSetting::Any &&
187 FunctionTargetID.getXnackSetting() !=
getTargetStreamer()->getTargetID()->getXnackSetting()) {
189 "' function does not match module xnack setting");
194 if (FunctionTargetID.isSramEccSupported() &&
195 FunctionTargetID.getSramEccSetting() != IsaInfo::TargetIDSetting::Any &&
198 "' function does not match module sramecc setting");
205 if (STM.isMesaKernel(
F) &&
209 getAmdKernelCode(KernelCode, CurrentProgramInfo, *
MF);
213 if (STM.isAmdHsaOS())
214 HSAMetadataStream->emitKernel(*
MF, CurrentProgramInfo);
232 auto &
Context = Streamer.getContext();
233 auto &ObjectFileInfo = *
Context.getObjectFileInfo();
234 auto &ReadOnlySection = *ObjectFileInfo.getReadOnlySection();
236 Streamer.pushSection();
237 Streamer.switchSection(&ReadOnlySection);
241 Streamer.emitValueToAlignment(
Align(64), 0, 1, 0);
242 ReadOnlySection.ensureMinAlignment(
Align(64));
249 STM, KernelName, getAmdhsaKernelDescriptor(*
MF, CurrentProgramInfo),
259 Streamer.popSection();
267 OS <<
"implicit-def: "
271 OS <<
" : SGPR spill to VGPR lane";
291 if (DumpCodeInstEmitter) {
318 ": unsupported initializer for address space");
332 "' is already defined");
341 TS->emitAMDGPULDS(GVSym,
Size, Alignment);
352 switch (CodeObjectVersion) {
385void AMDGPUAsmPrinter::emitCommonFunctionComments(
402uint16_t AMDGPUAsmPrinter::getAmdhsaKernelCodeProperties(
409 KernelCodeProperties |=
410 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER;
413 KernelCodeProperties |=
414 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR;
417 KernelCodeProperties |=
418 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR;
421 KernelCodeProperties |=
422 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR;
425 KernelCodeProperties |=
426 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID;
429 KernelCodeProperties |=
430 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT;
433 KernelCodeProperties |=
434 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
439 KernelCodeProperties |= amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK;
441 return KernelCodeProperties;
458 Align MaxKernArgAlign;
475 return KernelDescriptor;
484 ResourceUsage = &getAnalysis<AMDGPUResourceUsageAnalysis>();
506 getSIProgramInfo(CurrentProgramInfo,
MF);
511 EmitPALMetadata(
MF, CurrentProgramInfo);
513 emitPALFunctionMetadata(
MF);
515 EmitProgramInfoSI(
MF, CurrentProgramInfo);
518 DumpCodeInstEmitter =
nullptr;
522 bool SaveFlag =
OutStreamer->getUseAssemblerInfoForParsing();
525 OutStreamer->setUseAssemblerInfoForParsing(SaveFlag);
545 OutStreamer->emitRawComment(
" Function info:",
false);
548 emitCommonFunctionComments(
551 Info.getTotalNumVGPRs(STM),
553 Info.PrivateSegmentSize, getFunctionCodeSize(
MF), MFI);
557 OutStreamer->emitRawComment(
" Kernel info:",
false);
558 emitCommonFunctionComments(
559 getMCExprValue(CurrentProgramInfo.
NumArchVGPR, Ctx),
561 : std::optional<uint32_t>(),
562 getMCExprValue(CurrentProgramInfo.
NumVGPR, Ctx),
563 getMCExprValue(CurrentProgramInfo.
NumSGPR, Ctx),
564 getMCExprValue(CurrentProgramInfo.
ScratchSize, Ctx),
565 getFunctionCodeSize(
MF), MFI);
573 " bytes/workgroup (compile time only)",
false);
585 " NumSGPRsForWavesPerEU: " +
590 " NumVGPRsForWavesPerEU: " +
611 " COMPUTE_PGM_RSRC2:SCRATCH_EN: " +
614 OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:USER_SGPR: " +
617 OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TRAP_HANDLER: " +
620 OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TGID_X_EN: " +
623 OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TGID_Y_EN: " +
626 OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TGID_Z_EN: " +
629 OutStreamer->emitRawComment(
" COMPUTE_PGM_RSRC2:TIDIG_COMP_CNT: " +
637 " COMPUTE_PGM_RSRC3_GFX90A:ACCUM_OFFSET: " +
640 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET))),
643 " COMPUTE_PGM_RSRC3_GFX90A:TG_SPLIT: " +
646 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT))),
651 if (DumpCodeInstEmitter) {
657 std::string Comment =
"\n";
660 Comment +=
" ; " +
HexLines[i] +
"\n";
672void AMDGPUAsmPrinter::initializeTargetID(
const Module &M) {
686 if ((!TSTargetID->isXnackSupported() || TSTargetID->isXnackOnOrOff()) &&
687 (!TSTargetID->isSramEccSupported() || TSTargetID->isSramEccOnOrOff()))
692 if (TSTargetID->isXnackSupported())
693 if (TSTargetID->getXnackSetting() == IsaInfo::TargetIDSetting::Any)
695 if (TSTargetID->isSramEccSupported())
696 if (TSTargetID->getSramEccSetting() == IsaInfo::TargetIDSetting::Any)
697 TSTargetID->setSramEccSetting(STMTargetID.getSramEccSetting());
712 if (
MI.isDebugInstr())
715 CodeSize +=
TII->getInstSizeInBytes(
MI);
722void AMDGPUAsmPrinter::getSIProgramInfo(
SIProgramInfo &ProgInfo,
729 auto CreateExpr = [&Ctx](int64_t
Value) {
735 if (
Value->evaluateAsAbsolute(Val)) {
744 ProgInfo.
NumVGPR = CreateExpr(
Info.getTotalNumVGPRs(STM));
746 CreateExpr(
alignTo(std::max(1,
Info.NumVGPR), 4) / 4 - 1);
748 ProgInfo.
NumSGPR = CreateExpr(
Info.NumExplicitSGPR);
753 CreateExpr(
Info.HasDynamicallySizedStack ||
Info.HasRecursion);
755 const uint64_t MaxScratchPerWorkitem =
758 if (TryGetMCExprValue(ProgInfo.
ScratchSize, ScratchSize) &&
759 ScratchSize > MaxScratchPerWorkitem) {
779 if (TryGetMCExprValue(ProgInfo.
NumSGPR, NumSgpr) &&
780 NumSgpr > MaxAddressableNumSGPRs) {
787 ProgInfo.
NumSGPR = CreateExpr(MaxAddressableNumSGPRs - 1);
798 unsigned WaveDispatchNumSGPR = 0, WaveDispatchNumVGPR = 0;
807 unsigned LastEna = 0;
820 assert((InputEna || InputAddr) &&
821 "PSInputAddr and PSInputEnable should "
822 "never both be 0 for AMDGPU_PS shaders");
832 unsigned PSArgCount = 0;
833 unsigned IntermediateVGPR = 0;
834 for (
auto &Arg :
F.args()) {
835 unsigned NumRegs = (
DL.getTypeSizeInBits(Arg.getType()) + 31) / 32;
836 if (Arg.hasAttribute(Attribute::InReg)) {
837 WaveDispatchNumSGPR += NumRegs;
844 if (IsPixelShader && PSArgCount < 16) {
845 if ((1 << PSArgCount) & InputAddr) {
846 if (PSArgCount < LastEna)
847 WaveDispatchNumVGPR += NumRegs;
849 IntermediateVGPR += NumRegs;
855 if (IntermediateVGPR) {
856 WaveDispatchNumVGPR += IntermediateVGPR;
857 IntermediateVGPR = 0;
859 WaveDispatchNumVGPR += NumRegs;
864 {ProgInfo.
NumSGPR, CreateExpr(WaveDispatchNumSGPR)}, Ctx);
867 {ProgInfo.
NumVGPR, CreateExpr(WaveDispatchNumVGPR)}, Ctx);
877 {ProgInfo.
NumSGPR, CreateExpr(1ul),
881 {ProgInfo.
NumVGPR, CreateExpr(1ul),
889 if (TryGetMCExprValue(ProgInfo.
NumSGPR, NumSgpr) &&
890 NumSgpr > MaxAddressableNumSGPRs) {
895 NumSgpr, MaxAddressableNumSGPRs,
898 ProgInfo.
NumSGPR = CreateExpr(MaxAddressableNumSGPRs);
928 auto GetNumGPRBlocks = [&CreateExpr, &Ctx](
const MCExpr *NumGPR,
930 const MCExpr *OneConst = CreateExpr(1ul);
931 const MCExpr *GranuleConst = CreateExpr(Granule);
934 const MCExpr *AlignToGPR =
958 unsigned LDSAlignShift;
972 alignTo(ProgInfo.
LDSSize, 1ULL << LDSAlignShift) >> LDSAlignShift;
975 auto DivideCeil = [&Ctx](
const MCExpr *Numerator,
const MCExpr *Denominator) {
982 unsigned ScratchAlignShift =
990 CreateExpr(1ULL << ScratchAlignShift));
998 unsigned TIDIGCompCnt = 0;
1042 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,
1043 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT);
1046 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
1047 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT);
1054 const auto [MinWEU, MaxWEU] =
1057 if (TryGetMCExprValue(ProgInfo.
Occupancy, Occupancy) && Occupancy < MinWEU) {
1059 F,
F.getSubprogram(),
1060 "failed to meet occupancy target given by 'amdgpu-waves-per-eu' in "
1062 F.getName() +
"': desired occupancy was " +
Twine(MinWEU) +
1063 ", final occupancy is " +
Twine(Occupancy));
1064 F.getContext().diagnose(Diag);
1070 default: [[fallthrough]];
1096 auto EmitResolvedOrExpr = [
this](
const MCExpr *
Value,
unsigned Size) {
1098 if (
Value->evaluateAsAbsolute(Val))
1118 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.
ScratchBlocks,
1122 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.
ScratchBlocks,
1126 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.
ScratchBlocks,
1137 SetBits(CurrentProgramInfo.
VGPRBlocks, 0x3F, 0),
1138 SetBits(CurrentProgramInfo.
SGPRBlocks, 0x0F, 6),
1140 EmitResolvedOrExpr(GPRBlocks, 4);
1146 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.
ScratchBlocks,
1150 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.
ScratchBlocks,
1154 EmitResolvedOrExpr(SetBits(CurrentProgramInfo.
ScratchBlocks,
1164 : CurrentProgramInfo.LDSBlocks;
1182 if (ST.hasIEEEMode())
1195 (
unsigned)(CurrentProgramInfo.
LdsSize *
1212 MD->setNumUsedVgprs(
1218 MD->setNumUsedAgprs(
CC, getMCExprValue(CurrentProgramInfo.
NumAccVGPR, Ctx));
1221 MD->setNumUsedSgprs(
1223 if (MD->getPALMajorVersion() < 3) {
1228 if (getMCExprValue(CurrentProgramInfo.
ScratchBlocks, Ctx) > 0)
1232 MD->setHwStage(
CC,
".debug_mode", (
bool)CurrentProgramInfo.
DebugMode);
1233 MD->setHwStage(
CC,
".scratch_en",
1234 (
bool)getMCExprValue(CurrentProgramInfo.
ScratchEnable, Ctx));
1244 : CurrentProgramInfo.LDSBlocks;
1245 if (MD->getPALMajorVersion() < 3) {
1251 const unsigned ExtraLdsDwGranularity =
1253 MD->setGraphicsRegisters(
1254 ".ps_extra_lds_size",
1255 (
unsigned)(ExtraLDSSize * ExtraLdsDwGranularity *
sizeof(
uint32_t)));
1259 ".persp_sample_ena",
".persp_center_ena",
1260 ".persp_centroid_ena",
".persp_pull_model_ena",
1261 ".linear_sample_ena",
".linear_center_ena",
1262 ".linear_centroid_ena",
".line_stipple_tex_ena",
1263 ".pos_x_float_ena",
".pos_y_float_ena",
1264 ".pos_z_float_ena",
".pos_w_float_ena",
1265 ".front_face_ena",
".ancillary_ena",
1266 ".sample_coverage_ena",
".pos_fixed_pt_ena"};
1270 MD->setGraphicsRegisters(
".spi_ps_input_ena",
Field,
1271 (
bool)((PSInputEna >>
Idx) & 1));
1272 MD->setGraphicsRegisters(
".spi_ps_input_addr",
Field,
1273 (
bool)((PSInputAddr >>
Idx) & 1));
1279 if (MD->getPALMajorVersion() < 3 && STM.
isWave32())
1283void AMDGPUAsmPrinter::emitPALFunctionMetadata(
const MachineFunction &MF) {
1287 MD->setFunctionScratchSize(FnName, MFI.
getStackSize());
1291 if (MD->getPALMajorVersion() < 3) {
1302 MD->setFunctionLdsSize(FnName, CurrentProgramInfo.
LDSSize);
1303 MD->setFunctionNumUsedVgprs(
1305 MD->setFunctionNumUsedSgprs(
1372 if (STM.isXNACKEnabled())
1375 Align MaxKernArgAlign;
1380 getMCExprValue(CurrentProgramInfo.
ScratchSize, Ctx);
1395 if (ExtraCode && ExtraCode[0]) {
1396 if (ExtraCode[1] != 0)
1399 switch (ExtraCode[0]) {
1413 }
else if (MO.
isImm()) {
1414 int64_t Val = MO.
getImm();
1417 }
else if (isUInt<16>(Val)) {
1419 }
else if (isUInt<32>(Val)) {
1435void AMDGPUAsmPrinter::emitResourceUsageRemarks(
1441 const char *
Name =
"kernel-resource-usage";
1442 const char *Indent =
" ";
1449 auto EmitResourceUsageRemark = [&](
StringRef RemarkName,
1454 std::string LabelStr = RemarkLabel.str() +
": ";
1455 if (RemarkName !=
"FunctionName")
1456 LabelStr = Indent + LabelStr;
1472 EmitResourceUsageRemark(
"FunctionName",
"Function Name",
1474 EmitResourceUsageRemark(
"NumSGPR",
"SGPRs",
1475 getMCExprValue(CurrentProgramInfo.
NumSGPR, MCCtx));
1476 EmitResourceUsageRemark(
1478 getMCExprValue(CurrentProgramInfo.
NumArchVGPR, MCCtx));
1480 EmitResourceUsageRemark(
1482 getMCExprValue(CurrentProgramInfo.
NumAccVGPR, MCCtx));
1484 EmitResourceUsageRemark(
1485 "ScratchSize",
"ScratchSize [bytes/lane]",
1486 getMCExprValue(CurrentProgramInfo.
ScratchSize, MCCtx));
1490 EmitResourceUsageRemark(
"DynamicStack",
"Dynamic Stack", DynamicStackStr);
1491 EmitResourceUsageRemark(
"Occupancy",
"Occupancy [waves/SIMD]",
1492 getMCExprValue(CurrentProgramInfo.
Occupancy, MCCtx));
1493 EmitResourceUsageRemark(
"SGPRSpill",
"SGPRs Spill",
1495 EmitResourceUsageRemark(
"VGPRSpill",
"VGPRs Spill",
1497 if (isModuleEntryFunction)
1498 EmitResourceUsageRemark(
"BytesLDS",
"LDS Size [bytes/block]",
MachineBasicBlock MachineBasicBlock::iterator DebugLoc DL
LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUAsmPrinter()
static void EmitPALMetadataCommon(AMDGPUPALMetadata *MD, const SIProgramInfo &CurrentProgramInfo, CallingConv::ID CC, const GCNSubtarget &ST)
static unsigned getRsrcReg(CallingConv::ID CallConv)
static amd_element_byte_size_t getElementByteSizeValue(unsigned Size)
static uint32_t getFPMode(SIModeRegisterDefaults Mode)
static AsmPrinter * createAMDGPUAsmPrinterPass(TargetMachine &tm, std::unique_ptr< MCStreamer > &&Streamer)
AMDGPU Assembly printer class.
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
Analyzes how many registers and other resources are used by functions.
AMDHSA kernel descriptor definitions.
#define AMDHSA_BITS_GET(SRC, MSK)
amd_element_byte_size_t
The values used to define the number of bytes to use for the swizzle element size.
#define AMD_HSA_BITS_SET(dst, mask, val)
@ AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID
@ AMD_CODE_PROPERTY_PRIVATE_ELEMENT_SIZE
@ AMD_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR
@ AMD_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR
@ AMD_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER
@ AMD_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR
@ AMD_CODE_PROPERTY_IS_XNACK_SUPPORTED
@ AMD_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT
@ AMD_CODE_PROPERTY_IS_PTR64
@ AMD_CODE_PROPERTY_IS_DYNAMIC_CALLSTACK
Analysis containing CSE Info
#define LLVM_EXTERNAL_VISIBILITY
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
AMD GCN specific subclass of TargetSubtarget.
const HexagonInstrInfo * TII
const char LLVMTargetMachineRef TM
R600 Assembly printer class.
#define R_00B028_SPI_SHADER_PGM_RSRC1_PS
#define R_0286E8_SPI_TMPRING_SIZE
#define S_00B84C_SCRATCH_EN(x)
#define FP_ROUND_MODE_DP(x)
#define FP_ROUND_ROUND_TO_NEAREST
#define R_0286D0_SPI_PS_INPUT_ADDR
#define R_00B860_COMPUTE_TMPRING_SIZE
#define R_00B428_SPI_SHADER_PGM_RSRC1_HS
#define R_00B328_SPI_SHADER_PGM_RSRC1_ES
#define R_00B528_SPI_SHADER_PGM_RSRC1_LS
#define R_0286CC_SPI_PS_INPUT_ENA
#define R_00B128_SPI_SHADER_PGM_RSRC1_VS
#define FP_DENORM_MODE_DP(x)
#define R_00B848_COMPUTE_PGM_RSRC1
#define FP_ROUND_MODE_SP(x)
#define FP_DENORM_MODE_SP(x)
#define R_00B228_SPI_SHADER_PGM_RSRC1_GS
#define S_00B02C_EXTRA_LDS_SIZE(x)
#define R_00B84C_COMPUTE_PGM_RSRC2
#define R_00B02C_SPI_SHADER_PGM_RSRC2_PS
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
void emitFunctionEntryLabel() override
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
const MCSubtargetInfo * getGlobalSTI() const
void emitImplicitDef(const MachineInstr *MI) const override
Targets can override this to customize the output of IMPLICIT_DEF instructions in verbose mode.
std::vector< std::string > DisasmLines
void emitStartOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the start of their fi...
StringRef getPassName() const override
getPassName - Return a nice clean name for a pass.
std::vector< std::string > HexLines
bool IsTargetStreamerInitialized
void emitGlobalVariable(const GlobalVariable *GV) override
Emit the specified global variable to the .s file.
void getAnalysisUsage(AnalysisUsage &AU) const override
Record analysis usage.
bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &O) override
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
bool runOnMachineFunction(MachineFunction &MF) override
Emit the specified function out to the OutStreamer.
void emitFunctionBodyEnd() override
Targets can override this to emit stuff after the last basic block in the function.
bool doFinalization(Module &M) override
Shut down the asmprinter.
void emitEndOfAsmFile(Module &M) override
This virtual method can be overridden by targets that want to emit something at the end of their file...
AMDGPUAsmPrinter(TargetMachine &TM, std::unique_ptr< MCStreamer > Streamer)
bool doInitialization(Module &M) override
Set up the AsmPrinter when we are working on a new module.
void emitFunctionBodyStart() override
Targets can override this to emit stuff before the first basic block in the function.
void emitBasicBlockStart(const MachineBasicBlock &MBB) override
Targets can override this to emit stuff at the start of a basic block.
AMDGPUTargetStreamer * getTargetStreamer() const
static void printRegOperand(unsigned RegNo, raw_ostream &O, const MCRegisterInfo &MRI)
uint32_t getLDSSize() const
bool isMemoryBound() const
bool needsWaveLimiter() const
bool isEntryFunction() const
bool isModuleEntryFunction() const
unsigned getAddressableLocalMemorySize() const
unsigned getKernArgSegmentSize(const Function &F, Align &MaxAlign) const
unsigned getWavefrontSize() const
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
virtual bool EmitISAVersion()
void initializeTargetID(const MCSubtargetInfo &STI)
virtual void EmitAMDKernelCodeT(const amd_kernel_code_t &Header)
virtual bool EmitCodeEnd(const MCSubtargetInfo &STI)
virtual void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type)
virtual void EmitDirectiveAMDGCNTarget()
virtual void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
virtual bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled)
static const AMDGPUVariadicMCExpr * createMax(ArrayRef< const MCExpr * > Args, MCContext &Ctx)
static const AMDGPUVariadicMCExpr * createAlignTo(const MCExpr *Value, const MCExpr *Align, MCContext &Ctx)
static const AMDGPUVariadicMCExpr * createTotalNumVGPR(const MCExpr *NumAGPR, const MCExpr *NumVGPR, MCContext &Ctx)
static const AMDGPUVariadicMCExpr * createOccupancy(unsigned InitOcc, const MCExpr *NumSGPRs, const MCExpr *NumVGPRs, const GCNSubtarget &STM, MCContext &Ctx)
Mimics GCNSubtarget::computeOccupancy for MCExpr.
static const AMDGPUVariadicMCExpr * createExtraSGPRs(const MCExpr *VCCUsed, const MCExpr *FlatScrUsed, bool XNACKUsed, MCContext &Ctx)
Allow delayed MCExpr resolve of ExtraSGPRs (in case VCCUsed or FlatScrUsed are unresolvable but neede...
void setXnackSetting(TargetIDSetting NewXnackSetting)
Sets xnack setting to NewXnackSetting.
Represent the analysis usage information of a pass.
AnalysisUsage & addRequired()
AnalysisUsage & addPreserved()
Add the specified Pass class to the set of analyses preserved by this pass.
This class represents an incoming formal argument to a Function.
This class is intended to be used as a driving class for all asm writers.
const TargetLoweringObjectFile & getObjFileLowering() const
Return information about object file lowering.
MCSymbol * getSymbol(const GlobalValue *GV) const
virtual void emitGlobalVariable(const GlobalVariable *GV)
Emit the specified global variable to the .s file.
TargetMachine & TM
Target machine description.
MachineFunction * MF
The current machine function.
virtual void SetupMachineFunction(MachineFunction &MF)
This should be called when a new MachineFunction is being processed from runOnMachineFunction.
void emitFunctionBody()
This method emits the body and trailer for a function.
virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const
Return true if the basic block has exactly one predecessor and the control transfer mechanism between...
bool doInitialization(Module &M) override
Set up the AsmPrinter when we are working on a new module.
virtual void emitLinkage(const GlobalValue *GV, MCSymbol *GVSym) const
This emits linkage information about GVSym based on GV, if this is supported by the target.
void getAnalysisUsage(AnalysisUsage &AU) const override
Record analysis usage.
unsigned getFunctionNumber() const
Return a unique ID for the current function.
MachineOptimizationRemarkEmitter * ORE
Optimization remark emitter.
MCContext & OutContext
This is the context for the output file that we are streaming.
bool doFinalization(Module &M) override
Shut down the asmprinter.
virtual void emitBasicBlockStart(const MachineBasicBlock &MBB)
Targets can override this to emit stuff at the start of a basic block.
void emitVisibility(MCSymbol *Sym, unsigned Visibility, bool IsDefinition=true) const
This emits visibility information about symbol, if this is supported by the target.
std::unique_ptr< MCStreamer > OutStreamer
This is the MCStreamer object for the file we are generating.
bool isVerbose() const
Return true if assembly output should contain comments.
void getNameWithPrefix(SmallVectorImpl< char > &Name, const GlobalValue *GV) const
virtual void emitFunctionEntryLabel()
EmitFunctionEntryLabel - Emit the label that is the entrypoint for the function.
virtual bool PrintAsmOperand(const MachineInstr *MI, unsigned OpNo, const char *ExtraCode, raw_ostream &OS)
Print the specified operand of MI, an INLINEASM instruction, using the specified assembler variant.
A parsed version of the target data layout string in and methods for querying it.
Diagnostic information for optimization failures.
Diagnostic information for stack size etc.
DISubprogram * getSubprogram() const
Get the attached subprogram.
CallingConv::ID getCallingConv() const
getCallingConv()/setCallingConv(CC) - These method get and set the calling convention of this functio...
LLVMContext & getContext() const
getContext - Return a reference to the LLVMContext associated with this function.
unsigned getMinNumSGPRs(unsigned WavesPerEU) const
bool hasGFX90AInsts() const
unsigned computeOccupancy(const Function &F, unsigned LDSSize=0, unsigned NumSGPRs=0, unsigned NumVGPRs=0) const
Return occupancy for the given function.
const SIInstrInfo * getInstrInfo() const override
bool hasSGPRInitBug() const
bool isTgSplitEnabled() const
unsigned getMinNumVGPRs(unsigned WavesPerEU) const
bool isCuModeEnabled() const
const AMDGPU::IsaInfo::AMDGPUTargetID & getTargetID() const
bool isTrapHandlerEnabled() const
unsigned getMaxNumUserSGPRs() const
Generation getGeneration() const
unsigned getAddressableNumSGPRs() const
unsigned getMaxWaveScratchSize() const
bool hasKernargSegmentPtr() const
bool hasDispatchID() const
bool hasPrivateSegmentBuffer() const
bool hasDispatchPtr() const
bool hasFlatScratchInit() const
MaybeAlign getAlign() const
Returns the alignment of the given variable or function.
VisibilityTypes getVisibility() const
bool isDeclaration() const
Return true if the primary definition of this global value is outside of the current translation unit...
unsigned getAddressSpace() const
Module * getParent()
Get the module that this global value is contained inside of...
Type * getValueType() const
const Constant * getInitializer() const
getInitializer - Return the initializer for this global variable.
bool hasInitializer() const
Definitions have initializers, declarations don't.
This is an important class for using LLVM in a threaded context.
void diagnose(const DiagnosticInfo &DI)
Report a message to the currently installed diagnostic handler.
const DiagnosticHandler * getDiagHandlerPtr() const
getDiagHandlerPtr - Returns const raw pointer of DiagnosticHandler set by setDiagnosticHandler.
MCCodeEmitter * getEmitterPtr() const
static const MCBinaryExpr * createAnd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createLOr(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createGT(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createDiv(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createShl(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
Context object for machine code objects.
void reportError(SMLoc L, const Twine &Msg)
Base class for the full range of assembler expressions which are needed for parsing.
MCContext & getContext() const
This represents a section on linux, lots of unix variants and some bare metal systems.
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
bool isDefined() const
isDefined - Check if this symbol is defined (i.e., it has an address).
StringRef getName() const
getName - Get the symbol name.
bool isVariable() const
isVariable - Check if this is a variable symbol.
void redefineIfPossible()
Prepare this symbol to be redefined.
MCStreamer & getStreamer()
static const MCUnaryExpr * createNot(const MCExpr *Expr, MCContext &Ctx, SMLoc Loc=SMLoc())
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
uint64_t getStackSize() const
Return the number of bytes that must be allocated to hold all of the fixed size frame objects.
const TargetSubtargetInfo & getSubtarget() const
getSubtarget - Return the subtarget for which this machine code is being compiled.
StringRef getName() const
getName - Return the name of the corresponding LLVM function.
void setAlignment(Align A)
setAlignment - Set the alignment of the function.
MachineFrameInfo & getFrameInfo()
getFrameInfo - Return the frame info object for the current function.
MCContext & getContext() const
Function & getFunction()
Return the LLVM function that this machine code represents.
Ty * getInfo()
getInfo - Keep track of various per-function pieces of information for backends that would like to do...
const MachineBasicBlock & front() const
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
bool isReg() const
isReg - Tests if this is a MO_Register operand.
bool isImm() const
isImm - Tests if this is a MO_Immediate operand.
Register getReg() const
getReg - Returns the register number.
A Module instance is used to store all the information related to an LLVM module.
const DataLayout & getDataLayout() const
Get the data layout for the module's target platform.
Wrapper class representing virtual and physical registers.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
unsigned getNumSpilledVGPRs() const
unsigned getNumSpilledSGPRs() const
GCNUserSGPRUsageInfo & getUserSGPRInfo()
unsigned getMaxWavesPerEU() const
bool hasWorkGroupIDZ() const
bool hasWorkGroupIDY() const
SIModeRegisterDefaults getMode() const
bool hasWorkGroupInfo() const
bool hasWorkItemIDY() const
bool hasWorkGroupIDX() const
unsigned getNumKernargPreloadedSGPRs() const
unsigned getNumUserSGPRs() const
unsigned getPSInputAddr() const
bool hasWorkItemIDZ() const
unsigned getPSInputEnable() const
Represents a location in source code.
SmallString - A SmallString is just a SmallVector with methods and accessors that make it work better...
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
StringRef - Represent a constant reference to a string, i.e.
std::string str() const
str - Get the contents as an std::string.
Primary interface to the complete machine description for the target machine.
const Triple & getTargetTriple() const
const MCSubtargetInfo * getMCSubtargetInfo() const
const STC & getSubtarget(const Function &F) const
This method returns a pointer to the specified type of TargetSubtargetInfo.
virtual const TargetRegisterInfo * getRegisterInfo() const
getRegisterInfo - If register information is available, return it.
OSType getOS() const
Get the parsed operating system type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
LLVM Value Representation.
StringRef getName() const
Return a constant reference to the value's name.
This class implements an extremely fast bulk output stream that can only output to a stream.
A raw_ostream that writes to an SmallVector or SmallString.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ LOCAL_ADDRESS
Address space for local memory.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
@ FIXED_NUM_SGPRS_FOR_INIT_BUG
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
IsaVersion getIsaVersion(StringRef GPU)
bool isCompute(CallingConv::ID cc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
bool isGFX90A(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
bool isShader(CallingConv::ID cc)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
@ SPIR_KERNEL
Used for SPIR kernel functions.
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
DiagnosticInfoOptimizationBase::Argument NV
This is an optimization pass for GlobalISel generic memory operations.
auto size(R &&Range, std::enable_if_t< std::is_base_of< std::random_access_iterator_tag, typename std::iterator_traits< decltype(Range.begin())>::iterator_category >::value, void > *=nullptr)
Get the size of a range.
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
auto enumerate(FirstRange &&First, RestRanges &&...Rest)
Given two or more input ranges, returns a new range whose values are are tuples (A,...
static StringRef getCPU(StringRef CPU)
Processes a CPU name.
Target & getTheR600Target()
The target for R600 GPUs.
AsmPrinter * createR600AsmPrinterPass(TargetMachine &TM, std::unique_ptr< MCStreamer > &&Streamer)
unsigned Log2_32(uint32_t Value)
Return the floor log base 2 of the specified value, -1 if the value is zero.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
format_object< Ts... > format(const char *Fmt, const Ts &... Vals)
These are helper functions used to produce formatted output.
Target & getTheGCNTarget()
The target for GCN GPUs.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
OutputIt move(R &&Range, OutputIt Out)
Provide wrappers to std::move which take ranges instead of having to pass begin/end explicitly.
unsigned Log2(Align A)
Returns the log2 of the alignment.
Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
Implement std::hash so that hash_code can be used in STL containers.
AMD Kernel Code Object (amd_kernel_code_t).
uint16_t workitem_vgpr_count
Number of vector registers used by each work-item.
uint32_t code_properties
Code properties.
uint8_t kernarg_segment_alignment
The maximum byte alignment of variables used by the kernel in the specified memory segment.
uint32_t workgroup_group_segment_byte_size
The amount of group segment memory required by a work-group in bytes.
uint16_t wavefront_sgpr_count
Number of scalar registers used by a wavefront.
uint32_t workitem_private_segment_byte_size
The amount of memory required for the combined private, spill and arg segments for a work-item in byt...
uint64_t kernarg_segment_byte_size
The size in bytes of the kernarg segment that holds the values of the arguments to the kernel.
uint64_t compute_pgm_resource_registers
Shader program settings for CS.
const SIFunctionResourceInfo & getResourceInfo(const Function *F) const
const MCExpr * compute_pgm_rsrc2
const MCExpr * kernarg_size
const MCExpr * kernarg_preload
const MCExpr * compute_pgm_rsrc3
const MCExpr * private_segment_fixed_size
const MCExpr * compute_pgm_rsrc1
const MCExpr * group_segment_fixed_size
const MCExpr * kernel_code_properties
This struct is a compact representation of a valid (non-zero power of two) alignment.
virtual bool isAnalysisRemarkEnabled(StringRef PassName) const
Return true if analysis remarks are enabled, override to provide different implementation.
Track resource usage for kernels / entry functions.
const MCExpr * ComputePGMRSrc3GFX90A
const MCExpr * NumArchVGPR
const MCExpr * VGPRBlocks
const MCExpr * ScratchBlocks
uint64_t getComputePGMRSrc1(const GCNSubtarget &ST) const
Compute the value of the ComputePGMRsrc1 register.
uint32_t TrapHandlerEnable
const MCExpr * ScratchEnable
uint64_t getComputePGMRSrc2() const
Compute the value of the ComputePGMRsrc2 register.
const MCExpr * AccumOffset
const MCExpr * NumAccVGPR
const MCExpr * DynamicCallStack
const MCExpr * SGPRBlocks
const MCExpr * NumVGPRsForWavesPerEU
const MCExpr * ScratchSize
const MCExpr * NumSGPRsForWavesPerEU
void reset(const MachineFunction &MF)
uint64_t getPGMRSrc1(CallingConv::ID CC, const GCNSubtarget &ST) const
static void RegisterAsmPrinter(Target &T, Target::AsmPrinterCtorTy Fn)
RegisterAsmPrinter - Register an AsmPrinter implementation for the given target.