13#ifndef LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
14#define LLVM_LIB_TARGET_AMDGPU_SIMACHINEFUNCTIONINFO_H
32class MachineFrameInfo;
34class SIMachineFunctionInfo;
36class TargetRegisterClass;
97 std::optional<unsigned>
Mask;
139 if (
YamlIO.outputting()) {
141 YamlIO.mapRequired(
"reg",
A.RegisterName);
143 YamlIO.mapRequired(
"offset",
A.StackOffset);
145 auto Keys =
YamlIO.keys();
148 YamlIO.mapRequired(
"reg",
A.RegisterName);
150 YamlIO.mapRequired(
"offset",
A.StackOffset);
152 YamlIO.setError(
"missing required key 'reg' or 'offset'");
154 YamlIO.mapOptional(
"mask",
A.Mask);
156 static const bool flow =
true;
198 YamlIO.mapOptional(
"privateSegmentWaveByteOffset",
246 YamlIO.mapOptional(
"dx10-clamp",
Mode.DX10Clamp,
true);
247 YamlIO.mapOptional(
"fp32-input-denormals",
Mode.FP32InputDenormals,
true);
248 YamlIO.mapOptional(
"fp32-output-denormals",
Mode.FP32OutputDenormals,
true);
249 YamlIO.mapOptional(
"fp64-fp16-input-denormals",
Mode.FP64FP16InputDenormals,
true);
250 YamlIO.mapOptional(
"fp64-fp16-output-denormals",
Mode.FP64FP16OutputDenormals,
true);
328 YamlIO.mapOptional(
"highBitsOf32BitAddress",
384 Register ScratchRSrcReg = AMDGPU::PRIVATE_RSRC_REG;
388 Register FrameOffsetReg = AMDGPU::FP_REG;
393 Register StackPtrOffsetReg = AMDGPU::SP_REG;
403 unsigned PSInputAddr = 0;
404 unsigned PSInputEnable = 0;
415 unsigned BytesInStackArgArea = 0;
417 bool ReturnsVoid =
true;
421 std::pair<unsigned, unsigned> FlatWorkGroupSizes = {0, 0};
425 std::pair<unsigned, unsigned> WavesPerEU = {0, 0};
427 const AMDGPUGWSResourcePseudoSourceValue GWSResourcePSV;
430 SmallVector<unsigned> MaxNumWorkGroups = {0, 0, 0};
433 unsigned NumUserSGPRs = 0;
434 unsigned NumSystemSGPRs = 0;
436 bool HasSpilledSGPRs =
false;
437 bool HasSpilledVGPRs =
false;
438 bool HasNonSpillStackObjects =
false;
439 bool IsStackRealigned =
false;
441 unsigned NumSpilledSGPRs = 0;
442 unsigned NumSpilledVGPRs = 0;
446 GCNUserSGPRUsageInfo UserSGPRInfo;
449 bool WorkGroupIDX : 1;
450 bool WorkGroupIDY : 1;
451 bool WorkGroupIDZ : 1;
452 bool WorkGroupInfo : 1;
453 bool LDSKernelId : 1;
454 bool PrivateSegmentWaveByteOffset : 1;
456 bool WorkItemIDX : 1;
457 bool WorkItemIDY : 1;
458 bool WorkItemIDZ : 1;
462 bool ImplicitArgPtr : 1;
464 bool MayNeedAGPRs : 1;
471 unsigned HighBitsOf32BitAddress;
474 IndexedMap<uint8_t, VirtReg2IndexFunctor> VRegFlags;
479 mutable std::optional<bool> UsesAGPRs;
486 void MRI_NoteNewVirtualRegister(
Register Reg)
override;
487 void MRI_NoteCloneVirtualRegister(
Register NewReg,
Register SrcReg)
override;
500 SGPRSpillsToVirtualVGPRLanes;
504 SGPRSpillsToPhysicalVGPRLanes;
505 unsigned NumVirtualVGPRSpillLanes = 0;
506 unsigned NumPhysicalVGPRSpillLanes = 0;
525 using PrologEpilogSGPRSpill =
526 std::pair<Register, PrologEpilogSGPRSaveRestoreInfo>;
546 std::optional<int> ScavengeFI;
555 bool IsPrologEpilog);
559 return VGPRForAGPRCopy;
563 VGPRForAGPRCopy = NewVGPRForAGPRCopy;
588 auto I = SGPRSpillsToVirtualVGPRLanes.
find(FrameIndex);
589 return (
I == SGPRSpillsToVirtualVGPRLanes.
end())
601 is_sorted(PrologEpilogSGPRSpills, [](
const auto &
LHS,
const auto &
RHS) {
602 return LHS.first <
RHS.first;
604 return PrologEpilogSGPRSpills;
617 PrologEpilogSGPRSpills.
insert(
619 PrologEpilogSGPRSpills,
Reg,
620 [](
const auto &
LHS,
const auto &
RHS) {
return LHS <
RHS.first; }),
621 std::make_pair(
Reg, SI));
627 auto I =
find_if(PrologEpilogSGPRSpills,
628 [&
Reg](
const auto &Spill) {
return Spill.first ==
Reg; });
629 return I != PrologEpilogSGPRSpills.
end();
634 auto I =
find_if(PrologEpilogSGPRSpills,
635 [&
Reg](
const auto &Spill) {
return Spill.first ==
Reg; });
636 if (
I != PrologEpilogSGPRSpills.
end() &&
638 return I->second.getReg();
640 return AMDGPU::NoRegister;
645 for (
const auto &SI : PrologEpilogSGPRSpills) {
653 return find_if(PrologEpilogSGPRSpills,
656 return SI.second.getKind() ==
658 SI.second.getIndex() == FI;
659 }) != PrologEpilogSGPRSpills.
end();
664 auto I =
find_if(PrologEpilogSGPRSpills,
665 [&
Reg](
const auto &Spill) {
return Spill.first ==
Reg; });
673 auto I = SGPRSpillsToPhysicalVGPRLanes.
find(FrameIndex);
674 return (
I == SGPRSpillsToPhysicalVGPRLanes.
end())
681 if (VRegFlags.inBounds(
Reg))
682 VRegFlags[
Reg] |= Flag;
686 if (
Reg.isPhysical())
689 return VRegFlags.inBounds(
Reg) && VRegFlags[
Reg] & Flag;
715 auto I = VGPRToAGPRSpills.
find(FrameIndex);
716 return (
I == VGPRToAGPRSpills.
end()) ? (
MCPhysReg)AMDGPU::NoRegister
717 :
I->second.Lanes[Lane];
721 auto I = VGPRToAGPRSpills.
find(FrameIndex);
722 if (
I != VGPRToAGPRSpills.
end())
723 I->second.IsDead =
true;
731 bool SpillToPhysVGPRLane =
false,
732 bool IsPrologEpilog =
false);
738 bool ResetSGPRSpillStackIDs);
744 return BytesInStackArgArea;
748 BytesInStackArgArea = Bytes;
762 unsigned AllocSizeDWord,
int KernArgIdx,
776 return ArgInfo.WorkGroupIDX.getRegister();
782 return ArgInfo.WorkGroupIDY.getRegister();
788 return ArgInfo.WorkGroupIDZ.getRegister();
794 return ArgInfo.WorkGroupInfo.getRegister();
813 ArgInfo.PrivateSegmentWaveByteOffset
816 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
836 return WorkGroupInfo;
840 return PrivateSegmentWaveByteOffset;
856 return ImplicitArgPtr;
867 std::tuple<const ArgDescriptor *, const TargetRegisterClass *, LLT>
873 auto Arg = std::get<0>(
ArgInfo.getPreloadedValue(
Value));
874 return Arg ? Arg->getRegister() :
MCRegister();
884 return HighBitsOf32BitAddress;
892 return NumUserSGPRs + NumSystemSGPRs;
896 return UserSGPRInfo.getNumKernargPreloadSGPRs();
900 return ArgInfo.PrivateSegmentWaveByteOffset.getRegister();
906 return ScratchRSrcReg;
910 assert(
Reg != 0 &&
"Should never be unset");
911 ScratchRSrcReg =
Reg;
915 return FrameOffsetReg;
919 assert(
Reg != 0 &&
"Should never be unset");
920 FrameOffsetReg =
Reg;
924 assert(
Reg != 0 &&
"Should never be unset");
925 StackPtrOffsetReg =
Reg;
935 return StackPtrOffsetReg;
941 return ArgInfo.QueuePtr.getRegister();
945 return ArgInfo.ImplicitBufferPtr.getRegister();
949 return HasSpilledSGPRs;
953 HasSpilledSGPRs = Spill;
957 return HasSpilledVGPRs;
961 HasSpilledVGPRs = Spill;
965 return HasNonSpillStackObjects;
969 HasNonSpillStackObjects = StackObject;
973 return IsStackRealigned;
977 IsStackRealigned = Realigned;
981 return NumSpilledSGPRs;
985 return NumSpilledVGPRs;
989 NumSpilledSGPRs += num;
993 NumSpilledVGPRs += num;
1001 return PSInputEnable;
1005 return PSInputAddr & (1 <<
Index);
1009 PSInputAddr |= 1 <<
Index;
1013 PSInputEnable |= 1 <<
Index;
1021 ReturnsVoid =
Value;
1027 return FlatWorkGroupSizes;
1032 return FlatWorkGroupSizes.first;
1037 return FlatWorkGroupSizes.second;
1048 return WavesPerEU.first;
1053 return WavesPerEU.second;
1058 return &GWSResourcePSV;
1068 return (Occupancy < 4) ? Occupancy : 4;
1074 if (Occupancy > Limit)
1079 if (Occupancy < Limit)
1085 return MayNeedAGPRs;
Provides AMDGPU specific target descriptions.
The AMDGPU TargetMachine interface definition for hw codegen targets.
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
AMD GCN specific subclass of TargetSubtarget.
unsigned const TargetRegisterInfo * TRI
Promote Memory to Register
const char LLVMTargetMachineRef TM
static cl::opt< RegAllocEvictionAdvisorAnalysis::AdvisorMode > Mode("regalloc-enable-advisor", cl::Hidden, cl::init(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default), cl::desc("Enable regalloc advisor mode"), cl::values(clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Default, "default", "Default"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Release, "release", "precompiled"), clEnumValN(RegAllocEvictionAdvisorAnalysis::AdvisorMode::Development, "development", "for training")))
Interface definition for SIInstrInfo.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
void printCustom(raw_ostream &OS) const override
Implement printing for PseudoSourceValue.
static bool classof(const PseudoSourceValue *V)
AMDGPUGWSResourcePseudoSourceValue(const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
bool isMemoryBound() const
bool needsWaveLimiter() const
bool isConstant(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue has a constant value.
AMDGPUPseudoSourceValue(unsigned Kind, const AMDGPUTargetMachine &TM)
bool mayAlias(const MachineFrameInfo *) const override
Return true if the memory pointed to by this PseudoSourceValue can ever alias an LLVM IR Value.
bool isAliased(const MachineFrameInfo *) const override
Test whether the memory pointed to by this PseudoSourceValue may also be pointed to by an LLVM IR Val...
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
Allocate memory in an ever growing pool, as if by bump-pointer.
iterator find(const_arg_type_t< KeyT > Val)
Lightweight error class with error context and mandatory checking.
Wrapper class representing physical registers. Should be passed by value.
The MachineFrameInfo class represents an abstract stack frame until prolog/epilog code is inserted.
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, Register R)
PrologEpilogSGPRSaveRestoreInfo(SGPRSaveKind K, int I)
SGPRSaveKind getKind() const
Special value supplied for machine level alias analysis.
Wrapper class representing virtual and physical registers.
This class keeps track of the SPI_SP_INPUT_ADDR config register, which tells the hardware which inter...
bool hasNonSpillStackObjects() const
ArrayRef< PrologEpilogSGPRSpill > getPrologEpilogSGPRSpills() const
const WWMSpillsMap & getWWMSpills() const
bool usesAGPRs(const MachineFunction &MF) const
bool isPSInputAllocated(unsigned Index) const
void getAllScratchSGPRCopyDstRegs(SmallVectorImpl< Register > &Regs) const
ArrayRef< MCPhysReg > getAGPRSpillVGPRs() const
void setSGPRForEXECCopy(Register Reg)
bool initializeBaseYamlFields(const yaml::SIMachineFunctionInfo &YamlMFI, const MachineFunction &MF, PerFunctionMIParsingState &PFS, SMDiagnostic &Error, SMRange &SourceRange)
unsigned getOccupancy() const
unsigned getNumPreloadedSGPRs() const
void setWorkItemIDY(ArgDescriptor Arg)
unsigned getNumSpilledVGPRs() const
bool hasLDSKernelId() const
void increaseOccupancy(const MachineFunction &MF, unsigned Limit)
void setWorkItemIDZ(ArgDescriptor Arg)
std::pair< unsigned, unsigned > getWavesPerEU() const
unsigned getMaxNumWorkGroupsZ() const
MCPhysReg getVGPRToAGPRSpill(int FrameIndex, unsigned Lane) const
unsigned getNumSpilledSGPRs() const
GCNUserSGPRUsageInfo & getUserSGPRInfo()
void allocateWWMSpill(MachineFunction &MF, Register VGPR, uint64_t Size=4, Align Alignment=Align(4))
Register addDispatchPtr(const SIRegisterInfo &TRI)
Register getLongBranchReservedReg() const
bool hasSpilledVGPRs() const
void setFlag(Register Reg, uint8_t Flag)
void setVGPRToAGPRSpillDead(int FrameIndex)
unsigned getMaxFlatWorkGroupSize() const
std::pair< unsigned, unsigned > getFlatWorkGroupSizes() const
Register getStackPtrOffsetReg() const
bool isStackRealigned() const
Register addFlatScratchInit(const SIRegisterInfo &TRI)
Register getScratchRSrcReg() const
Returns the physical register reserved for use as the resource descriptor for scratch accesses.
unsigned getMaxWavesPerEU() const
void setStackPtrOffsetReg(Register Reg)
Register addReservedUserSGPR()
Increment user SGPRs used for padding the argument list only.
ArrayRef< MCPhysReg > getVGPRSpillAGPRs() const
int getScavengeFI(MachineFrameInfo &MFI, const SIRegisterInfo &TRI)
Register addQueuePtr(const SIRegisterInfo &TRI)
bool hasWorkGroupIDZ() const
Register getQueuePtrUserSGPR() const
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToVirtualVGPRLanes(int FrameIndex) const
SIMachineFunctionInfo(const SIMachineFunctionInfo &MFI)=default
SmallVector< unsigned > getMaxNumWorkGroups() const
bool hasPrologEpilogSGPRSpillEntry(Register Reg) const
Register getGITPtrLoReg(const MachineFunction &MF) const
bool hasWorkGroupIDY() const
void setVGPRForAGPRCopy(Register NewVGPRForAGPRCopy)
bool allocateVGPRSpillToAGPR(MachineFunction &MF, int FI, bool isAGPRtoVGPR)
Reserve AGPRs or VGPRs to support spilling for FrameIndex FI.
Register addWorkGroupIDY()
void splitWWMSpillRegisters(MachineFunction &MF, SmallVectorImpl< std::pair< Register, int > > &CalleeSavedRegs, SmallVectorImpl< std::pair< Register, int > > &ScratchRegs) const
void setBytesInStackArgArea(unsigned Bytes)
SIModeRegisterDefaults getMode() const
Register getSGPRForEXECCopy() const
void setFrameOffsetReg(Register Reg)
ArrayRef< SIRegisterInfo::SpilledReg > getSGPRSpillToPhysicalVGPRLanes(int FrameIndex) const
Register addPrivateSegmentWaveByteOffset()
std::tuple< const ArgDescriptor *, const TargetRegisterClass *, LLT > getPreloadedValue(AMDGPUFunctionArgInfo::PreloadedValue Value) const
bool hasWorkGroupInfo() const
bool mayUseAGPRs(const Function &F) const
bool isCalleeSavedReg(const MCPhysReg *CSRegs, MCPhysReg Reg) const
bool hasWorkItemIDY() const
unsigned getMinFlatWorkGroupSize() const
void shiftSpillPhysVGPRsToLowestRange(MachineFunction &MF)
Register addLDSKernelId()
Register getVGPRForAGPRCopy() const
const GCNUserSGPRUsageInfo & getUserSGPRInfo() const
bool allocateSGPRSpillToVGPRLane(MachineFunction &MF, int FI, bool SpillToPhysVGPRLane=false, bool IsPrologEpilog=false)
void setPrivateSegmentWaveByteOffset(Register Reg)
unsigned getMinWavesPerEU() const
Register getFrameOffsetReg() const
void setLongBranchReservedReg(Register Reg)
bool hasWorkGroupIDX() const
const AMDGPUFunctionArgInfo & getArgInfo() const
unsigned getMaxNumWorkGroupsX() const
unsigned getBytesInStackArgArea() const
Register addKernargSegmentPtr(const SIRegisterInfo &TRI)
Register addDispatchID(const SIRegisterInfo &TRI)
void setHasSpilledVGPRs(bool Spill=true)
void setIfReturnsVoid(bool Value)
void limitOccupancy(unsigned Limit)
bool removeDeadFrameIndices(MachineFrameInfo &MFI, bool ResetSGPRSpillStackIDs)
If ResetSGPRSpillStackIDs is true, reset the stack ID from sgpr-spill to the default stack.
void markPSInputAllocated(unsigned Index)
void setWorkItemIDX(ArgDescriptor Arg)
MachineFunctionInfo * clone(BumpPtrAllocator &Allocator, MachineFunction &DestMF, const DenseMap< MachineBasicBlock *, MachineBasicBlock * > &Src2DstMBB) const override
Make a functionally equivalent copy of this MachineFunctionInfo in MF.
bool checkFlag(Register Reg, uint8_t Flag) const
void markPSInputEnabled(unsigned Index)
void addToSpilledVGPRs(unsigned num)
MCRegister getPreloadedReg(AMDGPUFunctionArgInfo::PreloadedValue Value) const
uint32_t get32BitAddressHighBits() const
unsigned getMinAllowedOccupancy() const
void setHasSpilledSGPRs(bool Spill=true)
bool checkIndexInPrologEpilogSGPRSpills(int FI) const
unsigned getNumKernargPreloadedSGPRs() const
Register addPrivateSegmentBuffer(const SIRegisterInfo &TRI)
bool hasWorkItemIDX() const
unsigned getNumUserSGPRs() const
const ReservedRegSet & getWWMReservedRegs() const
Register getImplicitBufferPtrUserSGPR() const
std::optional< int > getOptionalScavengeFI() const
Register addImplicitBufferPtr(const SIRegisterInfo &TRI)
AMDGPUFunctionArgInfo & getArgInfo()
const PrologEpilogSGPRSaveRestoreInfo & getPrologEpilogSGPRSaveRestoreInfo(Register Reg) const
void setHasNonSpillStackObjects(bool StackObject=true)
void setIsStackRealigned(bool Realigned=true)
unsigned getGITPtrHigh() const
void limitOccupancy(const MachineFunction &MF)
bool hasSpilledSGPRs() const
ArrayRef< Register > getSGPRSpillVGPRs() const
unsigned getPSInputAddr() const
SmallVectorImpl< MCRegister > * addPreloadedKernArg(const SIRegisterInfo &TRI, const TargetRegisterClass *RC, unsigned AllocSizeDWord, int KernArgIdx, int PaddingSGPRs)
void addToPrologEpilogSGPRSpills(Register Reg, PrologEpilogSGPRSaveRestoreInfo SI)
Register getScratchSGPRCopyDstReg(Register Reg) const
Register getPrivateSegmentWaveByteOffsetSystemSGPR() const
bool hasImplicitArgPtr() const
Register addWorkGroupIDZ()
bool mayNeedAGPRs() const
Register addWorkGroupInfo()
bool hasWorkItemIDZ() const
unsigned getMaxNumWorkGroupsY() const
unsigned getPSInputEnable() const
void setScratchRSrcReg(Register Reg)
void addToSpilledSGPRs(unsigned num)
const AMDGPUGWSResourcePseudoSourceValue * getGWSPSV(const AMDGPUTargetMachine &TM)
void reserveWWMRegister(Register Reg)
bool hasPrivateSegmentWaveByteOffset() const
Register addWorkGroupIDX()
Instances of this class encapsulate one diagnostic report, allowing printing to a raw_ostream as a ca...
Represents a range in source code.
bool insert(const value_type &X)
Insert a new element into the SetVector.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
iterator insert(iterator I, T &&Elt)
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
StackOffset holds a fixed and a scalable offset in bytes.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
LLVM Value Representation.
This class implements an extremely fast bulk output stream that can only output to a stream.
This is an optimization pass for GlobalISel generic memory operations.
uint16_t MCPhysReg
An unsigned integer type large enough to represent all physical registers, but not necessarily virtua...
auto upper_bound(R &&Range, T &&Value)
Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...
bool is_sorted(R &&Range, Compare C)
Wrapper function around std::is_sorted to check if elements in a range R are sorted with respect to a...
auto find_if(R &&Range, UnaryPredicate P)
Provide wrappers to std::find_if which take ranges instead of having to pass begin/end explicitly.
bool is_contained(R &&Range, const E &Element)
Returns true if Element is found in Range.
This struct is a compact representation of a valid (non-zero power of two) alignment.
static ArgDescriptor createRegister(Register Reg, unsigned Mask=~0u)
Helper struct shared between Function Specialization and SCCP Solver.
@ PreserveSign
The sign of a flushed-to-zero number is preserved in the sign of 0.
MachineFunctionInfo - This class can be derived from and used by targets to hold private target-speci...
SmallVector< MCPhysReg, 32 > Lanes
Targets should override this in a way that mirrors the implementation of llvm::MachineFunctionInfo.
static void mapping(IO &YamlIO, SIArgumentInfo &AI)
static void mapping(IO &YamlIO, SIArgument &A)
static void mapping(IO &YamlIO, SIMachineFunctionInfo &MFI)
static void mapping(IO &YamlIO, SIMode &Mode)
std::optional< SIArgument > PrivateSegmentWaveByteOffset
std::optional< SIArgument > WorkGroupIDY
std::optional< SIArgument > FlatScratchInit
std::optional< SIArgument > DispatchPtr
std::optional< SIArgument > DispatchID
std::optional< SIArgument > WorkItemIDY
std::optional< SIArgument > WorkGroupIDX
std::optional< SIArgument > ImplicitArgPtr
std::optional< SIArgument > QueuePtr
std::optional< SIArgument > WorkGroupInfo
std::optional< SIArgument > LDSKernelId
std::optional< SIArgument > ImplicitBufferPtr
std::optional< SIArgument > WorkItemIDX
std::optional< SIArgument > KernargSegmentPtr
std::optional< SIArgument > WorkItemIDZ
std::optional< SIArgument > PrivateSegmentSize
std::optional< SIArgument > PrivateSegmentBuffer
std::optional< SIArgument > WorkGroupIDZ
std::optional< unsigned > Mask
SIArgument(const SIArgument &Other)
SIArgument & operator=(const SIArgument &Other)
static SIArgument createArgument(bool IsReg)
StringValue SGPRForEXECCopy
SmallVector< StringValue > WWMReservedRegs
uint32_t HighBitsOf32BitAddress
SIMachineFunctionInfo()=default
StringValue FrameOffsetReg
StringValue LongBranchReservedReg
uint64_t ExplicitKernArgSize
void mappingImpl(yaml::IO &YamlIO) override
~SIMachineFunctionInfo()=default
StringValue VGPRForAGPRCopy
std::optional< SIArgumentInfo > ArgInfo
std::optional< FrameIndex > ScavengeFI
unsigned BytesInStackArgArea
StringValue ScratchRSrcReg
StringValue StackPtrOffsetReg
SIMode(const SIModeRegisterDefaults &Mode)
bool FP64FP16OutputDenormals
bool operator==(const SIMode Other) const
bool FP64FP16InputDenormals
A wrapper around std::string which contains a source range that's being set during parsing.