LLVM 19.0.0git
AMDGPUBaseInfo.cpp
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1//===- AMDGPUBaseInfo.cpp - AMDGPU Base encoding information --------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8
9#include "AMDGPUBaseInfo.h"
10#include "AMDGPU.h"
11#include "AMDGPUAsmUtils.h"
12#include "AMDKernelCodeT.h"
16#include "llvm/IR/Attributes.h"
17#include "llvm/IR/Constants.h"
18#include "llvm/IR/Function.h"
19#include "llvm/IR/GlobalValue.h"
20#include "llvm/IR/IntrinsicsAMDGPU.h"
21#include "llvm/IR/IntrinsicsR600.h"
22#include "llvm/IR/LLVMContext.h"
23#include "llvm/MC/MCInstrInfo.h"
29#include <optional>
30
31#define GET_INSTRINFO_NAMED_OPS
32#define GET_INSTRMAP_INFO
33#include "AMDGPUGenInstrInfo.inc"
34
36 "amdhsa-code-object-version", llvm::cl::Hidden,
38 llvm::cl::desc("Set default AMDHSA Code Object Version (module flag "
39 "or asm directive still take priority if present)"));
40
41namespace {
42
43/// \returns Bit mask for given bit \p Shift and bit \p Width.
44unsigned getBitMask(unsigned Shift, unsigned Width) {
45 return ((1 << Width) - 1) << Shift;
46}
47
48/// Packs \p Src into \p Dst for given bit \p Shift and bit \p Width.
49///
50/// \returns Packed \p Dst.
51unsigned packBits(unsigned Src, unsigned Dst, unsigned Shift, unsigned Width) {
52 unsigned Mask = getBitMask(Shift, Width);
53 return ((Src << Shift) & Mask) | (Dst & ~Mask);
54}
55
56/// Unpacks bits from \p Src for given bit \p Shift and bit \p Width.
57///
58/// \returns Unpacked bits.
59unsigned unpackBits(unsigned Src, unsigned Shift, unsigned Width) {
60 return (Src & getBitMask(Shift, Width)) >> Shift;
61}
62
63/// \returns Vmcnt bit shift (lower bits).
64unsigned getVmcntBitShiftLo(unsigned VersionMajor) {
65 return VersionMajor >= 11 ? 10 : 0;
66}
67
68/// \returns Vmcnt bit width (lower bits).
69unsigned getVmcntBitWidthLo(unsigned VersionMajor) {
70 return VersionMajor >= 11 ? 6 : 4;
71}
72
73/// \returns Expcnt bit shift.
74unsigned getExpcntBitShift(unsigned VersionMajor) {
75 return VersionMajor >= 11 ? 0 : 4;
76}
77
78/// \returns Expcnt bit width.
79unsigned getExpcntBitWidth(unsigned VersionMajor) { return 3; }
80
81/// \returns Lgkmcnt bit shift.
82unsigned getLgkmcntBitShift(unsigned VersionMajor) {
83 return VersionMajor >= 11 ? 4 : 8;
84}
85
86/// \returns Lgkmcnt bit width.
87unsigned getLgkmcntBitWidth(unsigned VersionMajor) {
88 return VersionMajor >= 10 ? 6 : 4;
89}
90
91/// \returns Vmcnt bit shift (higher bits).
92unsigned getVmcntBitShiftHi(unsigned VersionMajor) { return 14; }
93
94/// \returns Vmcnt bit width (higher bits).
95unsigned getVmcntBitWidthHi(unsigned VersionMajor) {
96 return (VersionMajor == 9 || VersionMajor == 10) ? 2 : 0;
97}
98
99/// \returns Loadcnt bit width
100unsigned getLoadcntBitWidth(unsigned VersionMajor) {
101 return VersionMajor >= 12 ? 6 : 0;
102}
103
104/// \returns Samplecnt bit width.
105unsigned getSamplecntBitWidth(unsigned VersionMajor) {
106 return VersionMajor >= 12 ? 6 : 0;
107}
108
109/// \returns Bvhcnt bit width.
110unsigned getBvhcntBitWidth(unsigned VersionMajor) {
111 return VersionMajor >= 12 ? 3 : 0;
112}
113
114/// \returns Dscnt bit width.
115unsigned getDscntBitWidth(unsigned VersionMajor) {
116 return VersionMajor >= 12 ? 6 : 0;
117}
118
119/// \returns Dscnt bit shift in combined S_WAIT instructions.
120unsigned getDscntBitShift(unsigned VersionMajor) { return 0; }
121
122/// \returns Storecnt or Vscnt bit width, depending on VersionMajor.
123unsigned getStorecntBitWidth(unsigned VersionMajor) {
124 return VersionMajor >= 10 ? 6 : 0;
125}
126
127/// \returns Kmcnt bit width.
128unsigned getKmcntBitWidth(unsigned VersionMajor) {
129 return VersionMajor >= 12 ? 5 : 0;
130}
131
132/// \returns shift for Loadcnt/Storecnt in combined S_WAIT instructions.
133unsigned getLoadcntStorecntBitShift(unsigned VersionMajor) {
134 return VersionMajor >= 12 ? 8 : 0;
135}
136
137/// \returns VmVsrc bit width
138inline unsigned getVmVsrcBitWidth() { return 3; }
139
140/// \returns VmVsrc bit shift
141inline unsigned getVmVsrcBitShift() { return 2; }
142
143/// \returns VaVdst bit width
144inline unsigned getVaVdstBitWidth() { return 4; }
145
146/// \returns VaVdst bit shift
147inline unsigned getVaVdstBitShift() { return 12; }
148
149/// \returns SaSdst bit width
150inline unsigned getSaSdstBitWidth() { return 1; }
151
152/// \returns SaSdst bit shift
153inline unsigned getSaSdstBitShift() { return 0; }
154
155} // end namespace anonymous
156
157namespace llvm {
158
159namespace AMDGPU {
160
161/// \returns True if \p STI is AMDHSA.
162bool isHsaAbi(const MCSubtargetInfo &STI) {
163 return STI.getTargetTriple().getOS() == Triple::AMDHSA;
164}
165
167 if (auto Ver = mdconst::extract_or_null<ConstantInt>(
168 M.getModuleFlag("amdhsa_code_object_version"))) {
169 return (unsigned)Ver->getZExtValue() / 100;
170 }
171
173}
174
177}
178
179unsigned getAMDHSACodeObjectVersion(unsigned ABIVersion) {
180 switch (ABIVersion) {
182 return 4;
184 return 5;
186 return 6;
187 default:
189 }
190}
191
192uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion) {
193 if (T.getOS() != Triple::AMDHSA)
194 return 0;
195
196 switch (CodeObjectVersion) {
197 case 4:
199 case 5:
201 case 6:
203 default:
204 report_fatal_error("Unsupported AMDHSA Code Object Version " +
205 Twine(CodeObjectVersion));
206 }
207}
208
209unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion) {
210 switch (CodeObjectVersion) {
211 case AMDHSA_COV4:
212 return 48;
213 case AMDHSA_COV5:
214 case AMDHSA_COV6:
215 default:
217 }
218}
219
220
221// FIXME: All such magic numbers about the ABI should be in a
222// central TD file.
223unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion) {
224 switch (CodeObjectVersion) {
225 case AMDHSA_COV4:
226 return 24;
227 case AMDHSA_COV5:
228 case AMDHSA_COV6:
229 default:
231 }
232}
233
234unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion) {
235 switch (CodeObjectVersion) {
236 case AMDHSA_COV4:
237 return 32;
238 case AMDHSA_COV5:
239 case AMDHSA_COV6:
240 default:
242 }
243}
244
245unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion) {
246 switch (CodeObjectVersion) {
247 case AMDHSA_COV4:
248 return 40;
249 case AMDHSA_COV5:
250 case AMDHSA_COV6:
251 default:
253 }
254}
255
256#define GET_MIMGBaseOpcodesTable_IMPL
257#define GET_MIMGDimInfoTable_IMPL
258#define GET_MIMGInfoTable_IMPL
259#define GET_MIMGLZMappingTable_IMPL
260#define GET_MIMGMIPMappingTable_IMPL
261#define GET_MIMGBiasMappingTable_IMPL
262#define GET_MIMGOffsetMappingTable_IMPL
263#define GET_MIMGG16MappingTable_IMPL
264#define GET_MAIInstInfoTable_IMPL
265#include "AMDGPUGenSearchableTables.inc"
266
267int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding,
268 unsigned VDataDwords, unsigned VAddrDwords) {
269 const MIMGInfo *Info = getMIMGOpcodeHelper(BaseOpcode, MIMGEncoding,
270 VDataDwords, VAddrDwords);
271 return Info ? Info->Opcode : -1;
272}
273
275 const MIMGInfo *Info = getMIMGInfo(Opc);
276 return Info ? getMIMGBaseOpcodeInfo(Info->BaseOpcode) : nullptr;
277}
278
279int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels) {
280 const MIMGInfo *OrigInfo = getMIMGInfo(Opc);
281 const MIMGInfo *NewInfo =
282 getMIMGOpcodeHelper(OrigInfo->BaseOpcode, OrigInfo->MIMGEncoding,
283 NewChannels, OrigInfo->VAddrDwords);
284 return NewInfo ? NewInfo->Opcode : -1;
285}
286
287unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode,
288 const MIMGDimInfo *Dim, bool IsA16,
289 bool IsG16Supported) {
290 unsigned AddrWords = BaseOpcode->NumExtraArgs;
291 unsigned AddrComponents = (BaseOpcode->Coordinates ? Dim->NumCoords : 0) +
292 (BaseOpcode->LodOrClampOrMip ? 1 : 0);
293 if (IsA16)
294 AddrWords += divideCeil(AddrComponents, 2);
295 else
296 AddrWords += AddrComponents;
297
298 // Note: For subtargets that support A16 but not G16, enabling A16 also
299 // enables 16 bit gradients.
300 // For subtargets that support A16 (operand) and G16 (done with a different
301 // instruction encoding), they are independent.
302
303 if (BaseOpcode->Gradients) {
304 if ((IsA16 && !IsG16Supported) || BaseOpcode->G16)
305 // There are two gradients per coordinate, we pack them separately.
306 // For the 3d case,
307 // we get (dy/du, dx/du) (-, dz/du) (dy/dv, dx/dv) (-, dz/dv)
308 AddrWords += alignTo<2>(Dim->NumGradients / 2);
309 else
310 AddrWords += Dim->NumGradients;
311 }
312 return AddrWords;
313}
314
315struct MUBUFInfo {
318 uint8_t elements;
323 bool tfe;
324};
325
326struct MTBUFInfo {
329 uint8_t elements;
333};
334
335struct SMInfo {
338};
339
340struct VOPInfo {
343};
344
347};
348
351};
352
355};
356
361};
362
363struct VOPDInfo {
368};
369
373};
374
375#define GET_MTBUFInfoTable_DECL
376#define GET_MTBUFInfoTable_IMPL
377#define GET_MUBUFInfoTable_DECL
378#define GET_MUBUFInfoTable_IMPL
379#define GET_SMInfoTable_DECL
380#define GET_SMInfoTable_IMPL
381#define GET_VOP1InfoTable_DECL
382#define GET_VOP1InfoTable_IMPL
383#define GET_VOP2InfoTable_DECL
384#define GET_VOP2InfoTable_IMPL
385#define GET_VOP3InfoTable_DECL
386#define GET_VOP3InfoTable_IMPL
387#define GET_VOPC64DPPTable_DECL
388#define GET_VOPC64DPPTable_IMPL
389#define GET_VOPC64DPP8Table_DECL
390#define GET_VOPC64DPP8Table_IMPL
391#define GET_VOPCAsmOnlyInfoTable_DECL
392#define GET_VOPCAsmOnlyInfoTable_IMPL
393#define GET_VOP3CAsmOnlyInfoTable_DECL
394#define GET_VOP3CAsmOnlyInfoTable_IMPL
395#define GET_VOPDComponentTable_DECL
396#define GET_VOPDComponentTable_IMPL
397#define GET_VOPDPairs_DECL
398#define GET_VOPDPairs_IMPL
399#define GET_VOPTrue16Table_DECL
400#define GET_VOPTrue16Table_IMPL
401#define GET_WMMAOpcode2AddrMappingTable_DECL
402#define GET_WMMAOpcode2AddrMappingTable_IMPL
403#define GET_WMMAOpcode3AddrMappingTable_DECL
404#define GET_WMMAOpcode3AddrMappingTable_IMPL
405#include "AMDGPUGenSearchableTables.inc"
406
407int getMTBUFBaseOpcode(unsigned Opc) {
408 const MTBUFInfo *Info = getMTBUFInfoFromOpcode(Opc);
409 return Info ? Info->BaseOpcode : -1;
410}
411
412int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements) {
413 const MTBUFInfo *Info = getMTBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
414 return Info ? Info->Opcode : -1;
415}
416
417int getMTBUFElements(unsigned Opc) {
418 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
419 return Info ? Info->elements : 0;
420}
421
422bool getMTBUFHasVAddr(unsigned Opc) {
423 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
424 return Info ? Info->has_vaddr : false;
425}
426
427bool getMTBUFHasSrsrc(unsigned Opc) {
428 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
429 return Info ? Info->has_srsrc : false;
430}
431
432bool getMTBUFHasSoffset(unsigned Opc) {
433 const MTBUFInfo *Info = getMTBUFOpcodeHelper(Opc);
434 return Info ? Info->has_soffset : false;
435}
436
437int getMUBUFBaseOpcode(unsigned Opc) {
438 const MUBUFInfo *Info = getMUBUFInfoFromOpcode(Opc);
439 return Info ? Info->BaseOpcode : -1;
440}
441
442int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements) {
443 const MUBUFInfo *Info = getMUBUFInfoFromBaseOpcodeAndElements(BaseOpc, Elements);
444 return Info ? Info->Opcode : -1;
445}
446
447int getMUBUFElements(unsigned Opc) {
448 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
449 return Info ? Info->elements : 0;
450}
451
452bool getMUBUFHasVAddr(unsigned Opc) {
453 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
454 return Info ? Info->has_vaddr : false;
455}
456
457bool getMUBUFHasSrsrc(unsigned Opc) {
458 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
459 return Info ? Info->has_srsrc : false;
460}
461
462bool getMUBUFHasSoffset(unsigned Opc) {
463 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
464 return Info ? Info->has_soffset : false;
465}
466
467bool getMUBUFIsBufferInv(unsigned Opc) {
468 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
469 return Info ? Info->IsBufferInv : false;
470}
471
472bool getMUBUFTfe(unsigned Opc) {
473 const MUBUFInfo *Info = getMUBUFOpcodeHelper(Opc);
474 return Info ? Info->tfe : false;
475}
476
477bool getSMEMIsBuffer(unsigned Opc) {
478 const SMInfo *Info = getSMEMOpcodeHelper(Opc);
479 return Info ? Info->IsBuffer : false;
480}
481
482bool getVOP1IsSingle(unsigned Opc) {
483 const VOPInfo *Info = getVOP1OpcodeHelper(Opc);
484 return Info ? Info->IsSingle : false;
485}
486
487bool getVOP2IsSingle(unsigned Opc) {
488 const VOPInfo *Info = getVOP2OpcodeHelper(Opc);
489 return Info ? Info->IsSingle : false;
490}
491
492bool getVOP3IsSingle(unsigned Opc) {
493 const VOPInfo *Info = getVOP3OpcodeHelper(Opc);
494 return Info ? Info->IsSingle : false;
495}
496
497bool isVOPC64DPP(unsigned Opc) {
498 return isVOPC64DPPOpcodeHelper(Opc) || isVOPC64DPP8OpcodeHelper(Opc);
499}
500
501bool isVOPCAsmOnly(unsigned Opc) { return isVOPCAsmOnlyOpcodeHelper(Opc); }
502
503bool getMAIIsDGEMM(unsigned Opc) {
504 const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
505 return Info ? Info->is_dgemm : false;
506}
507
508bool getMAIIsGFX940XDL(unsigned Opc) {
509 const MAIInstInfo *Info = getMAIInstInfoHelper(Opc);
510 return Info ? Info->is_gfx940_xdl : false;
511}
512
514 if (ST.hasFeature(AMDGPU::FeatureGFX12Insts))
516 if (ST.hasFeature(AMDGPU::FeatureGFX11Insts))
518 llvm_unreachable("Subtarget generation does not support VOPD!");
519}
520
521CanBeVOPD getCanBeVOPD(unsigned Opc) {
522 const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
523 if (Info)
524 return {Info->CanBeVOPDX, true};
525 else
526 return {false, false};
527}
528
529unsigned getVOPDOpcode(unsigned Opc) {
530 const VOPDComponentInfo *Info = getVOPDComponentHelper(Opc);
531 return Info ? Info->VOPDOp : ~0u;
532}
533
534bool isVOPD(unsigned Opc) {
535 return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X);
536}
537
538bool isMAC(unsigned Opc) {
539 return Opc == AMDGPU::V_MAC_F32_e64_gfx6_gfx7 ||
540 Opc == AMDGPU::V_MAC_F32_e64_gfx10 ||
541 Opc == AMDGPU::V_MAC_F32_e64_vi ||
542 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx6_gfx7 ||
543 Opc == AMDGPU::V_MAC_LEGACY_F32_e64_gfx10 ||
544 Opc == AMDGPU::V_MAC_F16_e64_vi ||
545 Opc == AMDGPU::V_FMAC_F64_e64_gfx90a ||
546 Opc == AMDGPU::V_FMAC_F32_e64_gfx10 ||
547 Opc == AMDGPU::V_FMAC_F32_e64_gfx11 ||
548 Opc == AMDGPU::V_FMAC_F32_e64_gfx12 ||
549 Opc == AMDGPU::V_FMAC_F32_e64_vi ||
550 Opc == AMDGPU::V_FMAC_LEGACY_F32_e64_gfx10 ||
551 Opc == AMDGPU::V_FMAC_DX9_ZERO_F32_e64_gfx11 ||
552 Opc == AMDGPU::V_FMAC_F16_e64_gfx10 ||
553 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx11 ||
554 Opc == AMDGPU::V_FMAC_F16_t16_e64_gfx12 ||
555 Opc == AMDGPU::V_DOT2C_F32_F16_e64_vi ||
556 Opc == AMDGPU::V_DOT2C_I32_I16_e64_vi ||
557 Opc == AMDGPU::V_DOT4C_I32_I8_e64_vi ||
558 Opc == AMDGPU::V_DOT8C_I32_I4_e64_vi;
559}
560
561bool isPermlane16(unsigned Opc) {
562 return Opc == AMDGPU::V_PERMLANE16_B32_gfx10 ||
563 Opc == AMDGPU::V_PERMLANEX16_B32_gfx10 ||
564 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx11 ||
565 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx11 ||
566 Opc == AMDGPU::V_PERMLANE16_B32_e64_gfx12 ||
567 Opc == AMDGPU::V_PERMLANEX16_B32_e64_gfx12 ||
568 Opc == AMDGPU::V_PERMLANE16_VAR_B32_e64_gfx12 ||
569 Opc == AMDGPU::V_PERMLANEX16_VAR_B32_e64_gfx12;
570}
571
572bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc) {
573 return Opc == AMDGPU::V_CVT_F32_BF8_e64_gfx12 ||
574 Opc == AMDGPU::V_CVT_F32_FP8_e64_gfx12 ||
575 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp_gfx12 ||
576 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp_gfx12 ||
577 Opc == AMDGPU::V_CVT_F32_BF8_e64_dpp8_gfx12 ||
578 Opc == AMDGPU::V_CVT_F32_FP8_e64_dpp8_gfx12 ||
579 Opc == AMDGPU::V_CVT_PK_F32_BF8_e64_gfx12 ||
580 Opc == AMDGPU::V_CVT_PK_F32_FP8_e64_gfx12;
581}
582
583bool isGenericAtomic(unsigned Opc) {
584 return Opc == AMDGPU::G_AMDGPU_ATOMIC_FMIN ||
585 Opc == AMDGPU::G_AMDGPU_ATOMIC_FMAX ||
586 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP ||
587 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD ||
588 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB ||
589 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN ||
590 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN ||
591 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX ||
592 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX ||
593 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND ||
594 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR ||
595 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR ||
596 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC ||
597 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC ||
598 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD ||
599 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN ||
600 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX ||
601 Opc == AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP ||
602 Opc == AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG;
603}
604
605bool isTrue16Inst(unsigned Opc) {
606 const VOPTrue16Info *Info = getTrue16OpcodeHelper(Opc);
607 return Info ? Info->IsTrue16 : false;
608}
609
610unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc) {
611 const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom2AddrOpcode(Opc);
612 return Info ? Info->Opcode3Addr : ~0u;
613}
614
615unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc) {
616 const WMMAOpcodeMappingInfo *Info = getWMMAMappingInfoFrom3AddrOpcode(Opc);
617 return Info ? Info->Opcode2Addr : ~0u;
618}
619
620// Wrapper for Tablegen'd function. enum Subtarget is not defined in any
621// header files, so we need to wrap it in a function that takes unsigned
622// instead.
623int getMCOpcode(uint16_t Opcode, unsigned Gen) {
624 return getMCOpcodeGen(Opcode, static_cast<Subtarget>(Gen));
625}
626
627int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily) {
628 const VOPDInfo *Info =
629 getVOPDInfoFromComponentOpcodes(OpX, OpY, EncodingFamily);
630 return Info ? Info->Opcode : -1;
631}
632
633std::pair<unsigned, unsigned> getVOPDComponents(unsigned VOPDOpcode) {
634 const VOPDInfo *Info = getVOPDOpcodeHelper(VOPDOpcode);
635 assert(Info);
636 auto OpX = getVOPDBaseFromComponent(Info->OpX);
637 auto OpY = getVOPDBaseFromComponent(Info->OpY);
638 assert(OpX && OpY);
639 return {OpX->BaseVOP, OpY->BaseVOP};
640}
641
642namespace VOPD {
643
646
649 auto TiedIdx = OpDesc.getOperandConstraint(Component::SRC2, MCOI::TIED_TO);
650 assert(TiedIdx == -1 || TiedIdx == Component::DST);
651 HasSrc2Acc = TiedIdx != -1;
652
653 SrcOperandsNum = OpDesc.getNumOperands() - OpDesc.getNumDefs();
654 assert(SrcOperandsNum <= Component::MAX_SRC_NUM);
655
656 auto OperandsNum = OpDesc.getNumOperands();
657 unsigned CompOprIdx;
658 for (CompOprIdx = Component::SRC1; CompOprIdx < OperandsNum; ++CompOprIdx) {
659 if (OpDesc.operands()[CompOprIdx].OperandType == AMDGPU::OPERAND_KIMM32) {
660 MandatoryLiteralIdx = CompOprIdx;
661 break;
662 }
663 }
664}
665
666unsigned ComponentInfo::getIndexInParsedOperands(unsigned CompOprIdx) const {
667 assert(CompOprIdx < Component::MAX_OPR_NUM);
668
669 if (CompOprIdx == Component::DST)
671
672 auto CompSrcIdx = CompOprIdx - Component::DST_NUM;
673 if (CompSrcIdx < getCompParsedSrcOperandsNum())
674 return getIndexOfSrcInParsedOperands(CompSrcIdx);
675
676 // The specified operand does not exist.
677 return 0;
678}
679
681 std::function<unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc) const {
682
683 auto OpXRegs = getRegIndices(ComponentIndex::X, GetRegIdx);
684 auto OpYRegs = getRegIndices(ComponentIndex::Y, GetRegIdx);
685
686 const unsigned CompOprNum =
688 unsigned CompOprIdx;
689 for (CompOprIdx = 0; CompOprIdx < CompOprNum; ++CompOprIdx) {
690 unsigned BanksMasks = VOPD_VGPR_BANK_MASKS[CompOprIdx];
691 if (OpXRegs[CompOprIdx] && OpYRegs[CompOprIdx] &&
692 ((OpXRegs[CompOprIdx] & BanksMasks) ==
693 (OpYRegs[CompOprIdx] & BanksMasks)))
694 return CompOprIdx;
695 }
696
697 return {};
698}
699
700// Return an array of VGPR registers [DST,SRC0,SRC1,SRC2] used
701// by the specified component. If an operand is unused
702// or is not a VGPR, the corresponding value is 0.
703//
704// GetRegIdx(Component, MCOperandIdx) must return a VGPR register index
705// for the specified component and MC operand. The callback must return 0
706// if the operand is not a register or not a VGPR.
707InstInfo::RegIndices InstInfo::getRegIndices(
708 unsigned CompIdx,
709 std::function<unsigned(unsigned, unsigned)> GetRegIdx) const {
710 assert(CompIdx < COMPONENTS_NUM);
711
712 const auto &Comp = CompInfo[CompIdx];
714
715 RegIndices[DST] = GetRegIdx(CompIdx, Comp.getIndexOfDstInMCOperands());
716
717 for (unsigned CompOprIdx : {SRC0, SRC1, SRC2}) {
718 unsigned CompSrcIdx = CompOprIdx - DST_NUM;
719 RegIndices[CompOprIdx] =
720 Comp.hasRegSrcOperand(CompSrcIdx)
721 ? GetRegIdx(CompIdx, Comp.getIndexOfSrcInMCOperands(CompSrcIdx))
722 : 0;
723 }
724 return RegIndices;
725}
726
727} // namespace VOPD
728
730 return VOPD::InstInfo(OpX, OpY);
731}
732
733VOPD::InstInfo getVOPDInstInfo(unsigned VOPDOpcode,
734 const MCInstrInfo *InstrInfo) {
735 auto [OpX, OpY] = getVOPDComponents(VOPDOpcode);
736 const auto &OpXDesc = InstrInfo->get(OpX);
737 const auto &OpYDesc = InstrInfo->get(OpY);
739 VOPD::ComponentInfo OpYInfo(OpYDesc, OpXInfo);
740 return VOPD::InstInfo(OpXInfo, OpYInfo);
741}
742
743namespace IsaInfo {
744
746 : STI(STI), XnackSetting(TargetIDSetting::Any),
747 SramEccSetting(TargetIDSetting::Any) {
748 if (!STI.getFeatureBits().test(FeatureSupportsXNACK))
749 XnackSetting = TargetIDSetting::Unsupported;
750 if (!STI.getFeatureBits().test(FeatureSupportsSRAMECC))
751 SramEccSetting = TargetIDSetting::Unsupported;
752}
753
755 // Check if xnack or sramecc is explicitly enabled or disabled. In the
756 // absence of the target features we assume we must generate code that can run
757 // in any environment.
758 SubtargetFeatures Features(FS);
759 std::optional<bool> XnackRequested;
760 std::optional<bool> SramEccRequested;
761
762 for (const std::string &Feature : Features.getFeatures()) {
763 if (Feature == "+xnack")
764 XnackRequested = true;
765 else if (Feature == "-xnack")
766 XnackRequested = false;
767 else if (Feature == "+sramecc")
768 SramEccRequested = true;
769 else if (Feature == "-sramecc")
770 SramEccRequested = false;
771 }
772
773 bool XnackSupported = isXnackSupported();
774 bool SramEccSupported = isSramEccSupported();
775
776 if (XnackRequested) {
777 if (XnackSupported) {
778 XnackSetting =
779 *XnackRequested ? TargetIDSetting::On : TargetIDSetting::Off;
780 } else {
781 // If a specific xnack setting was requested and this GPU does not support
782 // xnack emit a warning. Setting will remain set to "Unsupported".
783 if (*XnackRequested) {
784 errs() << "warning: xnack 'On' was requested for a processor that does "
785 "not support it!\n";
786 } else {
787 errs() << "warning: xnack 'Off' was requested for a processor that "
788 "does not support it!\n";
789 }
790 }
791 }
792
793 if (SramEccRequested) {
794 if (SramEccSupported) {
795 SramEccSetting =
796 *SramEccRequested ? TargetIDSetting::On : TargetIDSetting::Off;
797 } else {
798 // If a specific sramecc setting was requested and this GPU does not
799 // support sramecc emit a warning. Setting will remain set to
800 // "Unsupported".
801 if (*SramEccRequested) {
802 errs() << "warning: sramecc 'On' was requested for a processor that "
803 "does not support it!\n";
804 } else {
805 errs() << "warning: sramecc 'Off' was requested for a processor that "
806 "does not support it!\n";
807 }
808 }
809 }
810}
811
812static TargetIDSetting
814 if (FeatureString.ends_with("-"))
816 if (FeatureString.ends_with("+"))
817 return TargetIDSetting::On;
818
819 llvm_unreachable("Malformed feature string");
820}
821
823 SmallVector<StringRef, 3> TargetIDSplit;
824 TargetID.split(TargetIDSplit, ':');
825
826 for (const auto &FeatureString : TargetIDSplit) {
827 if (FeatureString.starts_with("xnack"))
828 XnackSetting = getTargetIDSettingFromFeatureString(FeatureString);
829 if (FeatureString.starts_with("sramecc"))
830 SramEccSetting = getTargetIDSettingFromFeatureString(FeatureString);
831 }
832}
833
834std::string AMDGPUTargetID::toString() const {
835 std::string StringRep;
836 raw_string_ostream StreamRep(StringRep);
837
838 auto TargetTriple = STI.getTargetTriple();
839 auto Version = getIsaVersion(STI.getCPU());
840
841 StreamRep << TargetTriple.getArchName() << '-'
842 << TargetTriple.getVendorName() << '-'
843 << TargetTriple.getOSName() << '-'
844 << TargetTriple.getEnvironmentName() << '-';
845
846 std::string Processor;
847 // TODO: Following else statement is present here because we used various
848 // alias names for GPUs up until GFX9 (e.g. 'fiji' is same as 'gfx803').
849 // Remove once all aliases are removed from GCNProcessors.td.
850 if (Version.Major >= 9)
851 Processor = STI.getCPU().str();
852 else
853 Processor = (Twine("gfx") + Twine(Version.Major) + Twine(Version.Minor) +
854 Twine(Version.Stepping))
855 .str();
856
857 std::string Features;
858 if (STI.getTargetTriple().getOS() == Triple::AMDHSA) {
859 // sramecc.
861 Features += ":sramecc-";
863 Features += ":sramecc+";
864 // xnack.
866 Features += ":xnack-";
868 Features += ":xnack+";
869 }
870
871 StreamRep << Processor << Features;
872
873 StreamRep.flush();
874 return StringRep;
875}
876
877unsigned getWavefrontSize(const MCSubtargetInfo *STI) {
878 if (STI->getFeatureBits().test(FeatureWavefrontSize16))
879 return 16;
880 if (STI->getFeatureBits().test(FeatureWavefrontSize32))
881 return 32;
882
883 return 64;
884}
885
887 unsigned BytesPerCU = 0;
888 if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
889 BytesPerCU = 32768;
890 if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
891 BytesPerCU = 65536;
892
893 // "Per CU" really means "per whatever functional block the waves of a
894 // workgroup must share". So the effective local memory size is doubled in
895 // WGP mode on gfx10.
896 if (isGFX10Plus(*STI) && !STI->getFeatureBits().test(FeatureCuMode))
897 BytesPerCU *= 2;
898
899 return BytesPerCU;
900}
901
903 if (STI->getFeatureBits().test(FeatureLocalMemorySize32768))
904 return 32768;
905 if (STI->getFeatureBits().test(FeatureLocalMemorySize65536))
906 return 65536;
907 return 0;
908}
909
910unsigned getEUsPerCU(const MCSubtargetInfo *STI) {
911 // "Per CU" really means "per whatever functional block the waves of a
912 // workgroup must share". For gfx10 in CU mode this is the CU, which contains
913 // two SIMDs.
914 if (isGFX10Plus(*STI) && STI->getFeatureBits().test(FeatureCuMode))
915 return 2;
916 // Pre-gfx10 a CU contains four SIMDs. For gfx10 in WGP mode the WGP contains
917 // two CUs, so a total of four SIMDs.
918 return 4;
919}
920
922 unsigned FlatWorkGroupSize) {
923 assert(FlatWorkGroupSize != 0);
924 if (STI->getTargetTriple().getArch() != Triple::amdgcn)
925 return 8;
926 unsigned MaxWaves = getMaxWavesPerEU(STI) * getEUsPerCU(STI);
927 unsigned N = getWavesPerWorkGroup(STI, FlatWorkGroupSize);
928 if (N == 1) {
929 // Single-wave workgroups don't consume barrier resources.
930 return MaxWaves;
931 }
932
933 unsigned MaxBarriers = 16;
934 if (isGFX10Plus(*STI) && !STI->getFeatureBits().test(FeatureCuMode))
935 MaxBarriers = 32;
936
937 return std::min(MaxWaves / N, MaxBarriers);
938}
939
940unsigned getMinWavesPerEU(const MCSubtargetInfo *STI) {
941 return 1;
942}
943
944unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI) {
945 // FIXME: Need to take scratch memory into account.
946 if (isGFX90A(*STI))
947 return 8;
948 if (!isGFX10Plus(*STI))
949 return 10;
950 return hasGFX10_3Insts(*STI) ? 16 : 20;
951}
952
954 unsigned FlatWorkGroupSize) {
955 return divideCeil(getWavesPerWorkGroup(STI, FlatWorkGroupSize),
956 getEUsPerCU(STI));
957}
958
960 return 1;
961}
962
964 // Some subtargets allow encoding 2048, but this isn't tested or supported.
965 return 1024;
966}
967
969 unsigned FlatWorkGroupSize) {
970 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI));
971}
972
974 IsaVersion Version = getIsaVersion(STI->getCPU());
975 if (Version.Major >= 10)
976 return getAddressableNumSGPRs(STI);
977 if (Version.Major >= 8)
978 return 16;
979 return 8;
980}
981
983 return 8;
984}
985
986unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI) {
987 IsaVersion Version = getIsaVersion(STI->getCPU());
988 if (Version.Major >= 8)
989 return 800;
990 return 512;
991}
992
994 if (STI->getFeatureBits().test(FeatureSGPRInitBug))
996
997 IsaVersion Version = getIsaVersion(STI->getCPU());
998 if (Version.Major >= 10)
999 return 106;
1000 if (Version.Major >= 8)
1001 return 102;
1002 return 104;
1003}
1004
1005unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1006 assert(WavesPerEU != 0);
1007
1008 IsaVersion Version = getIsaVersion(STI->getCPU());
1009 if (Version.Major >= 10)
1010 return 0;
1011
1012 if (WavesPerEU >= getMaxWavesPerEU(STI))
1013 return 0;
1014
1015 unsigned MinNumSGPRs = getTotalNumSGPRs(STI) / (WavesPerEU + 1);
1016 if (STI->getFeatureBits().test(FeatureTrapHandler))
1017 MinNumSGPRs -= std::min(MinNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
1018 MinNumSGPRs = alignDown(MinNumSGPRs, getSGPRAllocGranule(STI)) + 1;
1019 return std::min(MinNumSGPRs, getAddressableNumSGPRs(STI));
1020}
1021
1022unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
1023 bool Addressable) {
1024 assert(WavesPerEU != 0);
1025
1026 unsigned AddressableNumSGPRs = getAddressableNumSGPRs(STI);
1027 IsaVersion Version = getIsaVersion(STI->getCPU());
1028 if (Version.Major >= 10)
1029 return Addressable ? AddressableNumSGPRs : 108;
1030 if (Version.Major >= 8 && !Addressable)
1031 AddressableNumSGPRs = 112;
1032 unsigned MaxNumSGPRs = getTotalNumSGPRs(STI) / WavesPerEU;
1033 if (STI->getFeatureBits().test(FeatureTrapHandler))
1034 MaxNumSGPRs -= std::min(MaxNumSGPRs, (unsigned)TRAP_NUM_SGPRS);
1035 MaxNumSGPRs = alignDown(MaxNumSGPRs, getSGPRAllocGranule(STI));
1036 return std::min(MaxNumSGPRs, AddressableNumSGPRs);
1037}
1038
1039unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
1040 bool FlatScrUsed, bool XNACKUsed) {
1041 unsigned ExtraSGPRs = 0;
1042 if (VCCUsed)
1043 ExtraSGPRs = 2;
1044
1045 IsaVersion Version = getIsaVersion(STI->getCPU());
1046 if (Version.Major >= 10)
1047 return ExtraSGPRs;
1048
1049 if (Version.Major < 8) {
1050 if (FlatScrUsed)
1051 ExtraSGPRs = 4;
1052 } else {
1053 if (XNACKUsed)
1054 ExtraSGPRs = 4;
1055
1056 if (FlatScrUsed ||
1057 STI->getFeatureBits().test(AMDGPU::FeatureArchitectedFlatScratch))
1058 ExtraSGPRs = 6;
1059 }
1060
1061 return ExtraSGPRs;
1062}
1063
1064unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed,
1065 bool FlatScrUsed) {
1066 return getNumExtraSGPRs(STI, VCCUsed, FlatScrUsed,
1067 STI->getFeatureBits().test(AMDGPU::FeatureXNACK));
1068}
1069
1070static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs,
1071 unsigned Granule) {
1072 return divideCeil(std::max(1u, NumRegs), Granule);
1073}
1074
1075unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs) {
1076 // SGPRBlocks is actual number of SGPR blocks minus 1.
1078 1;
1079}
1080
1082 std::optional<bool> EnableWavefrontSize32) {
1083 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1084 return 8;
1085
1086 bool IsWave32 = EnableWavefrontSize32 ?
1087 *EnableWavefrontSize32 :
1088 STI->getFeatureBits().test(FeatureWavefrontSize32);
1089
1090 if (STI->getFeatureBits().test(Feature1_5xVGPRs))
1091 return IsWave32 ? 24 : 12;
1092
1093 if (hasGFX10_3Insts(*STI))
1094 return IsWave32 ? 16 : 8;
1095
1096 return IsWave32 ? 8 : 4;
1097}
1098
1100 std::optional<bool> EnableWavefrontSize32) {
1101 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1102 return 8;
1103
1104 bool IsWave32 = EnableWavefrontSize32 ?
1105 *EnableWavefrontSize32 :
1106 STI->getFeatureBits().test(FeatureWavefrontSize32);
1107
1108 return IsWave32 ? 8 : 4;
1109}
1110
1111unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI) {
1112 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1113 return 512;
1114 if (!isGFX10Plus(*STI))
1115 return 256;
1116 bool IsWave32 = STI->getFeatureBits().test(FeatureWavefrontSize32);
1117 if (STI->getFeatureBits().test(Feature1_5xVGPRs))
1118 return IsWave32 ? 1536 : 768;
1119 return IsWave32 ? 1024 : 512;
1120}
1121
1122unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI) { return 256; }
1123
1125 if (STI->getFeatureBits().test(FeatureGFX90AInsts))
1126 return 512;
1127 return getAddressableNumArchVGPRs(STI);
1128}
1129
1131 unsigned NumVGPRs) {
1133 getMaxWavesPerEU(STI),
1134 getTotalNumVGPRs(STI));
1135}
1136
1137unsigned getNumWavesPerEUWithNumVGPRs(unsigned NumVGPRs, unsigned Granule,
1138 unsigned MaxWaves,
1139 unsigned TotalNumVGPRs) {
1140 if (NumVGPRs < Granule)
1141 return MaxWaves;
1142 unsigned RoundedRegs = alignTo(NumVGPRs, Granule);
1143 return std::min(std::max(TotalNumVGPRs / RoundedRegs, 1u), MaxWaves);
1144}
1145
1146unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves,
1148 if (Gen >= AMDGPUSubtarget::GFX10)
1149 return MaxWaves;
1150
1152 if (SGPRs <= 80)
1153 return 10;
1154 if (SGPRs <= 88)
1155 return 9;
1156 if (SGPRs <= 100)
1157 return 8;
1158 return 7;
1159 }
1160 if (SGPRs <= 48)
1161 return 10;
1162 if (SGPRs <= 56)
1163 return 9;
1164 if (SGPRs <= 64)
1165 return 8;
1166 if (SGPRs <= 72)
1167 return 7;
1168 if (SGPRs <= 80)
1169 return 6;
1170 return 5;
1171}
1172
1173unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1174 assert(WavesPerEU != 0);
1175
1176 unsigned MaxWavesPerEU = getMaxWavesPerEU(STI);
1177 if (WavesPerEU >= MaxWavesPerEU)
1178 return 0;
1179
1180 unsigned TotNumVGPRs = getTotalNumVGPRs(STI);
1181 unsigned AddrsableNumVGPRs = getAddressableNumVGPRs(STI);
1182 unsigned Granule = getVGPRAllocGranule(STI);
1183 unsigned MaxNumVGPRs = alignDown(TotNumVGPRs / WavesPerEU, Granule);
1184
1185 if (MaxNumVGPRs == alignDown(TotNumVGPRs / MaxWavesPerEU, Granule))
1186 return 0;
1187
1188 unsigned MinWavesPerEU = getNumWavesPerEUWithNumVGPRs(STI, AddrsableNumVGPRs);
1189 if (WavesPerEU < MinWavesPerEU)
1190 return getMinNumVGPRs(STI, MinWavesPerEU);
1191
1192 unsigned MaxNumVGPRsNext = alignDown(TotNumVGPRs / (WavesPerEU + 1), Granule);
1193 unsigned MinNumVGPRs = 1 + std::min(MaxNumVGPRs - Granule, MaxNumVGPRsNext);
1194 return std::min(MinNumVGPRs, AddrsableNumVGPRs);
1195}
1196
1197unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU) {
1198 assert(WavesPerEU != 0);
1199
1200 unsigned MaxNumVGPRs = alignDown(getTotalNumVGPRs(STI) / WavesPerEU,
1201 getVGPRAllocGranule(STI));
1202 unsigned AddressableNumVGPRs = getAddressableNumVGPRs(STI);
1203 return std::min(MaxNumVGPRs, AddressableNumVGPRs);
1204}
1205
1206unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs,
1207 std::optional<bool> EnableWavefrontSize32) {
1209 NumVGPRs, getVGPREncodingGranule(STI, EnableWavefrontSize32)) -
1210 1;
1211}
1212
1214 unsigned NumVGPRs,
1215 std::optional<bool> EnableWavefrontSize32) {
1217 NumVGPRs, getVGPRAllocGranule(STI, EnableWavefrontSize32));
1218}
1219} // end namespace IsaInfo
1220
1222 const MCSubtargetInfo *STI) {
1223 IsaVersion Version = getIsaVersion(STI->getCPU());
1224
1225 memset(&Header, 0, sizeof(Header));
1226
1227 Header.amd_kernel_code_version_major = 1;
1228 Header.amd_kernel_code_version_minor = 2;
1229 Header.amd_machine_kind = 1; // AMD_MACHINE_KIND_AMDGPU
1230 Header.amd_machine_version_major = Version.Major;
1231 Header.amd_machine_version_minor = Version.Minor;
1232 Header.amd_machine_version_stepping = Version.Stepping;
1233 Header.kernel_code_entry_byte_offset = sizeof(Header);
1234 Header.wavefront_size = 6;
1235
1236 // If the code object does not support indirect functions, then the value must
1237 // be 0xffffffff.
1238 Header.call_convention = -1;
1239
1240 // These alignment values are specified in powers of two, so alignment =
1241 // 2^n. The minimum alignment is 2^4 = 16.
1242 Header.kernarg_segment_alignment = 4;
1243 Header.group_segment_alignment = 4;
1244 Header.private_segment_alignment = 4;
1245
1246 if (Version.Major >= 10) {
1247 if (STI->getFeatureBits().test(FeatureWavefrontSize32)) {
1248 Header.wavefront_size = 5;
1249 Header.code_properties |= AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32;
1250 }
1251 Header.compute_pgm_resource_registers |=
1252 S_00B848_WGP_MODE(STI->getFeatureBits().test(FeatureCuMode) ? 0 : 1) |
1254 }
1255}
1256
1259}
1260
1263}
1264
1266 unsigned AS = GV->getAddressSpace();
1267 return AS == AMDGPUAS::CONSTANT_ADDRESS ||
1269}
1270
1272 return TT.getArch() == Triple::r600;
1273}
1274
1275std::pair<unsigned, unsigned>
1277 std::pair<unsigned, unsigned> Default,
1278 bool OnlyFirstRequired) {
1279 Attribute A = F.getFnAttribute(Name);
1280 if (!A.isStringAttribute())
1281 return Default;
1282
1283 LLVMContext &Ctx = F.getContext();
1284 std::pair<unsigned, unsigned> Ints = Default;
1285 std::pair<StringRef, StringRef> Strs = A.getValueAsString().split(',');
1286 if (Strs.first.trim().getAsInteger(0, Ints.first)) {
1287 Ctx.emitError("can't parse first integer attribute " + Name);
1288 return Default;
1289 }
1290 if (Strs.second.trim().getAsInteger(0, Ints.second)) {
1291 if (!OnlyFirstRequired || !Strs.second.trim().empty()) {
1292 Ctx.emitError("can't parse second integer attribute " + Name);
1293 return Default;
1294 }
1295 }
1296
1297 return Ints;
1298}
1299
1301 unsigned Size) {
1302 assert(Size > 2);
1304
1305 Attribute A = F.getFnAttribute(Name);
1306 if (!A.isStringAttribute())
1307 return Default;
1308
1309 SmallVector<unsigned> Vals(Size, 0);
1310
1311 LLVMContext &Ctx = F.getContext();
1312
1313 StringRef S = A.getValueAsString();
1314 unsigned i = 0;
1315 for (; !S.empty() && i < Size; i++) {
1316 std::pair<StringRef, StringRef> Strs = S.split(',');
1317 unsigned IntVal;
1318 if (Strs.first.trim().getAsInteger(0, IntVal)) {
1319 Ctx.emitError("can't parse integer attribute " + Strs.first + " in " +
1320 Name);
1321 return Default;
1322 }
1323 Vals[i] = IntVal;
1324 S = Strs.second;
1325 }
1326
1327 if (!S.empty() || i < Size) {
1328 Ctx.emitError("attribute " + Name +
1329 " has incorrect number of integers; expected " +
1330 llvm::utostr(Size));
1331 return Default;
1332 }
1333 return Vals;
1334}
1335
1336unsigned getVmcntBitMask(const IsaVersion &Version) {
1337 return (1 << (getVmcntBitWidthLo(Version.Major) +
1338 getVmcntBitWidthHi(Version.Major))) -
1339 1;
1340}
1341
1342unsigned getLoadcntBitMask(const IsaVersion &Version) {
1343 return (1 << getLoadcntBitWidth(Version.Major)) - 1;
1344}
1345
1346unsigned getSamplecntBitMask(const IsaVersion &Version) {
1347 return (1 << getSamplecntBitWidth(Version.Major)) - 1;
1348}
1349
1350unsigned getBvhcntBitMask(const IsaVersion &Version) {
1351 return (1 << getBvhcntBitWidth(Version.Major)) - 1;
1352}
1353
1354unsigned getExpcntBitMask(const IsaVersion &Version) {
1355 return (1 << getExpcntBitWidth(Version.Major)) - 1;
1356}
1357
1358unsigned getLgkmcntBitMask(const IsaVersion &Version) {
1359 return (1 << getLgkmcntBitWidth(Version.Major)) - 1;
1360}
1361
1362unsigned getDscntBitMask(const IsaVersion &Version) {
1363 return (1 << getDscntBitWidth(Version.Major)) - 1;
1364}
1365
1366unsigned getKmcntBitMask(const IsaVersion &Version) {
1367 return (1 << getKmcntBitWidth(Version.Major)) - 1;
1368}
1369
1370unsigned getStorecntBitMask(const IsaVersion &Version) {
1371 return (1 << getStorecntBitWidth(Version.Major)) - 1;
1372}
1373
1374unsigned getWaitcntBitMask(const IsaVersion &Version) {
1375 unsigned VmcntLo = getBitMask(getVmcntBitShiftLo(Version.Major),
1376 getVmcntBitWidthLo(Version.Major));
1377 unsigned Expcnt = getBitMask(getExpcntBitShift(Version.Major),
1378 getExpcntBitWidth(Version.Major));
1379 unsigned Lgkmcnt = getBitMask(getLgkmcntBitShift(Version.Major),
1380 getLgkmcntBitWidth(Version.Major));
1381 unsigned VmcntHi = getBitMask(getVmcntBitShiftHi(Version.Major),
1382 getVmcntBitWidthHi(Version.Major));
1383 return VmcntLo | Expcnt | Lgkmcnt | VmcntHi;
1384}
1385
1386unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt) {
1387 unsigned VmcntLo = unpackBits(Waitcnt, getVmcntBitShiftLo(Version.Major),
1388 getVmcntBitWidthLo(Version.Major));
1389 unsigned VmcntHi = unpackBits(Waitcnt, getVmcntBitShiftHi(Version.Major),
1390 getVmcntBitWidthHi(Version.Major));
1391 return VmcntLo | VmcntHi << getVmcntBitWidthLo(Version.Major);
1392}
1393
1394unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt) {
1395 return unpackBits(Waitcnt, getExpcntBitShift(Version.Major),
1396 getExpcntBitWidth(Version.Major));
1397}
1398
1399unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt) {
1400 return unpackBits(Waitcnt, getLgkmcntBitShift(Version.Major),
1401 getLgkmcntBitWidth(Version.Major));
1402}
1403
1404void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt,
1405 unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt) {
1406 Vmcnt = decodeVmcnt(Version, Waitcnt);
1407 Expcnt = decodeExpcnt(Version, Waitcnt);
1408 Lgkmcnt = decodeLgkmcnt(Version, Waitcnt);
1409}
1410
1411Waitcnt decodeWaitcnt(const IsaVersion &Version, unsigned Encoded) {
1412 Waitcnt Decoded;
1413 Decoded.LoadCnt = decodeVmcnt(Version, Encoded);
1414 Decoded.ExpCnt = decodeExpcnt(Version, Encoded);
1415 Decoded.DsCnt = decodeLgkmcnt(Version, Encoded);
1416 return Decoded;
1417}
1418
1419unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt,
1420 unsigned Vmcnt) {
1421 Waitcnt = packBits(Vmcnt, Waitcnt, getVmcntBitShiftLo(Version.Major),
1422 getVmcntBitWidthLo(Version.Major));
1423 return packBits(Vmcnt >> getVmcntBitWidthLo(Version.Major), Waitcnt,
1424 getVmcntBitShiftHi(Version.Major),
1425 getVmcntBitWidthHi(Version.Major));
1426}
1427
1428unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt,
1429 unsigned Expcnt) {
1430 return packBits(Expcnt, Waitcnt, getExpcntBitShift(Version.Major),
1431 getExpcntBitWidth(Version.Major));
1432}
1433
1434unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt,
1435 unsigned Lgkmcnt) {
1436 return packBits(Lgkmcnt, Waitcnt, getLgkmcntBitShift(Version.Major),
1437 getLgkmcntBitWidth(Version.Major));
1438}
1439
1440unsigned encodeWaitcnt(const IsaVersion &Version,
1441 unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt) {
1442 unsigned Waitcnt = getWaitcntBitMask(Version);
1443 Waitcnt = encodeVmcnt(Version, Waitcnt, Vmcnt);
1444 Waitcnt = encodeExpcnt(Version, Waitcnt, Expcnt);
1445 Waitcnt = encodeLgkmcnt(Version, Waitcnt, Lgkmcnt);
1446 return Waitcnt;
1447}
1448
1449unsigned encodeWaitcnt(const IsaVersion &Version, const Waitcnt &Decoded) {
1450 return encodeWaitcnt(Version, Decoded.LoadCnt, Decoded.ExpCnt, Decoded.DsCnt);
1451}
1452
1453static unsigned getCombinedCountBitMask(const IsaVersion &Version,
1454 bool IsStore) {
1455 unsigned Dscnt = getBitMask(getDscntBitShift(Version.Major),
1456 getDscntBitWidth(Version.Major));
1457 if (IsStore) {
1458 unsigned Storecnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1459 getStorecntBitWidth(Version.Major));
1460 return Dscnt | Storecnt;
1461 } else {
1462 unsigned Loadcnt = getBitMask(getLoadcntStorecntBitShift(Version.Major),
1463 getLoadcntBitWidth(Version.Major));
1464 return Dscnt | Loadcnt;
1465 }
1466}
1467
1468Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt) {
1469 Waitcnt Decoded;
1470 Decoded.LoadCnt =
1471 unpackBits(LoadcntDscnt, getLoadcntStorecntBitShift(Version.Major),
1472 getLoadcntBitWidth(Version.Major));
1473 Decoded.DsCnt = unpackBits(LoadcntDscnt, getDscntBitShift(Version.Major),
1474 getDscntBitWidth(Version.Major));
1475 return Decoded;
1476}
1477
1478Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt) {
1479 Waitcnt Decoded;
1480 Decoded.StoreCnt =
1481 unpackBits(StorecntDscnt, getLoadcntStorecntBitShift(Version.Major),
1482 getStorecntBitWidth(Version.Major));
1483 Decoded.DsCnt = unpackBits(StorecntDscnt, getDscntBitShift(Version.Major),
1484 getDscntBitWidth(Version.Major));
1485 return Decoded;
1486}
1487
1488static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt,
1489 unsigned Loadcnt) {
1490 return packBits(Loadcnt, Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1491 getLoadcntBitWidth(Version.Major));
1492}
1493
1494static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt,
1495 unsigned Storecnt) {
1496 return packBits(Storecnt, Waitcnt, getLoadcntStorecntBitShift(Version.Major),
1497 getStorecntBitWidth(Version.Major));
1498}
1499
1500static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt,
1501 unsigned Dscnt) {
1502 return packBits(Dscnt, Waitcnt, getDscntBitShift(Version.Major),
1503 getDscntBitWidth(Version.Major));
1504}
1505
1506static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt,
1507 unsigned Dscnt) {
1508 unsigned Waitcnt = getCombinedCountBitMask(Version, false);
1509 Waitcnt = encodeLoadcnt(Version, Waitcnt, Loadcnt);
1510 Waitcnt = encodeDscnt(Version, Waitcnt, Dscnt);
1511 return Waitcnt;
1512}
1513
1514unsigned encodeLoadcntDscnt(const IsaVersion &Version, const Waitcnt &Decoded) {
1515 return encodeLoadcntDscnt(Version, Decoded.LoadCnt, Decoded.DsCnt);
1516}
1517
1518static unsigned encodeStorecntDscnt(const IsaVersion &Version,
1519 unsigned Storecnt, unsigned Dscnt) {
1520 unsigned Waitcnt = getCombinedCountBitMask(Version, true);
1521 Waitcnt = encodeStorecnt(Version, Waitcnt, Storecnt);
1522 Waitcnt = encodeDscnt(Version, Waitcnt, Dscnt);
1523 return Waitcnt;
1524}
1525
1526unsigned encodeStorecntDscnt(const IsaVersion &Version,
1527 const Waitcnt &Decoded) {
1528 return encodeStorecntDscnt(Version, Decoded.StoreCnt, Decoded.DsCnt);
1529}
1530
1531//===----------------------------------------------------------------------===//
1532// Custom Operand Values
1533//===----------------------------------------------------------------------===//
1534
1536 int Size,
1537 const MCSubtargetInfo &STI) {
1538 unsigned Enc = 0;
1539 for (int Idx = 0; Idx < Size; ++Idx) {
1540 const auto &Op = Opr[Idx];
1541 if (Op.isSupported(STI))
1542 Enc |= Op.encode(Op.Default);
1543 }
1544 return Enc;
1545}
1546
1548 int Size, unsigned Code,
1549 bool &HasNonDefaultVal,
1550 const MCSubtargetInfo &STI) {
1551 unsigned UsedOprMask = 0;
1552 HasNonDefaultVal = false;
1553 for (int Idx = 0; Idx < Size; ++Idx) {
1554 const auto &Op = Opr[Idx];
1555 if (!Op.isSupported(STI))
1556 continue;
1557 UsedOprMask |= Op.getMask();
1558 unsigned Val = Op.decode(Code);
1559 if (!Op.isValid(Val))
1560 return false;
1561 HasNonDefaultVal |= (Val != Op.Default);
1562 }
1563 return (Code & ~UsedOprMask) == 0;
1564}
1565
1566static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size,
1567 unsigned Code, int &Idx, StringRef &Name,
1568 unsigned &Val, bool &IsDefault,
1569 const MCSubtargetInfo &STI) {
1570 while (Idx < Size) {
1571 const auto &Op = Opr[Idx++];
1572 if (Op.isSupported(STI)) {
1573 Name = Op.Name;
1574 Val = Op.decode(Code);
1575 IsDefault = (Val == Op.Default);
1576 return true;
1577 }
1578 }
1579
1580 return false;
1581}
1582
1584 int64_t InputVal) {
1585 if (InputVal < 0 || InputVal > Op.Max)
1586 return OPR_VAL_INVALID;
1587 return Op.encode(InputVal);
1588}
1589
1590static int encodeCustomOperand(const CustomOperandVal *Opr, int Size,
1591 const StringRef Name, int64_t InputVal,
1592 unsigned &UsedOprMask,
1593 const MCSubtargetInfo &STI) {
1594 int InvalidId = OPR_ID_UNKNOWN;
1595 for (int Idx = 0; Idx < Size; ++Idx) {
1596 const auto &Op = Opr[Idx];
1597 if (Op.Name == Name) {
1598 if (!Op.isSupported(STI)) {
1599 InvalidId = OPR_ID_UNSUPPORTED;
1600 continue;
1601 }
1602 auto OprMask = Op.getMask();
1603 if (OprMask & UsedOprMask)
1604 return OPR_ID_DUPLICATE;
1605 UsedOprMask |= OprMask;
1606 return encodeCustomOperandVal(Op, InputVal);
1607 }
1608 }
1609 return InvalidId;
1610}
1611
1612//===----------------------------------------------------------------------===//
1613// DepCtr
1614//===----------------------------------------------------------------------===//
1615
1616namespace DepCtr {
1617
1619 static int Default = -1;
1620 if (Default == -1)
1622 return Default;
1623}
1624
1625bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal,
1626 const MCSubtargetInfo &STI) {
1628 HasNonDefaultVal, STI);
1629}
1630
1631bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val,
1632 bool &IsDefault, const MCSubtargetInfo &STI) {
1633 return decodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Code, Id, Name, Val,
1634 IsDefault, STI);
1635}
1636
1637int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask,
1638 const MCSubtargetInfo &STI) {
1639 return encodeCustomOperand(DepCtrInfo, DEP_CTR_SIZE, Name, Val, UsedOprMask,
1640 STI);
1641}
1642
1643unsigned decodeFieldVmVsrc(unsigned Encoded) {
1644 return unpackBits(Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1645}
1646
1647unsigned decodeFieldVaVdst(unsigned Encoded) {
1648 return unpackBits(Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1649}
1650
1651unsigned decodeFieldSaSdst(unsigned Encoded) {
1652 return unpackBits(Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1653}
1654
1655unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc) {
1656 return packBits(VmVsrc, Encoded, getVmVsrcBitShift(), getVmVsrcBitWidth());
1657}
1658
1659unsigned encodeFieldVmVsrc(unsigned VmVsrc) {
1660 return encodeFieldVmVsrc(0xffff, VmVsrc);
1661}
1662
1663unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst) {
1664 return packBits(VaVdst, Encoded, getVaVdstBitShift(), getVaVdstBitWidth());
1665}
1666
1667unsigned encodeFieldVaVdst(unsigned VaVdst) {
1668 return encodeFieldVaVdst(0xffff, VaVdst);
1669}
1670
1671unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst) {
1672 return packBits(SaSdst, Encoded, getSaSdstBitShift(), getSaSdstBitWidth());
1673}
1674
1675unsigned encodeFieldSaSdst(unsigned SaSdst) {
1676 return encodeFieldSaSdst(0xffff, SaSdst);
1677}
1678
1679} // namespace DepCtr
1680
1681//===----------------------------------------------------------------------===//
1682// exp tgt
1683//===----------------------------------------------------------------------===//
1684
1685namespace Exp {
1686
1687struct ExpTgt {
1689 unsigned Tgt;
1690 unsigned MaxIndex;
1691};
1692
1693static constexpr ExpTgt ExpTgtInfo[] = {
1694 {{"null"}, ET_NULL, ET_NULL_MAX_IDX},
1695 {{"mrtz"}, ET_MRTZ, ET_MRTZ_MAX_IDX},
1696 {{"prim"}, ET_PRIM, ET_PRIM_MAX_IDX},
1697 {{"mrt"}, ET_MRT0, ET_MRT_MAX_IDX},
1698 {{"pos"}, ET_POS0, ET_POS_MAX_IDX},
1699 {{"dual_src_blend"}, ET_DUAL_SRC_BLEND0, ET_DUAL_SRC_BLEND_MAX_IDX},
1700 {{"param"}, ET_PARAM0, ET_PARAM_MAX_IDX},
1701};
1702
1703bool getTgtName(unsigned Id, StringRef &Name, int &Index) {
1704 for (const ExpTgt &Val : ExpTgtInfo) {
1705 if (Val.Tgt <= Id && Id <= Val.Tgt + Val.MaxIndex) {
1706 Index = (Val.MaxIndex == 0) ? -1 : (Id - Val.Tgt);
1707 Name = Val.Name;
1708 return true;
1709 }
1710 }
1711 return false;
1712}
1713
1714unsigned getTgtId(const StringRef Name) {
1715
1716 for (const ExpTgt &Val : ExpTgtInfo) {
1717 if (Val.MaxIndex == 0 && Name == Val.Name)
1718 return Val.Tgt;
1719
1720 if (Val.MaxIndex > 0 && Name.starts_with(Val.Name)) {
1721 StringRef Suffix = Name.drop_front(Val.Name.size());
1722
1723 unsigned Id;
1724 if (Suffix.getAsInteger(10, Id) || Id > Val.MaxIndex)
1725 return ET_INVALID;
1726
1727 // Disable leading zeroes
1728 if (Suffix.size() > 1 && Suffix[0] == '0')
1729 return ET_INVALID;
1730
1731 return Val.Tgt + Id;
1732 }
1733 }
1734 return ET_INVALID;
1735}
1736
1737bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI) {
1738 switch (Id) {
1739 case ET_NULL:
1740 return !isGFX11Plus(STI);
1741 case ET_POS4:
1742 case ET_PRIM:
1743 return isGFX10Plus(STI);
1744 case ET_DUAL_SRC_BLEND0:
1745 case ET_DUAL_SRC_BLEND1:
1746 return isGFX11Plus(STI);
1747 default:
1748 if (Id >= ET_PARAM0 && Id <= ET_PARAM31)
1749 return !isGFX11Plus(STI);
1750 return true;
1751 }
1752}
1753
1754} // namespace Exp
1755
1756//===----------------------------------------------------------------------===//
1757// MTBUF Format
1758//===----------------------------------------------------------------------===//
1759
1760namespace MTBUFFormat {
1761
1762int64_t getDfmt(const StringRef Name) {
1763 for (int Id = DFMT_MIN; Id <= DFMT_MAX; ++Id) {
1764 if (Name == DfmtSymbolic[Id])
1765 return Id;
1766 }
1767 return DFMT_UNDEF;
1768}
1769
1771 assert(Id <= DFMT_MAX);
1772 return DfmtSymbolic[Id];
1773}
1774
1776 if (isSI(STI) || isCI(STI))
1777 return NfmtSymbolicSICI;
1778 if (isVI(STI) || isGFX9(STI))
1779 return NfmtSymbolicVI;
1780 return NfmtSymbolicGFX10;
1781}
1782
1783int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI) {
1784 auto lookupTable = getNfmtLookupTable(STI);
1785 for (int Id = NFMT_MIN; Id <= NFMT_MAX; ++Id) {
1786 if (Name == lookupTable[Id])
1787 return Id;
1788 }
1789 return NFMT_UNDEF;
1790}
1791
1792StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI) {
1793 assert(Id <= NFMT_MAX);
1794 return getNfmtLookupTable(STI)[Id];
1795}
1796
1797bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1798 unsigned Dfmt;
1799 unsigned Nfmt;
1800 decodeDfmtNfmt(Id, Dfmt, Nfmt);
1801 return isValidNfmt(Nfmt, STI);
1802}
1803
1804bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI) {
1805 return !getNfmtName(Id, STI).empty();
1806}
1807
1808int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt) {
1809 return (Dfmt << DFMT_SHIFT) | (Nfmt << NFMT_SHIFT);
1810}
1811
1812void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt) {
1813 Dfmt = (Format >> DFMT_SHIFT) & DFMT_MASK;
1814 Nfmt = (Format >> NFMT_SHIFT) & NFMT_MASK;
1815}
1816
1818 if (isGFX11Plus(STI)) {
1819 for (int Id = UfmtGFX11::UFMT_FIRST; Id <= UfmtGFX11::UFMT_LAST; ++Id) {
1820 if (Name == UfmtSymbolicGFX11[Id])
1821 return Id;
1822 }
1823 } else {
1824 for (int Id = UfmtGFX10::UFMT_FIRST; Id <= UfmtGFX10::UFMT_LAST; ++Id) {
1825 if (Name == UfmtSymbolicGFX10[Id])
1826 return Id;
1827 }
1828 }
1829 return UFMT_UNDEF;
1830}
1831
1833 if(isValidUnifiedFormat(Id, STI))
1834 return isGFX10(STI) ? UfmtSymbolicGFX10[Id] : UfmtSymbolicGFX11[Id];
1835 return "";
1836}
1837
1838bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI) {
1839 return isGFX10(STI) ? Id <= UfmtGFX10::UFMT_LAST : Id <= UfmtGFX11::UFMT_LAST;
1840}
1841
1842int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt,
1843 const MCSubtargetInfo &STI) {
1844 int64_t Fmt = encodeDfmtNfmt(Dfmt, Nfmt);
1845 if (isGFX11Plus(STI)) {
1846 for (int Id = UfmtGFX11::UFMT_FIRST; Id <= UfmtGFX11::UFMT_LAST; ++Id) {
1847 if (Fmt == DfmtNfmt2UFmtGFX11[Id])
1848 return Id;
1849 }
1850 } else {
1851 for (int Id = UfmtGFX10::UFMT_FIRST; Id <= UfmtGFX10::UFMT_LAST; ++Id) {
1852 if (Fmt == DfmtNfmt2UFmtGFX10[Id])
1853 return Id;
1854 }
1855 }
1856 return UFMT_UNDEF;
1857}
1858
1859bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI) {
1860 return isGFX10Plus(STI) ? (Val <= UFMT_MAX) : (Val <= DFMT_NFMT_MAX);
1861}
1862
1864 if (isGFX10Plus(STI))
1865 return UFMT_DEFAULT;
1866 return DFMT_NFMT_DEFAULT;
1867}
1868
1869} // namespace MTBUFFormat
1870
1871//===----------------------------------------------------------------------===//
1872// SendMsg
1873//===----------------------------------------------------------------------===//
1874
1875namespace SendMsg {
1876
1879}
1880
1881bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI) {
1882 return (MsgId & ~(getMsgIdMask(STI))) == 0;
1883}
1884
1885bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI,
1886 bool Strict) {
1887 assert(isValidMsgId(MsgId, STI));
1888
1889 if (!Strict)
1890 return 0 <= OpId && isUInt<OP_WIDTH_>(OpId);
1891
1892 if (msgRequiresOp(MsgId, STI)) {
1893 if (MsgId == ID_GS_PreGFX11 && OpId == OP_GS_NOP)
1894 return false;
1895
1896 return !getMsgOpName(MsgId, OpId, STI).empty();
1897 }
1898
1899 return OpId == OP_NONE_;
1900}
1901
1902bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId,
1903 const MCSubtargetInfo &STI, bool Strict) {
1904 assert(isValidMsgOp(MsgId, OpId, STI, Strict));
1905
1906 if (!Strict)
1907 return 0 <= StreamId && isUInt<STREAM_ID_WIDTH_>(StreamId);
1908
1909 if (!isGFX11Plus(STI)) {
1910 switch (MsgId) {
1911 case ID_GS_PreGFX11:
1914 return (OpId == OP_GS_NOP) ?
1917 }
1918 }
1919 return StreamId == STREAM_ID_NONE_;
1920}
1921
1922bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI) {
1923 return MsgId == ID_SYSMSG ||
1924 (!isGFX11Plus(STI) &&
1925 (MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11));
1926}
1927
1928bool msgSupportsStream(int64_t MsgId, int64_t OpId,
1929 const MCSubtargetInfo &STI) {
1930 return !isGFX11Plus(STI) &&
1931 (MsgId == ID_GS_PreGFX11 || MsgId == ID_GS_DONE_PreGFX11) &&
1932 OpId != OP_GS_NOP;
1933}
1934
1935void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId,
1936 uint16_t &StreamId, const MCSubtargetInfo &STI) {
1937 MsgId = Val & getMsgIdMask(STI);
1938 if (isGFX11Plus(STI)) {
1939 OpId = 0;
1940 StreamId = 0;
1941 } else {
1942 OpId = (Val & OP_MASK_) >> OP_SHIFT_;
1944 }
1945}
1946
1948 uint64_t OpId,
1950 return MsgId | (OpId << OP_SHIFT_) | (StreamId << STREAM_ID_SHIFT_);
1951}
1952
1953} // namespace SendMsg
1954
1955//===----------------------------------------------------------------------===//
1956//
1957//===----------------------------------------------------------------------===//
1958
1960 return F.getFnAttributeAsParsedInteger("InitialPSInputAddr", 0);
1961}
1962
1964 // As a safe default always respond as if PS has color exports.
1965 return F.getFnAttributeAsParsedInteger(
1966 "amdgpu-color-export",
1967 F.getCallingConv() == CallingConv::AMDGPU_PS ? 1 : 0) != 0;
1968}
1969
1971 return F.getFnAttributeAsParsedInteger("amdgpu-depth-export", 0) != 0;
1972}
1973
1975 switch(cc) {
1985 return true;
1986 default:
1987 return false;
1988 }
1989}
1990
1992 return isShader(cc) || cc == CallingConv::AMDGPU_Gfx;
1993}
1994
1996 return !isGraphics(cc) || cc == CallingConv::AMDGPU_CS;
1997}
1998
2000 switch (CC) {
2010 return true;
2011 default:
2012 return false;
2013 }
2014}
2015
2017 switch (CC) {
2019 return true;
2020 default:
2021 return isEntryFunctionCC(CC) || isChainCC(CC);
2022 }
2023}
2024
2026 switch (CC) {
2029 return true;
2030 default:
2031 return false;
2032 }
2033}
2034
2035bool isKernelCC(const Function *Func) {
2036 return AMDGPU::isModuleEntryFunctionCC(Func->getCallingConv());
2037}
2038
2039bool hasXNACK(const MCSubtargetInfo &STI) {
2040 return STI.hasFeature(AMDGPU::FeatureXNACK);
2041}
2042
2043bool hasSRAMECC(const MCSubtargetInfo &STI) {
2044 return STI.hasFeature(AMDGPU::FeatureSRAMECC);
2045}
2046
2048 return STI.hasFeature(AMDGPU::FeatureMIMG_R128) && !STI.hasFeature(AMDGPU::FeatureR128A16);
2049}
2050
2051bool hasA16(const MCSubtargetInfo &STI) {
2052 return STI.hasFeature(AMDGPU::FeatureA16);
2053}
2054
2055bool hasG16(const MCSubtargetInfo &STI) {
2056 return STI.hasFeature(AMDGPU::FeatureG16);
2057}
2058
2060 return !STI.hasFeature(AMDGPU::FeatureUnpackedD16VMem) && !isCI(STI) &&
2061 !isSI(STI);
2062}
2063
2064bool hasGDS(const MCSubtargetInfo &STI) {
2065 return STI.hasFeature(AMDGPU::FeatureGDS);
2066}
2067
2068unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler) {
2069 auto Version = getIsaVersion(STI.getCPU());
2070 if (Version.Major == 10)
2071 return Version.Minor >= 3 ? 13 : 5;
2072 if (Version.Major == 11)
2073 return 5;
2074 if (Version.Major >= 12)
2075 return HasSampler ? 4 : 5;
2076 return 0;
2077}
2078
2079unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI) { return 16; }
2080
2081bool isSI(const MCSubtargetInfo &STI) {
2082 return STI.hasFeature(AMDGPU::FeatureSouthernIslands);
2083}
2084
2085bool isCI(const MCSubtargetInfo &STI) {
2086 return STI.hasFeature(AMDGPU::FeatureSeaIslands);
2087}
2088
2089bool isVI(const MCSubtargetInfo &STI) {
2090 return STI.hasFeature(AMDGPU::FeatureVolcanicIslands);
2091}
2092
2093bool isGFX9(const MCSubtargetInfo &STI) {
2094 return STI.hasFeature(AMDGPU::FeatureGFX9);
2095}
2096
2098 return isGFX9(STI) || isGFX10(STI);
2099}
2100
2102 return isGFX9(STI) || isGFX10(STI) || isGFX11(STI);
2103}
2104
2106 return isVI(STI) || isGFX9(STI) || isGFX10(STI);
2107}
2108
2109bool isGFX8Plus(const MCSubtargetInfo &STI) {
2110 return isVI(STI) || isGFX9Plus(STI);
2111}
2112
2113bool isGFX9Plus(const MCSubtargetInfo &STI) {
2114 return isGFX9(STI) || isGFX10Plus(STI);
2115}
2116
2117bool isNotGFX9Plus(const MCSubtargetInfo &STI) { return !isGFX9Plus(STI); }
2118
2119bool isGFX10(const MCSubtargetInfo &STI) {
2120 return STI.hasFeature(AMDGPU::FeatureGFX10);
2121}
2122
2124 return isGFX10(STI) || isGFX11(STI);
2125}
2126
2128 return isGFX10(STI) || isGFX11Plus(STI);
2129}
2130
2131bool isGFX11(const MCSubtargetInfo &STI) {
2132 return STI.hasFeature(AMDGPU::FeatureGFX11);
2133}
2134
2136 return isGFX11(STI) || isGFX12Plus(STI);
2137}
2138
2139bool isGFX12(const MCSubtargetInfo &STI) {
2140 return STI.getFeatureBits()[AMDGPU::FeatureGFX12];
2141}
2142
2143bool isGFX12Plus(const MCSubtargetInfo &STI) { return isGFX12(STI); }
2144
2145bool isNotGFX12Plus(const MCSubtargetInfo &STI) { return !isGFX12Plus(STI); }
2146
2148 return !isGFX11Plus(STI);
2149}
2150
2152 return isSI(STI) || isCI(STI) || isVI(STI) || isGFX9(STI);
2153}
2154
2156 return isGFX10(STI) && !AMDGPU::isGFX10_BEncoding(STI);
2157}
2158
2160 return STI.hasFeature(AMDGPU::FeatureGCN3Encoding);
2161}
2162
2164 return STI.hasFeature(AMDGPU::FeatureGFX10_AEncoding);
2165}
2166
2168 return STI.hasFeature(AMDGPU::FeatureGFX10_BEncoding);
2169}
2170
2172 return STI.hasFeature(AMDGPU::FeatureGFX10_3Insts);
2173}
2174
2176 return isGFX10_BEncoding(STI) && !isGFX12Plus(STI);
2177}
2178
2179bool isGFX90A(const MCSubtargetInfo &STI) {
2180 return STI.hasFeature(AMDGPU::FeatureGFX90AInsts);
2181}
2182
2183bool isGFX940(const MCSubtargetInfo &STI) {
2184 return STI.hasFeature(AMDGPU::FeatureGFX940Insts);
2185}
2186
2188 return STI.hasFeature(AMDGPU::FeatureArchitectedFlatScratch);
2189}
2190
2192 return STI.hasFeature(AMDGPU::FeatureMAIInsts);
2193}
2194
2195bool hasVOPD(const MCSubtargetInfo &STI) {
2196 return STI.hasFeature(AMDGPU::FeatureVOPD);
2197}
2198
2200 return STI.hasFeature(AMDGPU::FeatureDPPSrc1SGPR);
2201}
2202
2204 return STI.hasFeature(AMDGPU::FeatureKernargPreload);
2205}
2206
2207int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR,
2208 int32_t ArgNumVGPR) {
2209 if (has90AInsts && ArgNumAGPR)
2210 return alignTo(ArgNumVGPR, 4) + ArgNumAGPR;
2211 return std::max(ArgNumVGPR, ArgNumAGPR);
2212}
2213
2214bool isSGPR(unsigned Reg, const MCRegisterInfo* TRI) {
2215 const MCRegisterClass SGPRClass = TRI->getRegClass(AMDGPU::SReg_32RegClassID);
2216 const unsigned FirstSubReg = TRI->getSubReg(Reg, AMDGPU::sub0);
2217 return SGPRClass.contains(FirstSubReg != 0 ? FirstSubReg : Reg) ||
2218 Reg == AMDGPU::SCC;
2219}
2220
2221bool isHi(unsigned Reg, const MCRegisterInfo &MRI) {
2222 return MRI.getEncodingValue(Reg) & AMDGPU::HWEncoding::IS_HI;
2223}
2224
2225#define MAP_REG2REG \
2226 using namespace AMDGPU; \
2227 switch(Reg) { \
2228 default: return Reg; \
2229 CASE_CI_VI(FLAT_SCR) \
2230 CASE_CI_VI(FLAT_SCR_LO) \
2231 CASE_CI_VI(FLAT_SCR_HI) \
2232 CASE_VI_GFX9PLUS(TTMP0) \
2233 CASE_VI_GFX9PLUS(TTMP1) \
2234 CASE_VI_GFX9PLUS(TTMP2) \
2235 CASE_VI_GFX9PLUS(TTMP3) \
2236 CASE_VI_GFX9PLUS(TTMP4) \
2237 CASE_VI_GFX9PLUS(TTMP5) \
2238 CASE_VI_GFX9PLUS(TTMP6) \
2239 CASE_VI_GFX9PLUS(TTMP7) \
2240 CASE_VI_GFX9PLUS(TTMP8) \
2241 CASE_VI_GFX9PLUS(TTMP9) \
2242 CASE_VI_GFX9PLUS(TTMP10) \
2243 CASE_VI_GFX9PLUS(TTMP11) \
2244 CASE_VI_GFX9PLUS(TTMP12) \
2245 CASE_VI_GFX9PLUS(TTMP13) \
2246 CASE_VI_GFX9PLUS(TTMP14) \
2247 CASE_VI_GFX9PLUS(TTMP15) \
2248 CASE_VI_GFX9PLUS(TTMP0_TTMP1) \
2249 CASE_VI_GFX9PLUS(TTMP2_TTMP3) \
2250 CASE_VI_GFX9PLUS(TTMP4_TTMP5) \
2251 CASE_VI_GFX9PLUS(TTMP6_TTMP7) \
2252 CASE_VI_GFX9PLUS(TTMP8_TTMP9) \
2253 CASE_VI_GFX9PLUS(TTMP10_TTMP11) \
2254 CASE_VI_GFX9PLUS(TTMP12_TTMP13) \
2255 CASE_VI_GFX9PLUS(TTMP14_TTMP15) \
2256 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3) \
2257 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7) \
2258 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11) \
2259 CASE_VI_GFX9PLUS(TTMP12_TTMP13_TTMP14_TTMP15) \
2260 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7) \
2261 CASE_VI_GFX9PLUS(TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11) \
2262 CASE_VI_GFX9PLUS(TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2263 CASE_VI_GFX9PLUS(TTMP0_TTMP1_TTMP2_TTMP3_TTMP4_TTMP5_TTMP6_TTMP7_TTMP8_TTMP9_TTMP10_TTMP11_TTMP12_TTMP13_TTMP14_TTMP15) \
2264 CASE_GFXPRE11_GFX11PLUS(M0) \
2265 CASE_GFXPRE11_GFX11PLUS(SGPR_NULL) \
2266 CASE_GFXPRE11_GFX11PLUS_TO(SGPR_NULL64, SGPR_NULL) \
2267 }
2268
2269#define CASE_CI_VI(node) \
2270 assert(!isSI(STI)); \
2271 case node: return isCI(STI) ? node##_ci : node##_vi;
2272
2273#define CASE_VI_GFX9PLUS(node) \
2274 case node: return isGFX9Plus(STI) ? node##_gfx9plus : node##_vi;
2275
2276#define CASE_GFXPRE11_GFX11PLUS(node) \
2277 case node: return isGFX11Plus(STI) ? node##_gfx11plus : node##_gfxpre11;
2278
2279#define CASE_GFXPRE11_GFX11PLUS_TO(node, result) \
2280 case node: return isGFX11Plus(STI) ? result##_gfx11plus : result##_gfxpre11;
2281
2282unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI) {
2283 if (STI.getTargetTriple().getArch() == Triple::r600)
2284 return Reg;
2286}
2287
2288#undef CASE_CI_VI
2289#undef CASE_VI_GFX9PLUS
2290#undef CASE_GFXPRE11_GFX11PLUS
2291#undef CASE_GFXPRE11_GFX11PLUS_TO
2292
2293#define CASE_CI_VI(node) case node##_ci: case node##_vi: return node;
2294#define CASE_VI_GFX9PLUS(node) case node##_vi: case node##_gfx9plus: return node;
2295#define CASE_GFXPRE11_GFX11PLUS(node) case node##_gfx11plus: case node##_gfxpre11: return node;
2296#define CASE_GFXPRE11_GFX11PLUS_TO(node, result)
2297
2298unsigned mc2PseudoReg(unsigned Reg) {
2300}
2301
2302bool isInlineValue(unsigned Reg) {
2303 switch (Reg) {
2304 case AMDGPU::SRC_SHARED_BASE_LO:
2305 case AMDGPU::SRC_SHARED_BASE:
2306 case AMDGPU::SRC_SHARED_LIMIT_LO:
2307 case AMDGPU::SRC_SHARED_LIMIT:
2308 case AMDGPU::SRC_PRIVATE_BASE_LO:
2309 case AMDGPU::SRC_PRIVATE_BASE:
2310 case AMDGPU::SRC_PRIVATE_LIMIT_LO:
2311 case AMDGPU::SRC_PRIVATE_LIMIT:
2312 case AMDGPU::SRC_POPS_EXITING_WAVE_ID:
2313 return true;
2314 case AMDGPU::SRC_VCCZ:
2315 case AMDGPU::SRC_EXECZ:
2316 case AMDGPU::SRC_SCC:
2317 return true;
2318 case AMDGPU::SGPR_NULL:
2319 return true;
2320 default:
2321 return false;
2322 }
2323}
2324
2325#undef CASE_CI_VI
2326#undef CASE_VI_GFX9PLUS
2327#undef CASE_GFXPRE11_GFX11PLUS
2328#undef CASE_GFXPRE11_GFX11PLUS_TO
2329#undef MAP_REG2REG
2330
2331bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2332 assert(OpNo < Desc.NumOperands);
2333 unsigned OpType = Desc.operands()[OpNo].OperandType;
2334 return OpType >= AMDGPU::OPERAND_SRC_FIRST &&
2335 OpType <= AMDGPU::OPERAND_SRC_LAST;
2336}
2337
2338bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2339 assert(OpNo < Desc.NumOperands);
2340 unsigned OpType = Desc.operands()[OpNo].OperandType;
2341 return OpType >= AMDGPU::OPERAND_KIMM_FIRST &&
2342 OpType <= AMDGPU::OPERAND_KIMM_LAST;
2343}
2344
2345bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2346 assert(OpNo < Desc.NumOperands);
2347 unsigned OpType = Desc.operands()[OpNo].OperandType;
2348 switch (OpType) {
2365 return true;
2366 default:
2367 return false;
2368 }
2369}
2370
2371bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo) {
2372 assert(OpNo < Desc.NumOperands);
2373 unsigned OpType = Desc.operands()[OpNo].OperandType;
2374 return (OpType >= AMDGPU::OPERAND_REG_INLINE_C_FIRST &&
2378}
2379
2380// Avoid using MCRegisterClass::getSize, since that function will go away
2381// (move from MC* level to Target* level). Return size in bits.
2382unsigned getRegBitWidth(unsigned RCID) {
2383 switch (RCID) {
2384 case AMDGPU::SGPR_LO16RegClassID:
2385 case AMDGPU::AGPR_LO16RegClassID:
2386 return 16;
2387 case AMDGPU::SGPR_32RegClassID:
2388 case AMDGPU::VGPR_32RegClassID:
2389 case AMDGPU::VRegOrLds_32RegClassID:
2390 case AMDGPU::AGPR_32RegClassID:
2391 case AMDGPU::VS_32RegClassID:
2392 case AMDGPU::AV_32RegClassID:
2393 case AMDGPU::SReg_32RegClassID:
2394 case AMDGPU::SReg_32_XM0RegClassID:
2395 case AMDGPU::SRegOrLds_32RegClassID:
2396 return 32;
2397 case AMDGPU::SGPR_64RegClassID:
2398 case AMDGPU::VS_64RegClassID:
2399 case AMDGPU::SReg_64RegClassID:
2400 case AMDGPU::VReg_64RegClassID:
2401 case AMDGPU::AReg_64RegClassID:
2402 case AMDGPU::SReg_64_XEXECRegClassID:
2403 case AMDGPU::VReg_64_Align2RegClassID:
2404 case AMDGPU::AReg_64_Align2RegClassID:
2405 case AMDGPU::AV_64RegClassID:
2406 case AMDGPU::AV_64_Align2RegClassID:
2407 return 64;
2408 case AMDGPU::SGPR_96RegClassID:
2409 case AMDGPU::SReg_96RegClassID:
2410 case AMDGPU::VReg_96RegClassID:
2411 case AMDGPU::AReg_96RegClassID:
2412 case AMDGPU::VReg_96_Align2RegClassID:
2413 case AMDGPU::AReg_96_Align2RegClassID:
2414 case AMDGPU::AV_96RegClassID:
2415 case AMDGPU::AV_96_Align2RegClassID:
2416 return 96;
2417 case AMDGPU::SGPR_128RegClassID:
2418 case AMDGPU::SReg_128RegClassID:
2419 case AMDGPU::VReg_128RegClassID:
2420 case AMDGPU::AReg_128RegClassID:
2421 case AMDGPU::VReg_128_Align2RegClassID:
2422 case AMDGPU::AReg_128_Align2RegClassID:
2423 case AMDGPU::AV_128RegClassID:
2424 case AMDGPU::AV_128_Align2RegClassID:
2425 return 128;
2426 case AMDGPU::SGPR_160RegClassID:
2427 case AMDGPU::SReg_160RegClassID:
2428 case AMDGPU::VReg_160RegClassID:
2429 case AMDGPU::AReg_160RegClassID:
2430 case AMDGPU::VReg_160_Align2RegClassID:
2431 case AMDGPU::AReg_160_Align2RegClassID:
2432 case AMDGPU::AV_160RegClassID:
2433 case AMDGPU::AV_160_Align2RegClassID:
2434 return 160;
2435 case AMDGPU::SGPR_192RegClassID:
2436 case AMDGPU::SReg_192RegClassID:
2437 case AMDGPU::VReg_192RegClassID:
2438 case AMDGPU::AReg_192RegClassID:
2439 case AMDGPU::VReg_192_Align2RegClassID:
2440 case AMDGPU::AReg_192_Align2RegClassID:
2441 case AMDGPU::AV_192RegClassID:
2442 case AMDGPU::AV_192_Align2RegClassID:
2443 return 192;
2444 case AMDGPU::SGPR_224RegClassID:
2445 case AMDGPU::SReg_224RegClassID:
2446 case AMDGPU::VReg_224RegClassID:
2447 case AMDGPU::AReg_224RegClassID:
2448 case AMDGPU::VReg_224_Align2RegClassID:
2449 case AMDGPU::AReg_224_Align2RegClassID:
2450 case AMDGPU::AV_224RegClassID:
2451 case AMDGPU::AV_224_Align2RegClassID:
2452 return 224;
2453 case AMDGPU::SGPR_256RegClassID:
2454 case AMDGPU::SReg_256RegClassID:
2455 case AMDGPU::VReg_256RegClassID:
2456 case AMDGPU::AReg_256RegClassID:
2457 case AMDGPU::VReg_256_Align2RegClassID:
2458 case AMDGPU::AReg_256_Align2RegClassID:
2459 case AMDGPU::AV_256RegClassID:
2460 case AMDGPU::AV_256_Align2RegClassID:
2461 return 256;
2462 case AMDGPU::SGPR_288RegClassID:
2463 case AMDGPU::SReg_288RegClassID:
2464 case AMDGPU::VReg_288RegClassID:
2465 case AMDGPU::AReg_288RegClassID:
2466 case AMDGPU::VReg_288_Align2RegClassID:
2467 case AMDGPU::AReg_288_Align2RegClassID:
2468 case AMDGPU::AV_288RegClassID:
2469 case AMDGPU::AV_288_Align2RegClassID:
2470 return 288;
2471 case AMDGPU::SGPR_320RegClassID:
2472 case AMDGPU::SReg_320RegClassID:
2473 case AMDGPU::VReg_320RegClassID:
2474 case AMDGPU::AReg_320RegClassID:
2475 case AMDGPU::VReg_320_Align2RegClassID:
2476 case AMDGPU::AReg_320_Align2RegClassID:
2477 case AMDGPU::AV_320RegClassID:
2478 case AMDGPU::AV_320_Align2RegClassID:
2479 return 320;
2480 case AMDGPU::SGPR_352RegClassID:
2481 case AMDGPU::SReg_352RegClassID:
2482 case AMDGPU::VReg_352RegClassID:
2483 case AMDGPU::AReg_352RegClassID:
2484 case AMDGPU::VReg_352_Align2RegClassID:
2485 case AMDGPU::AReg_352_Align2RegClassID:
2486 case AMDGPU::AV_352RegClassID:
2487 case AMDGPU::AV_352_Align2RegClassID:
2488 return 352;
2489 case AMDGPU::SGPR_384RegClassID:
2490 case AMDGPU::SReg_384RegClassID:
2491 case AMDGPU::VReg_384RegClassID:
2492 case AMDGPU::AReg_384RegClassID:
2493 case AMDGPU::VReg_384_Align2RegClassID:
2494 case AMDGPU::AReg_384_Align2RegClassID:
2495 case AMDGPU::AV_384RegClassID:
2496 case AMDGPU::AV_384_Align2RegClassID:
2497 return 384;
2498 case AMDGPU::SGPR_512RegClassID:
2499 case AMDGPU::SReg_512RegClassID:
2500 case AMDGPU::VReg_512RegClassID:
2501 case AMDGPU::AReg_512RegClassID:
2502 case AMDGPU::VReg_512_Align2RegClassID:
2503 case AMDGPU::AReg_512_Align2RegClassID:
2504 case AMDGPU::AV_512RegClassID:
2505 case AMDGPU::AV_512_Align2RegClassID:
2506 return 512;
2507 case AMDGPU::SGPR_1024RegClassID:
2508 case AMDGPU::SReg_1024RegClassID:
2509 case AMDGPU::VReg_1024RegClassID:
2510 case AMDGPU::AReg_1024RegClassID:
2511 case AMDGPU::VReg_1024_Align2RegClassID:
2512 case AMDGPU::AReg_1024_Align2RegClassID:
2513 case AMDGPU::AV_1024RegClassID:
2514 case AMDGPU::AV_1024_Align2RegClassID:
2515 return 1024;
2516 default:
2517 llvm_unreachable("Unexpected register class");
2518 }
2519}
2520
2521unsigned getRegBitWidth(const MCRegisterClass &RC) {
2522 return getRegBitWidth(RC.getID());
2523}
2524
2526 unsigned OpNo) {
2527 assert(OpNo < Desc.NumOperands);
2528 unsigned RCID = Desc.operands()[OpNo].RegClass;
2529 return getRegBitWidth(RCID) / 8;
2530}
2531
2532bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi) {
2534 return true;
2535
2536 uint64_t Val = static_cast<uint64_t>(Literal);
2537 return (Val == llvm::bit_cast<uint64_t>(0.0)) ||
2538 (Val == llvm::bit_cast<uint64_t>(1.0)) ||
2539 (Val == llvm::bit_cast<uint64_t>(-1.0)) ||
2540 (Val == llvm::bit_cast<uint64_t>(0.5)) ||
2541 (Val == llvm::bit_cast<uint64_t>(-0.5)) ||
2542 (Val == llvm::bit_cast<uint64_t>(2.0)) ||
2543 (Val == llvm::bit_cast<uint64_t>(-2.0)) ||
2544 (Val == llvm::bit_cast<uint64_t>(4.0)) ||
2545 (Val == llvm::bit_cast<uint64_t>(-4.0)) ||
2546 (Val == 0x3fc45f306dc9c882 && HasInv2Pi);
2547}
2548
2549bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi) {
2551 return true;
2552
2553 // The actual type of the operand does not seem to matter as long
2554 // as the bits match one of the inline immediate values. For example:
2555 //
2556 // -nan has the hexadecimal encoding of 0xfffffffe which is -2 in decimal,
2557 // so it is a legal inline immediate.
2558 //
2559 // 1065353216 has the hexadecimal encoding 0x3f800000 which is 1.0f in
2560 // floating-point, so it is a legal inline immediate.
2561
2562 uint32_t Val = static_cast<uint32_t>(Literal);
2563 return (Val == llvm::bit_cast<uint32_t>(0.0f)) ||
2564 (Val == llvm::bit_cast<uint32_t>(1.0f)) ||
2565 (Val == llvm::bit_cast<uint32_t>(-1.0f)) ||
2566 (Val == llvm::bit_cast<uint32_t>(0.5f)) ||
2567 (Val == llvm::bit_cast<uint32_t>(-0.5f)) ||
2568 (Val == llvm::bit_cast<uint32_t>(2.0f)) ||
2569 (Val == llvm::bit_cast<uint32_t>(-2.0f)) ||
2570 (Val == llvm::bit_cast<uint32_t>(4.0f)) ||
2571 (Val == llvm::bit_cast<uint32_t>(-4.0f)) ||
2572 (Val == 0x3e22f983 && HasInv2Pi);
2573}
2574
2575bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi) {
2576 if (!HasInv2Pi)
2577 return false;
2579 return true;
2580 uint16_t Val = static_cast<uint16_t>(Literal);
2581 return Val == 0x3F00 || // 0.5
2582 Val == 0xBF00 || // -0.5
2583 Val == 0x3F80 || // 1.0
2584 Val == 0xBF80 || // -1.0
2585 Val == 0x4000 || // 2.0
2586 Val == 0xC000 || // -2.0
2587 Val == 0x4080 || // 4.0
2588 Val == 0xC080 || // -4.0
2589 Val == 0x3E22; // 1.0 / (2.0 * pi)
2590}
2591
2592bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi) {
2593 return isInlinableLiteral32(Literal, HasInv2Pi);
2594}
2595
2596bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi) {
2597 if (!HasInv2Pi)
2598 return false;
2600 return true;
2601 uint16_t Val = static_cast<uint16_t>(Literal);
2602 return Val == 0x3C00 || // 1.0
2603 Val == 0xBC00 || // -1.0
2604 Val == 0x3800 || // 0.5
2605 Val == 0xB800 || // -0.5
2606 Val == 0x4000 || // 2.0
2607 Val == 0xC000 || // -2.0
2608 Val == 0x4400 || // 4.0
2609 Val == 0xC400 || // -4.0
2610 Val == 0x3118; // 1/2pi
2611}
2612
2613std::optional<unsigned> getInlineEncodingV216(bool IsFloat, uint32_t Literal) {
2614 // Unfortunately, the Instruction Set Architecture Reference Guide is
2615 // misleading about how the inline operands work for (packed) 16-bit
2616 // instructions. In a nutshell, the actual HW behavior is:
2617 //
2618 // - integer encodings (-16 .. 64) are always produced as sign-extended
2619 // 32-bit values
2620 // - float encodings are produced as:
2621 // - for F16 instructions: corresponding half-precision float values in
2622 // the LSBs, 0 in the MSBs
2623 // - for UI16 instructions: corresponding single-precision float value
2624 int32_t Signed = static_cast<int32_t>(Literal);
2625 if (Signed >= 0 && Signed <= 64)
2626 return 128 + Signed;
2627
2628 if (Signed >= -16 && Signed <= -1)
2629 return 192 + std::abs(Signed);
2630
2631 if (IsFloat) {
2632 // clang-format off
2633 switch (Literal) {
2634 case 0x3800: return 240; // 0.5
2635 case 0xB800: return 241; // -0.5
2636 case 0x3C00: return 242; // 1.0
2637 case 0xBC00: return 243; // -1.0
2638 case 0x4000: return 244; // 2.0
2639 case 0xC000: return 245; // -2.0
2640 case 0x4400: return 246; // 4.0
2641 case 0xC400: return 247; // -4.0
2642 case 0x3118: return 248; // 1.0 / (2.0 * pi)
2643 default: break;
2644 }
2645 // clang-format on
2646 } else {
2647 // clang-format off
2648 switch (Literal) {
2649 case 0x3F000000: return 240; // 0.5
2650 case 0xBF000000: return 241; // -0.5
2651 case 0x3F800000: return 242; // 1.0
2652 case 0xBF800000: return 243; // -1.0
2653 case 0x40000000: return 244; // 2.0
2654 case 0xC0000000: return 245; // -2.0
2655 case 0x40800000: return 246; // 4.0
2656 case 0xC0800000: return 247; // -4.0
2657 case 0x3E22F983: return 248; // 1.0 / (2.0 * pi)
2658 default: break;
2659 }
2660 // clang-format on
2661 }
2662
2663 return {};
2664}
2665
2666// Encoding of the literal as an inline constant for a V_PK_*_IU16 instruction
2667// or nullopt.
2668std::optional<unsigned> getInlineEncodingV2I16(uint32_t Literal) {
2669 return getInlineEncodingV216(false, Literal);
2670}
2671
2672// Encoding of the literal as an inline constant for a V_PK_*_BF16 instruction
2673// or nullopt.
2674std::optional<unsigned> getInlineEncodingV2BF16(uint32_t Literal) {
2675 int32_t Signed = static_cast<int32_t>(Literal);
2676 if (Signed >= 0 && Signed <= 64)
2677 return 128 + Signed;
2678
2679 if (Signed >= -16 && Signed <= -1)
2680 return 192 + std::abs(Signed);
2681
2682 // clang-format off
2683 switch (Literal) {
2684 case 0x3F00: return 240; // 0.5
2685 case 0xBF00: return 241; // -0.5
2686 case 0x3F80: return 242; // 1.0
2687 case 0xBF80: return 243; // -1.0
2688 case 0x4000: return 244; // 2.0
2689 case 0xC000: return 245; // -2.0
2690 case 0x4080: return 246; // 4.0
2691 case 0xC080: return 247; // -4.0
2692 case 0x3E22: return 248; // 1.0 / (2.0 * pi)
2693 default: break;
2694 }
2695 // clang-format on
2696
2697 return std::nullopt;
2698}
2699
2700// Encoding of the literal as an inline constant for a V_PK_*_F16 instruction
2701// or nullopt.
2702std::optional<unsigned> getInlineEncodingV2F16(uint32_t Literal) {
2703 return getInlineEncodingV216(true, Literal);
2704}
2705
2706// Whether the given literal can be inlined for a V_PK_* instruction.
2708 switch (OpType) {
2712 return getInlineEncodingV216(false, Literal).has_value();
2716 return getInlineEncodingV216(true, Literal).has_value();
2721 default:
2722 llvm_unreachable("bad packed operand type");
2723 }
2724}
2725
2726// Whether the given literal can be inlined for a V_PK_*_IU16 instruction.
2728 return getInlineEncodingV2I16(Literal).has_value();
2729}
2730
2731// Whether the given literal can be inlined for a V_PK_*_BF16 instruction.
2733 return getInlineEncodingV2BF16(Literal).has_value();
2734}
2735
2736// Whether the given literal can be inlined for a V_PK_*_F16 instruction.
2738 return getInlineEncodingV2F16(Literal).has_value();
2739}
2740
2741bool isValid32BitLiteral(uint64_t Val, bool IsFP64) {
2742 if (IsFP64)
2743 return !(Val & 0xffffffffu);
2744
2745 return isUInt<32>(Val) || isInt<32>(Val);
2746}
2747
2749 const Function *F = A->getParent();
2750
2751 // Arguments to compute shaders are never a source of divergence.
2752 CallingConv::ID CC = F->getCallingConv();
2753 switch (CC) {
2756 return true;
2767 // For non-compute shaders, SGPR inputs are marked with either inreg or
2768 // byval. Everything else is in VGPRs.
2769 return A->hasAttribute(Attribute::InReg) ||
2770 A->hasAttribute(Attribute::ByVal);
2771 default:
2772 // TODO: treat i1 as divergent?
2773 return A->hasAttribute(Attribute::InReg);
2774 }
2775}
2776
2777bool isArgPassedInSGPR(const CallBase *CB, unsigned ArgNo) {
2778 // Arguments to compute shaders are never a source of divergence.
2780 switch (CC) {
2783 return true;
2794 // For non-compute shaders, SGPR inputs are marked with either inreg or
2795 // byval. Everything else is in VGPRs.
2796 return CB->paramHasAttr(ArgNo, Attribute::InReg) ||
2797 CB->paramHasAttr(ArgNo, Attribute::ByVal);
2798 default:
2799 return CB->paramHasAttr(ArgNo, Attribute::InReg);
2800 }
2801}
2802
2803static bool hasSMEMByteOffset(const MCSubtargetInfo &ST) {
2804 return isGCN3Encoding(ST) || isGFX10Plus(ST);
2805}
2806
2808 return isGFX9Plus(ST);
2809}
2810
2812 int64_t EncodedOffset) {
2813 if (isGFX12Plus(ST))
2814 return isUInt<23>(EncodedOffset);
2815
2816 return hasSMEMByteOffset(ST) ? isUInt<20>(EncodedOffset)
2817 : isUInt<8>(EncodedOffset);
2818}
2819
2821 int64_t EncodedOffset,
2822 bool IsBuffer) {
2823 if (isGFX12Plus(ST))
2824 return isInt<24>(EncodedOffset);
2825
2826 return !IsBuffer &&
2828 isInt<21>(EncodedOffset);
2829}
2830
2831static bool isDwordAligned(uint64_t ByteOffset) {
2832 return (ByteOffset & 3) == 0;
2833}
2834
2836 uint64_t ByteOffset) {
2837 if (hasSMEMByteOffset(ST))
2838 return ByteOffset;
2839
2840 assert(isDwordAligned(ByteOffset));
2841 return ByteOffset >> 2;
2842}
2843
2844std::optional<int64_t> getSMRDEncodedOffset(const MCSubtargetInfo &ST,
2845 int64_t ByteOffset, bool IsBuffer) {
2846 if (isGFX12Plus(ST)) // 24 bit signed offsets
2847 return isInt<24>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2848 : std::nullopt;
2849
2850 // The signed version is always a byte offset.
2851 if (!IsBuffer && hasSMRDSignedImmOffset(ST)) {
2853 return isInt<20>(ByteOffset) ? std::optional<int64_t>(ByteOffset)
2854 : std::nullopt;
2855 }
2856
2857 if (!isDwordAligned(ByteOffset) && !hasSMEMByteOffset(ST))
2858 return std::nullopt;
2859
2860 int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
2861 return isLegalSMRDEncodedUnsignedOffset(ST, EncodedOffset)
2862 ? std::optional<int64_t>(EncodedOffset)
2863 : std::nullopt;
2864}
2865
2866std::optional<int64_t> getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST,
2867 int64_t ByteOffset) {
2868 if (!isCI(ST) || !isDwordAligned(ByteOffset))
2869 return std::nullopt;
2870
2871 int64_t EncodedOffset = convertSMRDOffsetUnits(ST, ByteOffset);
2872 return isUInt<32>(EncodedOffset) ? std::optional<int64_t>(EncodedOffset)
2873 : std::nullopt;
2874}
2875
2877 if (AMDGPU::isGFX10(ST))
2878 return 12;
2879
2880 if (AMDGPU::isGFX12(ST))
2881 return 24;
2882 return 13;
2883}
2884
2885namespace {
2886
2887struct SourceOfDivergence {
2888 unsigned Intr;
2889};
2890const SourceOfDivergence *lookupSourceOfDivergence(unsigned Intr);
2891
2892struct AlwaysUniform {
2893 unsigned Intr;
2894};
2895const AlwaysUniform *lookupAlwaysUniform(unsigned Intr);
2896
2897#define GET_SourcesOfDivergence_IMPL
2898#define GET_UniformIntrinsics_IMPL
2899#define GET_Gfx9BufferFormat_IMPL
2900#define GET_Gfx10BufferFormat_IMPL
2901#define GET_Gfx11PlusBufferFormat_IMPL
2902#include "AMDGPUGenSearchableTables.inc"
2903
2904} // end anonymous namespace
2905
2906bool isIntrinsicSourceOfDivergence(unsigned IntrID) {
2907 return lookupSourceOfDivergence(IntrID);
2908}
2909
2910bool isIntrinsicAlwaysUniform(unsigned IntrID) {
2911 return lookupAlwaysUniform(IntrID);
2912}
2913
2915 uint8_t NumComponents,
2916 uint8_t NumFormat,
2917 const MCSubtargetInfo &STI) {
2918 return isGFX11Plus(STI)
2919 ? getGfx11PlusBufferFormatInfo(BitsPerComp, NumComponents,
2920 NumFormat)
2921 : isGFX10(STI) ? getGfx10BufferFormatInfo(BitsPerComp,
2922 NumComponents, NumFormat)
2923 : getGfx9BufferFormatInfo(BitsPerComp,
2924 NumComponents, NumFormat);
2925}
2926
2928 const MCSubtargetInfo &STI) {
2929 return isGFX11Plus(STI) ? getGfx11PlusBufferFormatInfo(Format)
2930 : isGFX10(STI) ? getGfx10BufferFormatInfo(Format)
2931 : getGfx9BufferFormatInfo(Format);
2932}
2933
2935 for (auto OpName : { OpName::vdst, OpName::src0, OpName::src1,
2936 OpName::src2 }) {
2937 int Idx = getNamedOperandIdx(OpDesc.getOpcode(), OpName);
2938 if (Idx == -1)
2939 continue;
2940
2941 if (OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64RegClassID ||
2942 OpDesc.operands()[Idx].RegClass == AMDGPU::VReg_64_Align2RegClassID)
2943 return true;
2944 }
2945
2946 return false;
2947}
2948
2949bool isDPALU_DPP(const MCInstrDesc &OpDesc) {
2950 return hasAny64BitVGPROperands(OpDesc);
2951}
2952
2954 // Currently this is 128 for all subtargets
2955 return 128;
2956}
2957
2958} // namespace AMDGPU
2959
2962 switch (S) {
2964 OS << "Unsupported";
2965 break;
2967 OS << "Any";
2968 break;
2970 OS << "Off";
2971 break;
2973 OS << "On";
2974 break;
2975 }
2976 return OS;
2977}
2978
2979} // namespace llvm
unsigned const MachineRegisterInfo * MRI
#define MAP_REG2REG
unsigned Intr
static llvm::cl::opt< unsigned > DefaultAMDHSACodeObjectVersion("amdhsa-code-object-version", llvm::cl::Hidden, llvm::cl::init(llvm::AMDGPU::AMDHSA_COV5), llvm::cl::desc("Set default AMDHSA Code Object Version (module flag " "or asm directive still take priority if present)"))
Provides AMDGPU specific target descriptions.
AMDHSA kernel descriptor definitions.
@ AMD_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32
This file contains the simple types necessary to represent the attributes associated with functions a...
static GCRegistry::Add< ErlangGC > A("erlang", "erlang-compatible garbage collector")
Analysis containing CSE Info
Definition: CSEInfo.cpp:27
This file contains the declarations for the subclasses of Constant, which represent the different fla...
Returns the sub type a function will return at a given Idx Should correspond to the result type of an ExtractValue instruction executed with just that one unsigned Idx
std::string Name
uint64_t Size
#define F(x, y, z)
Definition: MD5.cpp:55
unsigned const TargetRegisterInfo * TRI
unsigned Reg
return NewInfo
#define S_00B848_MEM_ORDERED(x)
Definition: SIDefines.h:1150
#define S_00B848_WGP_MODE(x)
Definition: SIDefines.h:1147
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
raw_pwrite_stream & OS
This file contains some functions that are useful when dealing with strings.
void setTargetIDFromFeaturesString(StringRef FS)
TargetIDSetting getXnackSetting() const
AMDGPUTargetID(const MCSubtargetInfo &STI)
void setTargetIDFromTargetIDStream(StringRef TargetID)
TargetIDSetting getSramEccSetting() const
unsigned getIndexInParsedOperands(unsigned CompOprIdx) const
unsigned getIndexOfDstInParsedOperands() const
unsigned getIndexOfSrcInParsedOperands(unsigned CompSrcIdx) const
unsigned getCompParsedSrcOperandsNum() const
std::optional< unsigned > getInvalidCompOperandIndex(std::function< unsigned(unsigned, unsigned)> GetRegIdx, bool SkipSrc=false) const
std::array< unsigned, Component::MAX_OPR_NUM > RegIndices
Definition: Any.h:28
This class represents an incoming formal argument to a Function.
Definition: Argument.h:31
Base class for all callable instructions (InvokeInst and CallInst) Holds everything related to callin...
Definition: InstrTypes.h:1494
CallingConv::ID getCallingConv() const
Definition: InstrTypes.h:1800
bool paramHasAttr(unsigned ArgNo, Attribute::AttrKind Kind) const
Determine whether the argument or parameter has the given attribute.
This class represents an Operation in the Expression.
constexpr bool test(unsigned I) const
unsigned getAddressSpace() const
Definition: GlobalValue.h:205
This is an important class for using LLVM in a threaded context.
Definition: LLVMContext.h:67
void emitError(uint64_t LocCookie, const Twine &ErrorStr)
emitError - Emit an error message to the currently installed error handler with optional location inf...
Describe properties that are true of each instruction in the target description file.
Definition: MCInstrDesc.h:198
unsigned getNumOperands() const
Return the number of declared MachineOperands for this MachineInstruction.
Definition: MCInstrDesc.h:237
ArrayRef< MCOperandInfo > operands() const
Definition: MCInstrDesc.h:239
unsigned getNumDefs() const
Return the number of MachineOperands that are register definitions.
Definition: MCInstrDesc.h:248
int getOperandConstraint(unsigned OpNum, MCOI::OperandConstraint Constraint) const
Returns the value of the specified operand constraint if it is present.
Definition: MCInstrDesc.h:219
unsigned getOpcode() const
Return the opcode number for this descriptor.
Definition: MCInstrDesc.h:230
Interface to description of machine instruction set.
Definition: MCInstrInfo.h:26
const MCInstrDesc & get(unsigned Opcode) const
Return the machine instruction descriptor that corresponds to the specified instruction opcode.
Definition: MCInstrInfo.h:63
MCRegisterClass - Base class of TargetRegisterClass.
unsigned getID() const
getID() - Return the register class ID number.
bool contains(MCRegister Reg) const
contains - Return true if the specified register is included in this register class.
MCRegisterInfo base class - We assume that the target defines a static array of MCRegisterDesc object...
Generic base class for all target subtargets.
bool hasFeature(unsigned Feature) const
const Triple & getTargetTriple() const
const FeatureBitset & getFeatureBits() const
StringRef getCPU() const
A Module instance is used to store all the information related to an LLVM module.
Definition: Module.h:65
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
Definition: SmallVector.h:1209
A wrapper around a string literal that serves as a proxy for constructing global tables of StringRefs...
Definition: StringRef.h:845
StringRef - Represent a constant reference to a string, i.e.
Definition: StringRef.h:50
std::pair< StringRef, StringRef > split(char Separator) const
Split into two substrings around the first occurrence of a separator character.
Definition: StringRef.h:692
bool getAsInteger(unsigned Radix, T &Result) const
Parse the current string as an integer of the specified radix.
Definition: StringRef.h:462
std::string str() const
str - Get the contents as an std::string.
Definition: StringRef.h:222
constexpr bool empty() const
empty - Check if the string is empty.
Definition: StringRef.h:134
constexpr size_t size() const
size - Get the string size.
Definition: StringRef.h:137
bool ends_with(StringRef Suffix) const
Check if this string ends with the given Suffix.
Definition: StringRef.h:269
Manages the enabling and disabling of subtarget specific features.
const std::vector< std::string > & getFeatures() const
Returns the vector of individual subtarget features.
Triple - Helper class for working with autoconf configuration names.
Definition: Triple.h:44
OSType getOS() const
Get the parsed operating system type of this triple.
Definition: Triple.h:382
ArchType getArch() const
Get the parsed architecture type of this triple.
Definition: Triple.h:373
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
Definition: Twine.h:81
This class implements an extremely fast bulk output stream that can only output to a stream.
Definition: raw_ostream.h:52
A raw_ostream that writes to an std::string.
Definition: raw_ostream.h:660
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
@ CONSTANT_ADDRESS_32BIT
Address space for 32-bit constant memory.
@ LOCAL_ADDRESS
Address space for local memory.
@ CONSTANT_ADDRESS
Address space for constant memory (VTX2).
@ GLOBAL_ADDRESS
Address space for global memory (RAT0, VTX0).
bool decodeDepCtr(unsigned Code, int &Id, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
unsigned encodeFieldVaVdst(unsigned Encoded, unsigned VaVdst)
unsigned decodeFieldSaSdst(unsigned Encoded)
unsigned encodeFieldVmVsrc(unsigned Encoded, unsigned VmVsrc)
int encodeDepCtr(const StringRef Name, int64_t Val, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned encodeFieldSaSdst(unsigned Encoded, unsigned SaSdst)
const CustomOperandVal DepCtrInfo[]
bool isSymbolicDepCtrEncoding(unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
unsigned decodeFieldVaVdst(unsigned Encoded)
int getDefaultDepCtrEncoding(const MCSubtargetInfo &STI)
unsigned decodeFieldVmVsrc(unsigned Encoded)
bool isSupportedTgtId(unsigned Id, const MCSubtargetInfo &STI)
static constexpr ExpTgt ExpTgtInfo[]
bool getTgtName(unsigned Id, StringRef &Name, int &Index)
unsigned getTgtId(const StringRef Name)
constexpr uint32_t VersionMajor
HSA metadata major version.
unsigned getVGPREncodingGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumVGPRs(const MCSubtargetInfo *STI)
unsigned getWavesPerEUForWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getWavefrontSize(const MCSubtargetInfo *STI)
unsigned getMaxWorkGroupsPerCU(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getMaxFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxWavesPerEU(const MCSubtargetInfo *STI)
unsigned getWavesPerWorkGroup(const MCSubtargetInfo *STI, unsigned FlatWorkGroupSize)
unsigned getNumExtraSGPRs(const MCSubtargetInfo *STI, bool VCCUsed, bool FlatScrUsed, bool XNACKUsed)
unsigned getSGPREncodingGranule(const MCSubtargetInfo *STI)
unsigned getLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getAddressableLocalMemorySize(const MCSubtargetInfo *STI)
unsigned getMinNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEUsPerCU(const MCSubtargetInfo *STI)
unsigned getAddressableNumSGPRs(const MCSubtargetInfo *STI)
unsigned getAddressableNumVGPRs(const MCSubtargetInfo *STI)
unsigned getMinNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
static TargetIDSetting getTargetIDSettingFromFeatureString(StringRef FeatureString)
unsigned getMinFlatWorkGroupSize(const MCSubtargetInfo *STI)
unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, bool Addressable)
unsigned getNumSGPRBlocks(const MCSubtargetInfo *STI, unsigned NumSGPRs)
unsigned getMinWavesPerEU(const MCSubtargetInfo *STI)
unsigned getSGPRAllocGranule(const MCSubtargetInfo *STI)
unsigned getNumWavesPerEUWithNumVGPRs(const MCSubtargetInfo *STI, unsigned NumVGPRs)
unsigned getMaxNumVGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU)
unsigned getEncodedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getOccupancyWithNumSGPRs(unsigned SGPRs, unsigned MaxWaves, AMDGPUSubtarget::Generation Gen)
static unsigned getGranulatedNumRegisterBlocks(unsigned NumRegs, unsigned Granule)
unsigned getVGPRAllocGranule(const MCSubtargetInfo *STI, std::optional< bool > EnableWavefrontSize32)
unsigned getAddressableNumArchVGPRs(const MCSubtargetInfo *STI)
unsigned getAllocatedNumVGPRBlocks(const MCSubtargetInfo *STI, unsigned NumVGPRs, std::optional< bool > EnableWavefrontSize32)
unsigned getTotalNumSGPRs(const MCSubtargetInfo *STI)
StringLiteral const UfmtSymbolicGFX11[]
bool isValidUnifiedFormat(unsigned Id, const MCSubtargetInfo &STI)
unsigned getDefaultFormatEncoding(const MCSubtargetInfo &STI)
StringRef getUnifiedFormatName(unsigned Id, const MCSubtargetInfo &STI)
unsigned const DfmtNfmt2UFmtGFX10[]
StringLiteral const DfmtSymbolic[]
static StringLiteral const * getNfmtLookupTable(const MCSubtargetInfo &STI)
bool isValidNfmt(unsigned Id, const MCSubtargetInfo &STI)
StringLiteral const NfmtSymbolicGFX10[]
bool isValidDfmtNfmt(unsigned Id, const MCSubtargetInfo &STI)
int64_t convertDfmtNfmt2Ufmt(unsigned Dfmt, unsigned Nfmt, const MCSubtargetInfo &STI)
StringRef getDfmtName(unsigned Id)
int64_t encodeDfmtNfmt(unsigned Dfmt, unsigned Nfmt)
int64_t getUnifiedFormat(const StringRef Name, const MCSubtargetInfo &STI)
bool isValidFormatEncoding(unsigned Val, const MCSubtargetInfo &STI)
StringRef getNfmtName(unsigned Id, const MCSubtargetInfo &STI)
unsigned const DfmtNfmt2UFmtGFX11[]
StringLiteral const NfmtSymbolicVI[]
StringLiteral const NfmtSymbolicSICI[]
int64_t getNfmt(const StringRef Name, const MCSubtargetInfo &STI)
int64_t getDfmt(const StringRef Name)
StringLiteral const UfmtSymbolicGFX10[]
void decodeDfmtNfmt(unsigned Format, unsigned &Dfmt, unsigned &Nfmt)
uint64_t encodeMsg(uint64_t MsgId, uint64_t OpId, uint64_t StreamId)
bool msgSupportsStream(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI)
void decodeMsg(unsigned Val, uint16_t &MsgId, uint16_t &OpId, uint16_t &StreamId, const MCSubtargetInfo &STI)
bool isValidMsgId(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgStream(int64_t MsgId, int64_t OpId, int64_t StreamId, const MCSubtargetInfo &STI, bool Strict)
StringRef getMsgOpName(int64_t MsgId, uint64_t Encoding, const MCSubtargetInfo &STI)
Map from an encoding to the symbolic name for a sendmsg operation.
static uint64_t getMsgIdMask(const MCSubtargetInfo &STI)
bool msgRequiresOp(int64_t MsgId, const MCSubtargetInfo &STI)
bool isValidMsgOp(int64_t MsgId, int64_t OpId, const MCSubtargetInfo &STI, bool Strict)
constexpr unsigned VOPD_VGPR_BANK_MASKS[]
constexpr unsigned COMPONENTS_NUM
bool isGCN3Encoding(const MCSubtargetInfo &STI)
bool isInlinableLiteralBF16(int16_t Literal, bool HasInv2Pi)
bool isGFX10_BEncoding(const MCSubtargetInfo &STI)
bool isGFX10_GFX11(const MCSubtargetInfo &STI)
bool isInlinableLiteralV216(uint32_t Literal, uint8_t OpType)
LLVM_READONLY const MIMGInfo * getMIMGInfo(unsigned Opc)
unsigned getRegOperandSize(const MCRegisterInfo *MRI, const MCInstrDesc &Desc, unsigned OpNo)
Get size of register operand.
void decodeWaitcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned &Vmcnt, unsigned &Expcnt, unsigned &Lgkmcnt)
Decodes Vmcnt, Expcnt and Lgkmcnt from given Waitcnt for given isa Version, and writes decoded values...
bool isInlinableLiteralFP16(int16_t Literal, bool HasInv2Pi)
SmallVector< unsigned > getIntegerVecAttribute(const Function &F, StringRef Name, unsigned Size)
uint64_t convertSMRDOffsetUnits(const MCSubtargetInfo &ST, uint64_t ByteOffset)
Convert ByteOffset to dwords if the subtarget uses dword SMRD immediate offsets.
static unsigned encodeStorecnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Storecnt)
static bool hasSMRDSignedImmOffset(const MCSubtargetInfo &ST)
static bool hasSMEMByteOffset(const MCSubtargetInfo &ST)
bool isVOPCAsmOnly(unsigned Opc)
int getMIMGOpcode(unsigned BaseOpcode, unsigned MIMGEncoding, unsigned VDataDwords, unsigned VAddrDwords)
bool getMTBUFHasSrsrc(unsigned Opc)
std::optional< int64_t > getSMRDEncodedLiteralOffset32(const MCSubtargetInfo &ST, int64_t ByteOffset)
static bool isSymbolicCustomOperandEncoding(const CustomOperandVal *Opr, int Size, unsigned Code, bool &HasNonDefaultVal, const MCSubtargetInfo &STI)
bool isGFX10Before1030(const MCSubtargetInfo &STI)
bool isSISrcInlinableOperand(const MCInstrDesc &Desc, unsigned OpNo)
Does this operand support only inlinable literals?
unsigned mapWMMA2AddrTo3AddrOpcode(unsigned Opc)
const int OPR_ID_UNSUPPORTED
bool shouldEmitConstantsToTextSection(const Triple &TT)
bool isInlinableLiteralV2I16(uint32_t Literal)
int getMTBUFElements(unsigned Opc)
static int encodeCustomOperandVal(const CustomOperandVal &Op, int64_t InputVal)
int32_t getTotalNumVGPRs(bool has90AInsts, int32_t ArgNumAGPR, int32_t ArgNumVGPR)
bool isGFX10(const MCSubtargetInfo &STI)
LLVM_READONLY int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx)
void initDefaultAMDKernelCodeT(amd_kernel_code_t &Header, const MCSubtargetInfo *STI)
bool isInlinableLiteralV2BF16(uint32_t Literal)
unsigned getMaxNumUserSGPRs(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV216(bool IsFloat, uint32_t Literal)
unsigned getNumFlatOffsetBits(const MCSubtargetInfo &ST)
For pre-GFX12 FLAT instructions the offset must be positive; MSB is ignored and forced to zero.
unsigned mc2PseudoReg(unsigned Reg)
Convert hardware register Reg to a pseudo register.
bool hasA16(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedSignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset, bool IsBuffer)
bool isGFX12Plus(const MCSubtargetInfo &STI)
unsigned getNSAMaxSize(const MCSubtargetInfo &STI, bool HasSampler)
CanBeVOPD getCanBeVOPD(unsigned Opc)
bool hasPackedD16(const MCSubtargetInfo &STI)
unsigned getStorecntBitMask(const IsaVersion &Version)
unsigned getLdsDwGranularity(const MCSubtargetInfo &ST)
bool isGFX940(const MCSubtargetInfo &STI)
bool isEntryFunctionCC(CallingConv::ID CC)
bool isInlinableLiteralV2F16(uint32_t Literal)
bool isHsaAbi(const MCSubtargetInfo &STI)
bool isGFX11(const MCSubtargetInfo &STI)
const int OPR_VAL_INVALID
bool getSMEMIsBuffer(unsigned Opc)
bool isGFX10_3_GFX11(const MCSubtargetInfo &STI)
bool isGroupSegment(const GlobalValue *GV)
IsaVersion getIsaVersion(StringRef GPU)
bool getMTBUFHasSoffset(unsigned Opc)
bool hasXNACK(const MCSubtargetInfo &STI)
bool isValid32BitLiteral(uint64_t Val, bool IsFP64)
static unsigned getCombinedCountBitMask(const IsaVersion &Version, bool IsStore)
unsigned getVOPDOpcode(unsigned Opc)
bool isDPALU_DPP(const MCInstrDesc &OpDesc)
unsigned encodeWaitcnt(const IsaVersion &Version, unsigned Vmcnt, unsigned Expcnt, unsigned Lgkmcnt)
Encodes Vmcnt, Expcnt and Lgkmcnt into Waitcnt for given isa Version.
bool isVOPC64DPP(unsigned Opc)
int getMUBUFOpcode(unsigned BaseOpc, unsigned Elements)
bool isCompute(CallingConv::ID cc)
bool getMAIIsGFX940XDL(unsigned Opc)
bool isSI(const MCSubtargetInfo &STI)
unsigned getDefaultAMDHSACodeObjectVersion()
bool isReadOnlySegment(const GlobalValue *GV)
bool isArgPassedInSGPR(const Argument *A)
bool isIntrinsicAlwaysUniform(unsigned IntrID)
int getMUBUFBaseOpcode(unsigned Opc)
unsigned getAMDHSACodeObjectVersion(const Module &M)
unsigned decodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt)
unsigned getWaitcntBitMask(const IsaVersion &Version)
bool getVOP3IsSingle(unsigned Opc)
bool isGFX9(const MCSubtargetInfo &STI)
bool getVOP1IsSingle(unsigned Opc)
static bool isDwordAligned(uint64_t ByteOffset)
unsigned getVOPDEncodingFamily(const MCSubtargetInfo &ST)
bool isGFX10_AEncoding(const MCSubtargetInfo &STI)
bool isKImmOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this a KImm operand?
bool getHasColorExport(const Function &F)
int getMTBUFBaseOpcode(unsigned Opc)
bool isChainCC(CallingConv::ID CC)
bool isGFX90A(const MCSubtargetInfo &STI)
unsigned getSamplecntBitMask(const IsaVersion &Version)
unsigned getDefaultQueueImplicitArgPosition(unsigned CodeObjectVersion)
bool hasSRAMECC(const MCSubtargetInfo &STI)
bool getHasDepthExport(const Function &F)
bool isGFX8_GFX9_GFX10(const MCSubtargetInfo &STI)
bool getMUBUFHasVAddr(unsigned Opc)
int getVOPDFull(unsigned OpX, unsigned OpY, unsigned EncodingFamily)
bool isTrue16Inst(unsigned Opc)
bool hasAny64BitVGPROperands(const MCInstrDesc &OpDesc)
std::pair< unsigned, unsigned > getVOPDComponents(unsigned VOPDOpcode)
bool isInlinableLiteral32(int32_t Literal, bool HasInv2Pi)
bool isGFX12(const MCSubtargetInfo &STI)
unsigned getInitialPSInputAddr(const Function &F)
unsigned encodeExpcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Expcnt)
bool isSISrcOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this an AMDGPU specific source operand? These include registers, inline constants,...
unsigned getKmcntBitMask(const IsaVersion &Version)
unsigned getVmcntBitMask(const IsaVersion &Version)
bool isNotGFX10Plus(const MCSubtargetInfo &STI)
bool hasMAIInsts(const MCSubtargetInfo &STI)
bool isIntrinsicSourceOfDivergence(unsigned IntrID)
bool isKernelCC(const Function *Func)
bool isGenericAtomic(unsigned Opc)
Waitcnt decodeStorecntDscnt(const IsaVersion &Version, unsigned StorecntDscnt)
bool isGFX8Plus(const MCSubtargetInfo &STI)
LLVM_READONLY bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx)
LLVM_READNONE bool isInlinableIntLiteral(int64_t Literal)
Is this literal inlinable, and not one of the values intended for floating point values.
unsigned getLgkmcntBitMask(const IsaVersion &Version)
bool getMUBUFTfe(unsigned Opc)
std::optional< int64_t > getSMRDEncodedOffset(const MCSubtargetInfo &ST, int64_t ByteOffset, bool IsBuffer)
bool isSGPR(unsigned Reg, const MCRegisterInfo *TRI)
Is Reg - scalar register.
bool isHi(unsigned Reg, const MCRegisterInfo &MRI)
unsigned getBvhcntBitMask(const IsaVersion &Version)
bool hasMIMG_R128(const MCSubtargetInfo &STI)
bool hasGFX10_3Insts(const MCSubtargetInfo &STI)
bool hasG16(const MCSubtargetInfo &STI)
unsigned getAddrSizeMIMGOp(const MIMGBaseOpcodeInfo *BaseOpcode, const MIMGDimInfo *Dim, bool IsA16, bool IsG16Supported)
int getMTBUFOpcode(unsigned BaseOpc, unsigned Elements)
unsigned getExpcntBitMask(const IsaVersion &Version)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool getMUBUFHasSoffset(unsigned Opc)
bool isNotGFX11Plus(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
std::optional< unsigned > getInlineEncodingV2F16(uint32_t Literal)
bool isInlineValue(unsigned Reg)
bool isSISrcFPOperand(const MCInstrDesc &Desc, unsigned OpNo)
Is this floating-point operand?
bool isShader(CallingConv::ID cc)
unsigned getHostcallImplicitArgPosition(unsigned CodeObjectVersion)
static unsigned getDefaultCustomOperandEncoding(const CustomOperandVal *Opr, int Size, const MCSubtargetInfo &STI)
static unsigned encodeLoadcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Loadcnt)
bool isGFX10Plus(const MCSubtargetInfo &STI)
unsigned getMCReg(unsigned Reg, const MCSubtargetInfo &STI)
If Reg is a pseudo reg, return the correct hardware register given STI otherwise return Reg.
static bool decodeCustomOperand(const CustomOperandVal *Opr, int Size, unsigned Code, int &Idx, StringRef &Name, unsigned &Val, bool &IsDefault, const MCSubtargetInfo &STI)
bool isGlobalSegment(const GlobalValue *GV)
@ OPERAND_KIMM_LAST
Definition: SIDefines.h:269
@ OPERAND_KIMM32
Operand with 32-bit immediate that uses the constant bus.
Definition: SIDefines.h:234
@ OPERAND_REG_INLINE_C_LAST
Definition: SIDefines.h:260
@ OPERAND_REG_IMM_V2FP16
Definition: SIDefines.h:211
@ OPERAND_REG_INLINE_C_FP64
Definition: SIDefines.h:223
@ OPERAND_REG_INLINE_C_V2BF16
Definition: SIDefines.h:225
@ OPERAND_REG_IMM_V2INT16
Definition: SIDefines.h:212
@ OPERAND_REG_INLINE_AC_V2FP16
Definition: SIDefines.h:246
@ OPERAND_SRC_FIRST
Definition: SIDefines.h:265
@ OPERAND_REG_IMM_V2BF16
Definition: SIDefines.h:210
@ OPERAND_REG_INLINE_AC_FIRST
Definition: SIDefines.h:262
@ OPERAND_KIMM_FIRST
Definition: SIDefines.h:268
@ OPERAND_REG_IMM_FP16
Definition: SIDefines.h:206
@ OPERAND_REG_IMM_FP64
Definition: SIDefines.h:204
@ OPERAND_REG_INLINE_C_V2FP16
Definition: SIDefines.h:226
@ OPERAND_REG_INLINE_AC_V2INT16
Definition: SIDefines.h:244
@ OPERAND_REG_INLINE_AC_FP16
Definition: SIDefines.h:241
@ OPERAND_REG_INLINE_AC_FP32
Definition: SIDefines.h:242
@ OPERAND_REG_INLINE_AC_V2BF16
Definition: SIDefines.h:245
@ OPERAND_REG_IMM_FP32
Definition: SIDefines.h:203
@ OPERAND_REG_INLINE_C_FIRST
Definition: SIDefines.h:259
@ OPERAND_REG_INLINE_C_FP32
Definition: SIDefines.h:222
@ OPERAND_REG_INLINE_AC_LAST
Definition: SIDefines.h:263
@ OPERAND_REG_INLINE_C_V2INT16
Definition: SIDefines.h:224
@ OPERAND_REG_IMM_V2FP32
Definition: SIDefines.h:214
@ OPERAND_REG_INLINE_AC_FP64
Definition: SIDefines.h:243
@ OPERAND_REG_INLINE_C_FP16
Definition: SIDefines.h:221
@ OPERAND_REG_INLINE_C_V2FP32
Definition: SIDefines.h:228
@ OPERAND_REG_IMM_FP32_DEFERRED
Definition: SIDefines.h:209
@ OPERAND_SRC_LAST
Definition: SIDefines.h:266
@ OPERAND_REG_IMM_FP16_DEFERRED
Definition: SIDefines.h:208
bool isNotGFX9Plus(const MCSubtargetInfo &STI)
bool hasGDS(const MCSubtargetInfo &STI)
bool isLegalSMRDEncodedUnsignedOffset(const MCSubtargetInfo &ST, int64_t EncodedOffset)
bool isGFX9Plus(const MCSubtargetInfo &STI)
bool hasDPPSrc1SGPR(const MCSubtargetInfo &STI)
const int OPR_ID_DUPLICATE
bool isVOPD(unsigned Opc)
VOPD::InstInfo getVOPDInstInfo(const MCInstrDesc &OpX, const MCInstrDesc &OpY)
unsigned encodeVmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Vmcnt)
unsigned decodeExpcnt(const IsaVersion &Version, unsigned Waitcnt)
bool isCvt_F32_Fp8_Bf8_e64(unsigned Opc)
Waitcnt decodeLoadcntDscnt(const IsaVersion &Version, unsigned LoadcntDscnt)
std::optional< unsigned > getInlineEncodingV2I16(uint32_t Literal)
unsigned getRegBitWidth(const TargetRegisterClass &RC)
Get the size in bits of a register from the register class RC.
static unsigned encodeStorecntDscnt(const IsaVersion &Version, unsigned Storecnt, unsigned Dscnt)
int getMCOpcode(uint16_t Opcode, unsigned Gen)
const MIMGBaseOpcodeInfo * getMIMGBaseOpcode(unsigned Opc)
bool isVI(const MCSubtargetInfo &STI)
bool getMUBUFIsBufferInv(unsigned Opc)
std::optional< unsigned > getInlineEncodingV2BF16(uint32_t Literal)
static int encodeCustomOperand(const CustomOperandVal *Opr, int Size, const StringRef Name, int64_t InputVal, unsigned &UsedOprMask, const MCSubtargetInfo &STI)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
bool isMAC(unsigned Opc)
bool isCI(const MCSubtargetInfo &STI)
unsigned encodeLgkmcnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Lgkmcnt)
bool getVOP2IsSingle(unsigned Opc)
bool getMAIIsDGEMM(unsigned Opc)
Returns true if MAI operation is a double precision GEMM.
LLVM_READONLY const MIMGBaseOpcodeInfo * getMIMGBaseOpcodeInfo(unsigned BaseOpcode)
const int OPR_ID_UNKNOWN
unsigned getCompletionActionImplicitArgPosition(unsigned CodeObjectVersion)
int getMaskedMIMGOp(unsigned Opc, unsigned NewChannels)
bool isModuleEntryFunctionCC(CallingConv::ID CC)
bool isNotGFX12Plus(const MCSubtargetInfo &STI)
bool getMTBUFHasVAddr(unsigned Opc)
unsigned decodeVmcnt(const IsaVersion &Version, unsigned Waitcnt)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
std::pair< unsigned, unsigned > getIntegerPairAttribute(const Function &F, StringRef Name, std::pair< unsigned, unsigned > Default, bool OnlyFirstRequired)
unsigned getLoadcntBitMask(const IsaVersion &Version)
bool isInlinableLiteralI16(int32_t Literal, bool HasInv2Pi)
bool hasVOPD(const MCSubtargetInfo &STI)
static unsigned encodeDscnt(const IsaVersion &Version, unsigned Waitcnt, unsigned Dscnt)
bool isInlinableLiteral64(int64_t Literal, bool HasInv2Pi)
Is this literal inlinable.
unsigned getMultigridSyncArgImplicitArgPosition(unsigned CodeObjectVersion)
bool isGFX9_GFX10_GFX11(const MCSubtargetInfo &STI)
bool isGFX9_GFX10(const MCSubtargetInfo &STI)
int getMUBUFElements(unsigned Opc)
static unsigned encodeLoadcntDscnt(const IsaVersion &Version, unsigned Loadcnt, unsigned Dscnt)
const GcnBufferFormatInfo * getGcnBufferFormatInfo(uint8_t BitsPerComp, uint8_t NumComponents, uint8_t NumFormat, const MCSubtargetInfo &STI)
bool isGraphics(CallingConv::ID cc)
unsigned mapWMMA3AddrTo2AddrOpcode(unsigned Opc)
bool isPermlane16(unsigned Opc)
bool getMUBUFHasSrsrc(unsigned Opc)
unsigned getDscntBitMask(const IsaVersion &Version)
constexpr std::underlying_type_t< E > Mask()
Get a bitmask with 1s in all places up to the high-order bit of E's largest value.
Definition: BitmaskEnum.h:121
unsigned ID
LLVM IR allows to use arbitrary numbers as calling convention identifiers.
Definition: CallingConv.h:24
@ AMDGPU_CS
Used for Mesa/AMDPAL compute shaders.
Definition: CallingConv.h:197
@ AMDGPU_VS
Used for Mesa vertex shaders, or AMDPAL last shader stage before rasterization (vertex shader if tess...
Definition: CallingConv.h:188
@ AMDGPU_KERNEL
Used for AMDGPU code object kernels.
Definition: CallingConv.h:200
@ AMDGPU_Gfx
Used for AMD graphics targets.
Definition: CallingConv.h:232
@ AMDGPU_CS_ChainPreserve
Used on AMDGPUs to give the middle-end more control over argument placement.
Definition: CallingConv.h:249
@ AMDGPU_HS
Used for Mesa/AMDPAL hull shaders (= tessellation control shaders).
Definition: CallingConv.h:206
@ AMDGPU_GS
Used for Mesa/AMDPAL geometry shaders.
Definition: CallingConv.h:191
@ AMDGPU_CS_Chain
Used on AMDGPUs to give the middle-end more control over argument placement.
Definition: CallingConv.h:245
@ AMDGPU_PS
Used for Mesa/AMDPAL pixel shaders.
Definition: CallingConv.h:194
@ SPIR_KERNEL
Used for SPIR kernel functions.
Definition: CallingConv.h:144
@ AMDGPU_ES
Used for AMDPAL shader stage before geometry shader if geometry is in use.
Definition: CallingConv.h:218
@ AMDGPU_LS
Used for AMDPAL vertex shader if tessellation is in use.
Definition: CallingConv.h:213
@ ELFABIVERSION_AMDGPU_HSA_V4
Definition: ELF.h:378
@ ELFABIVERSION_AMDGPU_HSA_V5
Definition: ELF.h:379
@ ELFABIVERSION_AMDGPU_HSA_V6
Definition: ELF.h:380
initializer< Ty > init(const Ty &Val)
Definition: CommandLine.h:450
This is an optimization pass for GlobalISel generic memory operations.
Definition: AddressRanges.h:18
uint64_t divideCeil(uint64_t Numerator, uint64_t Denominator)
Returns the integer ceil(Numerator / Denominator).
Definition: MathExtras.h:428
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Definition: Error.cpp:156
raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
uint64_t alignTo(uint64_t Size, Align A)
Returns a multiple of A needed to store Size bytes.
Definition: Alignment.h:155
raw_ostream & operator<<(raw_ostream &OS, const APFixedPoint &FX)
Definition: APFixedPoint.h:293
uint64_t alignDown(uint64_t Value, uint64_t Align, uint64_t Skew=0)
Returns the largest uint64_t less than or equal to Value and is Skew mod Align.
Definition: MathExtras.h:439
@ AlwaysUniform
The result values are always uniform.
@ Default
The result values are uniform if and only if all operands are uniform.
#define N
AMD Kernel Code Object (amd_kernel_code_t).
Instruction set architecture version.
Definition: TargetParser.h:125
Represents the counter values to wait for in an s_waitcnt instruction.
Description of the encoding of one expression Op.