LLVM 19.0.0git
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#include "Target/RISCV/RISCVISelDAGToDAG.h"
Public Member Functions | |
RISCVDAGToDAGISel ()=delete | |
RISCVDAGToDAGISel (RISCVTargetMachine &TargetMachine, CodeGenOptLevel OptLevel) | |
bool | runOnMachineFunction (MachineFunction &MF) override |
void | PreprocessISelDAG () override |
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts. | |
void | PostprocessISelDAG () override |
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection. | |
void | Select (SDNode *Node) override |
Main hook for targets to transform nodes into machine nodes. | |
bool | SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) override |
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint. | |
bool | SelectAddrFrameIndex (SDValue Addr, SDValue &Base, SDValue &Offset) |
bool | SelectFrameAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset) |
bool | SelectAddrRegImm (SDValue Addr, SDValue &Base, SDValue &Offset, bool IsINX=false) |
bool | SelectAddrRegImmINX (SDValue Addr, SDValue &Base, SDValue &Offset) |
bool | SelectAddrRegImmLsb00000 (SDValue Addr, SDValue &Base, SDValue &Offset) |
Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros. | |
bool | SelectAddrRegRegScale (SDValue Addr, unsigned MaxShiftAmount, SDValue &Base, SDValue &Index, SDValue &Scale) |
template<unsigned MaxShift> | |
bool | SelectAddrRegRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale) |
template<unsigned MaxShift, unsigned Bits> | |
bool | SelectAddrRegZextRegScale (SDValue Addr, SDValue &Base, SDValue &Index, SDValue &Scale) |
bool | tryShrinkShlLogicImm (SDNode *Node) |
bool | trySignedBitfieldExtract (SDNode *Node) |
bool | tryIndexedLoad (SDNode *Node) |
bool | selectShiftMask (SDValue N, unsigned ShiftWidth, SDValue &ShAmt) |
bool | selectShiftMaskXLen (SDValue N, SDValue &ShAmt) |
bool | selectShiftMask32 (SDValue N, SDValue &ShAmt) |
bool | selectSETCC (SDValue N, ISD::CondCode ExpectedCCVal, SDValue &Val) |
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0. | |
bool | selectSETNE (SDValue N, SDValue &Val) |
bool | selectSETEQ (SDValue N, SDValue &Val) |
bool | selectSExtBits (SDValue N, unsigned Bits, SDValue &Val) |
template<unsigned Bits> | |
bool | selectSExtBits (SDValue N, SDValue &Val) |
bool | selectZExtBits (SDValue N, unsigned Bits, SDValue &Val) |
template<unsigned Bits> | |
bool | selectZExtBits (SDValue N, SDValue &Val) |
bool | selectSHXADDOp (SDValue N, unsigned ShAmt, SDValue &Val) |
Look for various patterns that can be done with a SHL that can be folded into a SHXADD. | |
template<unsigned ShAmt> | |
bool | selectSHXADDOp (SDValue N, SDValue &Val) |
bool | selectSHXADD_UWOp (SDValue N, unsigned ShAmt, SDValue &Val) |
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW. | |
template<unsigned ShAmt> | |
bool | selectSHXADD_UWOp (SDValue N, SDValue &Val) |
bool | hasAllNBitUsers (SDNode *Node, unsigned Bits, const unsigned Depth=0) const |
bool | hasAllBUsers (SDNode *Node) const |
bool | hasAllHUsers (SDNode *Node) const |
bool | hasAllWUsers (SDNode *Node) const |
bool | selectSimm5Shl2 (SDValue N, SDValue &Simm5, SDValue &Shl2) |
bool | selectVLOp (SDValue N, SDValue &VL) |
bool | selectVSplat (SDValue N, SDValue &SplatVal) |
bool | selectVSplatSimm5 (SDValue N, SDValue &SplatVal) |
bool | selectVSplatUimm (SDValue N, unsigned Bits, SDValue &SplatVal) |
template<unsigned Bits> | |
bool | selectVSplatUimmBits (SDValue N, SDValue &Val) |
bool | selectVSplatSimm5Plus1 (SDValue N, SDValue &SplatVal) |
bool | selectVSplatSimm5Plus1NonZero (SDValue N, SDValue &SplatVal) |
bool | selectLow8BitsVSplat (SDValue N, SDValue &SplatVal) |
bool | selectFPImm (SDValue N, SDValue &Imm) |
bool | selectRVVSimm5 (SDValue N, unsigned Width, SDValue &Imm) |
template<unsigned Width> | |
bool | selectRVVSimm5 (SDValue N, SDValue &Imm) |
void | addVectorLoadStoreOperands (SDNode *Node, unsigned SEWImm, const SDLoc &DL, unsigned CurOp, bool IsMasked, bool IsStridedOrIndexed, SmallVectorImpl< SDValue > &Operands, bool IsLoad=false, MVT *IndexVT=nullptr) |
void | selectVLSEG (SDNode *Node, bool IsMasked, bool IsStrided) |
void | selectVLSEGFF (SDNode *Node, bool IsMasked) |
void | selectVLXSEG (SDNode *Node, bool IsMasked, bool IsOrdered) |
void | selectVSSEG (SDNode *Node, bool IsMasked, bool IsStrided) |
void | selectVSXSEG (SDNode *Node, bool IsMasked, bool IsOrdered) |
void | selectVSETVLI (SDNode *Node) |
void | selectSF_VC_X_SE (SDNode *Node) |
Public Member Functions inherited from llvm::SelectionDAGISel | |
SelectionDAGISel (TargetMachine &tm, CodeGenOptLevel OL=CodeGenOptLevel::Default) | |
virtual | ~SelectionDAGISel () |
const TargetLowering * | getTargetLowering () const |
void | initializeAnalysisResults (MachineFunctionAnalysisManager &MFAM) |
void | initializeAnalysisResults (MachineFunctionPass &MFP) |
virtual bool | runOnMachineFunction (MachineFunction &mf) |
virtual void | emitFunctionEntryCode () |
virtual void | PreprocessISelDAG () |
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts. | |
virtual void | PostprocessISelDAG () |
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection. | |
virtual void | Select (SDNode *N)=0 |
Main hook for targets to transform nodes into machine nodes. | |
virtual bool | SelectInlineAsmMemoryOperand (const SDValue &Op, InlineAsm::ConstraintCode ConstraintID, std::vector< SDValue > &OutOps) |
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint. | |
virtual bool | IsProfitableToFold (SDValue N, SDNode *U, SDNode *Root) const |
IsProfitableToFold - Returns true if it's profitable to fold the specific operand node N of U during instruction selection that starts at Root. | |
bool | CheckAndMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const |
CheckAndMask - The isel is trying to match something like (and X, 255). | |
bool | CheckOrMask (SDValue LHS, ConstantSDNode *RHS, int64_t DesiredMaskS) const |
CheckOrMask - The isel is trying to match something like (or X, 255). | |
virtual bool | CheckPatternPredicate (unsigned PredNo) const |
CheckPatternPredicate - This function is generated by tblgen in the target. | |
virtual bool | CheckNodePredicate (SDNode *N, unsigned PredNo) const |
CheckNodePredicate - This function is generated by tblgen in the target. | |
virtual bool | CheckNodePredicateWithOperands (SDNode *N, unsigned PredNo, const SmallVectorImpl< SDValue > &Operands) const |
CheckNodePredicateWithOperands - This function is generated by tblgen in the target. | |
virtual bool | CheckComplexPattern (SDNode *Root, SDNode *Parent, SDValue N, unsigned PatternNo, SmallVectorImpl< std::pair< SDValue, SDNode * > > &Result) |
virtual SDValue | RunSDNodeXForm (SDValue V, unsigned XFormNo) |
void | SelectCodeCommon (SDNode *NodeToMatch, const unsigned char *MatcherTable, unsigned TableSize) |
virtual bool | ComplexPatternFuncMutatesDAG () const |
Return true if complex patterns for this target can mutate the DAG. | |
bool | mayRaiseFPException (SDNode *Node) const |
Return whether the node may raise an FP exception. | |
bool | isOrEquivalentToAdd (const SDNode *N) const |
Static Public Member Functions | |
static RISCVCC::CondCode | getRISCVCCForIntCC (ISD::CondCode CC) |
Static Public Member Functions inherited from llvm::SelectionDAGISel | |
static bool | IsLegalToFold (SDValue N, SDNode *U, SDNode *Root, CodeGenOptLevel OptLevel, bool IgnoreChains=false) |
IsLegalToFold - Returns true if the specific operand node N of U can be folded during instruction selection that starts at Root. | |
static void | InvalidateNodeId (SDNode *N) |
static int | getUninvalidatedNodeId (SDNode *N) |
static void | EnforceNodeIdInvariant (SDNode *N) |
static int | getNumFixedFromVariadicInfo (unsigned Flags) |
getNumFixedFromVariadicInfo - Transform an EmitNode flags word into the number of fixed arity values that should be skipped when copying from the root. | |
Definition at line 24 of file RISCVISelDAGToDAG.h.
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delete |
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inlineexplicit |
Definition at line 30 of file RISCVISelDAGToDAG.h.
void RISCVDAGToDAGISel::addVectorLoadStoreOperands | ( | SDNode * | Node, |
unsigned | SEWImm, | ||
const SDLoc & | DL, | ||
unsigned | CurOp, | ||
bool | IsMasked, | ||
bool | IsStridedOrIndexed, | ||
SmallVectorImpl< SDValue > & | Operands, | ||
bool | IsLoad = false , |
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MVT * | IndexVT = nullptr |
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) |
Definition at line 293 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValue(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVII::MASK_AGNOSTIC, Operands, and selectVLOp().
Referenced by Select(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSSEG(), and selectVSXSEG().
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inlinestatic |
Definition at line 167 of file RISCVISelDAGToDAG.h.
References CC, llvm::RISCVCC::COND_EQ, llvm::RISCVCC::COND_GE, llvm::RISCVCC::COND_GEU, llvm::RISCVCC::COND_LT, llvm::RISCVCC::COND_LTU, llvm::RISCVCC::COND_NE, llvm_unreachable, llvm::ISD::SETEQ, llvm::ISD::SETGE, llvm::ISD::SETLT, llvm::ISD::SETNE, llvm::ISD::SETUGE, and llvm::ISD::SETULT.
Definition at line 122 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
Referenced by Select().
Definition at line 123 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
Referenced by Select().
bool RISCVDAGToDAGISel::hasAllNBitUsers | ( | SDNode * | Node, |
unsigned | Bits, | ||
const unsigned | Depth = 0 |
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) | const |
Definition at line 3026 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::bit_width(), llvm::Depth, llvm::User::getOperand(), llvm::RISCVSubtarget::getXLen(), hasAllNBitUsers(), llvm::Log2_32(), llvm::SelectionDAG::MaxRecursionDepth, llvm::ISD::MUL, llvm::ISD::OR, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::ISD::SRL, llvm::ISD::SUB, llvm::SelectionDAGISel::TII, vectorPseudoHasAllNBitUsers(), and llvm::ISD::XOR.
Referenced by hasAllBUsers(), hasAllHUsers(), hasAllNBitUsers(), and hasAllWUsers().
Definition at line 124 of file RISCVISelDAGToDAG.h.
References hasAllNBitUsers().
Referenced by Select().
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overridevirtual |
PostprocessISelDAG() - This hook allows the target to hack on the graph right after selection.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 140 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getRoot(), N, llvm::SelectionDAG::RemoveDeadNodes(), and llvm::SelectionDAG::setRoot().
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overridevirtual |
PreprocessISelDAG - This hook allows targets to hack on the graph before instruction selection starts.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 49 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::allnodes_begin(), llvm::SelectionDAG::allnodes_end(), llvm::ISD::ANY_EXTEND, assert(), llvm::SelectionDAG::CreateStackTemporary(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), DL, llvm::SelectionDAG::getEntryNode(), llvm::TypeSize::getFixed(), llvm::MachinePointerInfo::getFixedStack(), llvm::SelectionDAG::getMachineFunction(), llvm::SelectionDAG::getMemBasePlusOffset(), llvm::SelectionDAG::getMemIntrinsicNode(), llvm::SDValue::getNode(), llvm::SelectionDAG::getNode(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getStore(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getUNDEF(), llvm::MVT::getVectorElementType(), llvm::SelectionDAG::getVTList(), llvm::MachinePointerInfo::getWithOffset(), llvm::RISCVSubtarget::getXLenVT(), llvm::Hi, llvm::ISD::INTRINSIC_W_CHAIN, llvm::MVT::isInteger(), llvm::MVT::isScalableVector(), LLVM_DEBUG, llvm::Lo, llvm::SelectionDAGISel::MF, llvm::MachineMemOperand::MOLoad, N, llvm::SelectionDAG::RemoveDeadNodes(), llvm::SelectionDAG::ReplaceAllUsesOfValueWith(), llvm::ISD::SPLAT_VECTOR, llvm::RISCVISD::SPLAT_VECTOR_SPLIT_I64_VL, llvm::ISD::TokenFactor, llvm::RISCVISD::VFMV_V_F_VL, and llvm::RISCVISD::VMV_V_X_VL.
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inlineoverridevirtual |
Reimplemented from llvm::SelectionDAGISel.
Definition at line 34 of file RISCVISelDAGToDAG.h.
References llvm::MachineFunction::getSubtarget(), llvm::SelectionDAGISel::MF, and llvm::SelectionDAGISel::runOnMachineFunction().
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overridevirtual |
Main hook for targets to transform nodes into machine nodes.
Implements llvm::SelectionDAGISel.
Definition at line 877 of file RISCVISelDAGToDAG.cpp.
References addVectorLoadStoreOperands(), llvm::ISD::AND, assert(), llvm::bit_width(), llvm::ISD::BITCAST, llvm::APFloat::bitcastToAPInt(), llvm::RISCVISD::BuildPairF64, llvm::CallingConv::C, CASE_VMSLT_OPCODES, CASE_VMSLT_VMNAND_VMSET_OPCODES, CASE_VMXOR_VMANDN_VMOR_OPCODES, llvm::ISD::Constant, llvm::ISD::ConstantFP, llvm::countr_one(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, llvm::dbgs(), llvm::RISCVTargetLowering::decomposeSubvectorInsertExtractToSubRegs(), DL, llvm::RISCVSubtarget::expandVScale(), llvm::ISD::EXTRACT_SUBVECTOR, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getCopyFromReg(), llvm::SelectionDAG::getCopyToReg(), llvm::SelectionDAG::getEntryNode(), llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::TargetMachine::getOptLevel(), llvm::RISCVTargetLowering::getRegClassIDForVecVT(), llvm::SelectionDAG::getRegister(), llvm::RISCVSubtarget::getRegisterInfo(), llvm::TypeSize::getScalable(), llvm::MVT::getScalarSizeInBits(), llvm::APInt::getSExtValue(), llvm::SDValue::getSimpleValueType(), llvm::MVT::getSizeInBits(), llvm::EVT::getStoreSize(), llvm::MVT::getStoreSize(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::SelectionDAG::getTargetInsertSubreg(), llvm::RISCVSubtarget::getTargetLowering(), llvm::SDValue::getValue(), llvm::SDValue::getValueType(), llvm::MVT::getVectorElementCount(), llvm::MVT::getVectorElementType(), llvm::RISCVSubtarget::getXLen(), llvm::RISCVSubtarget::getXLenVT(), hasAllBUsers(), hasAllHUsers(), hasAllWUsers(), llvm::SDValue::hasOneUse(), llvm::Hi, Idx, llvm::ISD::INSERT_SUBVECTOR, llvm::ISD::INTRINSIC_VOID, llvm::ISD::INTRINSIC_W_CHAIN, llvm::ISD::INTRINSIC_WO_CHAIN, llvm::RISCVSubtarget::is64Bit(), llvm::MVT::isFixedLengthVector(), llvm::SelectionDAGISel::IsLegalToFold(), llvm::isMask_64(), llvm::APFloat::isNegZero(), llvm::isOneConstant(), llvm::APFloat::isPosZero(), llvm::isPowerOf2_64(), llvm::SelectionDAGISel::IsProfitableToFold(), llvm::MVT::isScalableVector(), llvm::isShiftedMask_64(), llvm::APFloat::isZero(), LLVM_DEBUG, llvm_unreachable, llvm::RISCVII::LMUL_F2, llvm::RISCVII::LMUL_F4, llvm::RISCVII::LMUL_F8, llvm::Lo, llvm::ISD::LOAD, llvm::Log2_32(), llvm::M1(), llvm::RISCVII::MASK_AGNOSTIC, llvm::MachineMemOperand::MONonTemporal, llvm::MONontemporalBit0, llvm::MONontemporalBit1, llvm::ISD::MUL, N, Operands, llvm::ISD::OR, P, llvm::ISD::PREFETCH, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), llvm::RISCVFPRndMode::RNE, llvm::RISCV::RVVBitsPerBlock, selectImm(), selectSF_VC_X_SE(), selectVLOp(), selectVLSEG(), selectVLSEGFF(), selectVLXSEG(), selectVSETVLI(), selectVSSEG(), selectVSXSEG(), llvm::MachineMemOperand::setFlags(), llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, llvm::MVT::SimpleTy, llvm::RISCVISD::SplitF64, llvm::ISD::SRA, llvm::ISD::SRL, llvm::RISCVII::TAIL_AGNOSTIC, llvm::SelectionDAGISel::TLI, llvm::SelectionDAGISel::TM, TRI, tryIndexedLoad(), tryShrinkShlLogicImm(), trySignedBitfieldExtract(), llvm::RISCVISD::VFMV_S_F_VL, llvm::RISCVISD::VFMV_V_F_VL, llvm::RISCVISD::VMV_S_X_VL, llvm::RISCVISD::VMV_V_X_VL, X, and llvm::ISD::XOR.
Definition at line 2350 of file RISCVISelDAGToDAG.cpp.
References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), and llvm::Offset.
Referenced by SelectAddrRegImm(), SelectAddrRegImmLsb00000(), and SelectFrameAddrRegImm().
bool RISCVDAGToDAGISel::SelectAddrRegImm | ( | SDValue | Addr, |
SDValue & | Base, | ||
SDValue & | Offset, | ||
bool | IsINX = false |
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) |
Definition at line 2514 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::RISCVISD::ADD_LO, Addr, assert(), llvm::sampleprof::Base, llvm::commonAlignment(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getDataLayout(), llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::getTargetGlobalAddress(), llvm::SDValue::getValueType(), llvm::SelectionDAG::isBaseWithConstantOffset(), isWorthFoldingAdd(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().
Referenced by SelectAddrRegImmINX(), and SelectInlineAsmMemoryOperand().
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inline |
Definition at line 52 of file RISCVISelDAGToDAG.h.
References Addr, llvm::sampleprof::Base, llvm::Offset, and SelectAddrRegImm().
Similar to SelectAddrRegImm, except that the least significant 5 bits of Offset shoule be all zeros.
Definition at line 2608 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, Addr, assert(), llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::Offset, SelectAddrFrameIndex(), and selectConstantAddr().
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inline |
Definition at line 61 of file RISCVISelDAGToDAG.h.
References Addr, llvm::sampleprof::Base, and SelectAddrRegRegScale().
bool RISCVDAGToDAGISel::SelectAddrRegRegScale | ( | SDValue | Addr, |
unsigned | MaxShiftAmount, | ||
SDValue & | Base, | ||
SDValue & | Index, | ||
SDValue & | Scale | ||
) |
Definition at line 2460 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::ISD::SHL.
Referenced by SelectAddrRegRegScale(), and SelectAddrRegZextRegScale().
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inline |
Definition at line 67 of file RISCVISelDAGToDAG.h.
References Addr, llvm::ISD::AND, llvm::sampleprof::Base, llvm::CallingConv::C, and SelectAddrRegRegScale().
Definition at line 3338 of file RISCVISelDAGToDAG.cpp.
References assert(), llvm::APFloat::bitcastToAPInt(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getSExtValue(), llvm::SDNode::getSimpleValueType(), llvm::ConstantFPSDNode::getValueAPF(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::is64Bit(), llvm::APFloat::isNegZero(), llvm::APFloat::isPosZero(), N, selectImm(), and llvm::SelectionDAGISel::TLI.
Definition at line 2362 of file RISCVISelDAGToDAG.cpp.
References Addr, llvm::sampleprof::Base, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::SelectionDAG::getTargetFrameIndex(), llvm::RISCVSubtarget::getXLenVT(), llvm::SelectionDAG::isBaseWithConstantOffset(), llvm::Offset, and SelectAddrFrameIndex().
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overridevirtual |
SelectInlineAsmMemoryOperand - Select the specified address as a target addressing mode, according to the specified constraint.
If this does not match or is not implemented, return true. The resultant operands (which will appear in the machine instruction) should be added to the OutOps vector.
Reimplemented from llvm::SelectionDAGISel.
Definition at line 2322 of file RISCVISelDAGToDAG.cpp.
References llvm::InlineAsm::A, assert(), llvm::SelectionDAGISel::CurDAG, llvm::InlineAsm::getMemConstraintName(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::InlineAsm::m, llvm::InlineAsm::o, llvm::report_fatal_error(), and SelectAddrRegImm().
Definition at line 3312 of file RISCVISelDAGToDAG.cpp.
References N, selectVSplat(), llvm::ISD::SIGN_EXTEND, llvm::RISCVISD::TRUNCATE_VECTOR_VL, llvm::RISCVISD::VSEXT_VL, llvm::RISCVISD::VZEXT_VL, and llvm::ISD::ZERO_EXTEND.
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inline |
Definition at line 144 of file RISCVISelDAGToDAG.h.
References N, and selectRVVSimm5().
Definition at line 3368 of file RISCVISelDAGToDAG.cpp.
References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), N, and llvm::SignExtend64().
Referenced by selectRVVSimm5().
bool RISCVDAGToDAGISel::selectSETCC | ( | SDValue | N, |
ISD::CondCode | ExpectedCCVal, | ||
SDValue & | Val | ||
) |
RISC-V doesn't have general instructions for integer setne/seteq, but we can check for equality with 0.
This function emits instructions that convert the seteq/setne into something that can be compared with 0. ExpectedCCVal
indicates the condition code to attempt to match (e.g. ISD::SETNE).
Definition at line 2749 of file RISCVISelDAGToDAG.cpp.
References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::ISD::isIntEqualitySetCC(), llvm::isNullConstant(), LHS, N, RHS, and llvm::ISD::SETCC.
Referenced by selectSETEQ(), and selectSETNE().
Definition at line 97 of file RISCVISelDAGToDAG.h.
References N, selectSETCC(), and llvm::ISD::SETEQ.
Definition at line 94 of file RISCVISelDAGToDAG.h.
References N, selectSETCC(), and llvm::ISD::SETNE.
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inline |
Definition at line 102 of file RISCVISelDAGToDAG.h.
References N, and selectSExtBits().
Definition at line 2808 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAG::ComputeNumSignBits(), llvm::SelectionDAGISel::CurDAG, llvm::SDValue::getConstantOperandVal(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::MVT::getSizeInBits(), N, llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::SRA.
Referenced by selectSExtBits().
void RISCVDAGToDAGISel::selectSF_VC_X_SE | ( | SDNode * | Node | ) |
Definition at line 818 of file RISCVISelDAGToDAG.cpp.
References assert(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), llvm::ISD::INTRINSIC_VOID, llvm::Log2_32(), Operands, and llvm::SelectionDAGISel::ReplaceNode().
Referenced by Select().
Definition at line 2672 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::ADD, llvm::ISD::AND, assert(), llvm::SelectionDAG::computeKnownBits(), llvm::SelectionDAGISel::CurDAG, DL, llvm::APInt::getBitWidth(), llvm::SDValue::getConstantOperandAPInt(), llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDNode::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getRegister(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::isPowerOf2_32(), llvm::APInt::isSubsetOf(), N, llvm::ISD::SUB, llvm::KnownBits::Zero, and llvm::ISD::ZERO_EXTEND.
Referenced by selectShiftMask32(), and selectShiftMaskXLen().
Definition at line 89 of file RISCVISelDAGToDAG.h.
References N, and selectShiftMask().
Definition at line 86 of file RISCVISelDAGToDAG.h.
References llvm::RISCVSubtarget::getXLen(), N, and selectShiftMask().
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Definition at line 116 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADD_UWOp().
Look for various patterns that can be done with a SHL that can be folded into a SHXADD_UW.
ShAmt
contains 1, 2, or 3 and is set based on which SHXADD_UW we are trying to match.
Definition at line 2953 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::countl_zero(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, and llvm::ISD::SHL.
Referenced by selectSHXADD_UWOp().
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Definition at line 111 of file RISCVISelDAGToDAG.h.
References N, and selectSHXADDOp().
Look for various patterns that can be done with a SHL that can be folded into a SHXADD.
ShAmt
contains 1, 2, or 3 and is set based on which SHXADD we are trying to match.
Definition at line 2858 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::bit_width(), llvm::countr_zero(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SDValue::getConstantOperandVal(), llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLen(), llvm::SDValue::hasOneUse(), llvm::isShiftedMask_64(), N, llvm::ISD::SHL, and llvm::ISD::SRL.
Referenced by selectSHXADDOp().
Definition at line 3184 of file RISCVISelDAGToDAG.cpp.
References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::SelectionDAG::getTargetConstant(), N, and llvm::Offset.
Definition at line 3208 of file RISCVISelDAGToDAG.cpp.
References llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, getReg(), llvm::SelectionDAG::getTargetConstant(), N, and llvm::RISCV::VLMaxSentinel.
Referenced by addVectorLoadStoreOperands(), and Select().
Definition at line 339 of file RISCVISelDAGToDAG.cpp.
References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), I, llvm::Log2_32(), Merge, Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), and llvm::SelectionDAG::setNodeMemRefs().
Referenced by Select().
Definition at line 379 of file RISCVISelDAGToDAG.cpp.
References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::RISCVSubtarget::getXLenVT(), I, llvm::Log2_32(), Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), and llvm::SelectionDAG::setNodeMemRefs().
Referenced by Select().
Definition at line 421 of file RISCVISelDAGToDAG.cpp.
References addVectorLoadStoreOperands(), assert(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::RISCVTargetLowering::getSubregIndexByMVT(), llvm::SelectionDAG::getTargetExtractSubreg(), llvm::MVT::getVectorElementCount(), I, llvm::RISCVSubtarget::is64Bit(), llvm::Log2_32(), Operands, P, llvm::SelectionDAG::RemoveDeadNode(), llvm::SelectionDAGISel::ReplaceUses(), llvm::report_fatal_error(), and llvm::SelectionDAG::setNodeMemRefs().
Referenced by Select().
void RISCVDAGToDAGISel::selectVSETVLI | ( | SDNode * | Node | ) |
Definition at line 546 of file RISCVISelDAGToDAG.cpp.
References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::RISCVVType::decodeVSEW(), DL, llvm::RISCVVType::encodeVTYPE(), llvm::SelectionDAG::getMachineNode(), llvm::RISCVSubtarget::getRealVLen(), llvm::SelectionDAG::getRegister(), llvm::RISCVVType::getSEWLMULRatio(), llvm::SelectionDAG::getTargetConstant(), llvm::RISCVSubtarget::getXLenVT(), llvm::RISCVSubtarget::hasVInstructions(), llvm::ISD::INTRINSIC_WO_CHAIN, llvm::isAllOnesConstant(), llvm::Offset, and llvm::SelectionDAGISel::ReplaceNode().
Referenced by Select().
Definition at line 3247 of file RISCVISelDAGToDAG.cpp.
References findVSplat(), N, and llvm::Splat.
Referenced by selectLow8BitsVSplat().
Definition at line 3286 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatImmHelper().
Definition at line 3291 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatImmHelper().
Definition at line 3297 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, N, and selectVSplatImmHelper().
Definition at line 3305 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, llvm::isUIntN(), N, and selectVSplatImmHelper().
Referenced by selectVSplatUimmBits().
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Definition at line 133 of file RISCVISelDAGToDAG.h.
References N, and selectVSplatUimm().
Definition at line 472 of file RISCVISelDAGToDAG.cpp.
References addVectorLoadStoreOperands(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::Log2_32(), Operands, P, llvm::SelectionDAGISel::ReplaceNode(), and llvm::SelectionDAG::setNodeMemRefs().
Referenced by Select().
Definition at line 504 of file RISCVISelDAGToDAG.cpp.
References addVectorLoadStoreOperands(), assert(), createTuple(), llvm::SelectionDAGISel::CurDAG, DL, llvm::RISCVTargetLowering::getLMUL(), llvm::SelectionDAG::getMachineNode(), llvm::MVT::getScalarSizeInBits(), llvm::MVT::getVectorElementCount(), llvm::RISCVSubtarget::is64Bit(), llvm::Log2_32(), Operands, P, llvm::SelectionDAGISel::ReplaceNode(), llvm::report_fatal_error(), and llvm::SelectionDAG::setNodeMemRefs().
Referenced by Select().
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Definition at line 106 of file RISCVISelDAGToDAG.h.
References N, and selectZExtBits().
Definition at line 2837 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::APInt::getBitsSetFrom(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::MaskedValueIsZero(), and N.
Referenced by selectZExtBits().
Definition at line 749 of file RISCVISelDAGToDAG.cpp.
References assert(), llvm::CallingConv::C, llvm::SelectionDAGISel::CurDAG, llvm::LSBaseSDNode::getAddressingMode(), llvm::LoadSDNode::getBasePtr(), llvm::MemSDNode::getChain(), llvm::LoadSDNode::getExtensionType(), llvm::SelectionDAG::getMachineNode(), llvm::MemSDNode::getMemoryVT(), llvm::LoadSDNode::getOffset(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::getValueType(), llvm::SDNode::getValueType(), llvm::Offset, llvm::ISD::POST_INC, llvm::ISD::PRE_INC, llvm::SelectionDAGISel::ReplaceNode(), llvm::SelectionDAG::setNodeMemRefs(), llvm::ISD::UNINDEXED, and llvm::ISD::ZEXTLOAD.
Referenced by Select().
Definition at line 604 of file RISCVISelDAGToDAG.cpp.
References llvm::ISD::AND, assert(), llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::ConstantSDNode::getSExtValue(), llvm::SelectionDAG::getTargetConstant(), llvm::ConstantSDNode::getZExtValue(), llvm::SDValue::hasOneUse(), llvm_unreachable, llvm::ISD::OR, llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SHL, llvm::ISD::SIGN_EXTEND_INREG, and llvm::ISD::XOR.
Referenced by Select().
Definition at line 682 of file RISCVISelDAGToDAG.cpp.
References llvm::SelectionDAGISel::CurDAG, DL, llvm::SelectionDAG::getMachineNode(), llvm::SDValue::getOpcode(), llvm::SDValue::getOperand(), llvm::SDNode::getOperand(), llvm::MVT::getSizeInBits(), llvm::SelectionDAG::getTargetConstant(), llvm::SDValue::hasOneUse(), llvm::SelectionDAGISel::ReplaceNode(), llvm::ISD::SHL, and llvm::ISD::SIGN_EXTEND_INREG.
Referenced by Select().