42 cl::desc(
"Force a specific generic_v<N> flag to be "
43 "added. For testing purposes only."),
48 if (!HSAMetadataDoc.
fromYAML(HSAMetadataString))
233 OS <<
"\t.amdgcn_target \"" <<
getTargetID()->toString() <<
"\"\n";
239 OS <<
"\t.amdhsa_code_object_version " << COV <<
'\n';
243 OS <<
"\t.amd_kernel_code_t\n";
245 OS <<
"\t.end_amd_kernel_code_t\n";
253 OS <<
"\t.amdgpu_hsa_kernel " << SymbolName <<
'\n' ;
260 OS <<
"\t.amdgpu_lds " << Symbol->getName() <<
", " <<
Size <<
", "
261 << Alignment.
value() <<
'\n';
265 OS <<
"\t.amd_amdgpu_isa \"" <<
getTargetID()->toString() <<
"\"\n";
275 std::string HSAMetadataString;
277 HSAMetadataDoc.
toYAML(StrOS);
280 OS << StrOS.
str() <<
'\n';
287 OS << (TrapEnabled ?
"\ts_trap 2" :
"\ts_endpgm")
288 <<
" ; Kernarg preload header. Trap with incompatible firmware that "
289 "doesn't support preloading kernel arguments.\n";
290 OS <<
"\t.fill 63, 4, 0xbf800000 ; s_nop 0\n";
295 const uint32_t Encoded_s_code_end = 0xbf9f0000;
296 const uint32_t Encoded_s_nop = 0xbf800000;
297 uint32_t Encoded_pad = Encoded_s_code_end;
307 Encoded_pad = Encoded_s_nop;
311 OS <<
"\t.p2alignl " << Log2CacheLineSize <<
", " << Encoded_pad <<
'\n';
312 OS <<
"\t.fill " << (FillSize / 4) <<
", 4, " << Encoded_pad <<
'\n';
319 bool ReserveVCC,
bool ReserveFlatScr) {
323 OS <<
"\t.amdhsa_kernel " << KernelName <<
'\n';
329 const MCExpr *pgm_rsrc1_bits =
331 if (pgm_rsrc1_bits->evaluateAsAbsolute(IVal))
332 OS << static_cast<uint64_t>(IVal);
334 pgm_rsrc1_bits->
print(OS, MAI);
338 OS <<
"\t\t.amdhsa_group_segment_fixed_size ";
342 OS <<
"\t\t.amdhsa_private_segment_fixed_size ";
346 OS <<
"\t\t.amdhsa_kernarg_size ";
352 amdhsa::COMPUTE_PGM_RSRC2_USER_SGPR_COUNT,
".amdhsa_user_sgpr_count");
357 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER_SHIFT,
358 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_BUFFER,
359 ".amdhsa_user_sgpr_private_segment_buffer");
361 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR_SHIFT,
362 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_PTR,
363 ".amdhsa_user_sgpr_dispatch_ptr");
365 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR_SHIFT,
366 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_QUEUE_PTR,
367 ".amdhsa_user_sgpr_queue_ptr");
369 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR_SHIFT,
370 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_KERNARG_SEGMENT_PTR,
371 ".amdhsa_user_sgpr_kernarg_segment_ptr");
373 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID_SHIFT,
374 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_DISPATCH_ID,
375 ".amdhsa_user_sgpr_dispatch_id");
378 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT_SHIFT,
379 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_FLAT_SCRATCH_INIT,
380 ".amdhsa_user_sgpr_flat_scratch_init");
383 amdhsa::KERNARG_PRELOAD_SPEC_LENGTH,
384 ".amdhsa_user_sgpr_kernarg_preload_length");
386 amdhsa::KERNARG_PRELOAD_SPEC_OFFSET,
387 ".amdhsa_user_sgpr_kernarg_preload_offset");
391 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE_SHIFT,
392 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_SGPR_PRIVATE_SEGMENT_SIZE,
393 ".amdhsa_user_sgpr_private_segment_size");
394 if (IVersion.
Major >= 10)
396 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32_SHIFT,
397 amdhsa::KERNEL_CODE_PROPERTY_ENABLE_WAVEFRONT_SIZE32,
398 ".amdhsa_wavefront_size32");
401 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK_SHIFT,
402 amdhsa::KERNEL_CODE_PROPERTY_USES_DYNAMIC_STACK,
403 ".amdhsa_uses_dynamic_stack");
405 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT_SHIFT,
406 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_PRIVATE_SEGMENT,
408 ?
".amdhsa_enable_private_segment"
409 :
".amdhsa_system_sgpr_private_segment_wavefront_offset"));
411 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X_SHIFT,
412 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_X,
413 ".amdhsa_system_sgpr_workgroup_id_x");
415 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y_SHIFT,
416 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Y,
417 ".amdhsa_system_sgpr_workgroup_id_y");
419 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z_SHIFT,
420 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_ID_Z,
421 ".amdhsa_system_sgpr_workgroup_id_z");
423 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO_SHIFT,
424 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_SGPR_WORKGROUP_INFO,
425 ".amdhsa_system_sgpr_workgroup_info");
427 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID_SHIFT,
428 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_VGPR_WORKITEM_ID,
429 ".amdhsa_system_vgpr_workitem_id");
432 OS <<
"\t\t.amdhsa_next_free_vgpr " << NextVGPR <<
'\n';
433 OS <<
"\t\t.amdhsa_next_free_sgpr " << NextSGPR <<
'\n';
439 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET_SHIFT,
440 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_ACCUM_OFFSET,
getContext());
445 OS <<
"\t\t.amdhsa_accum_offset ";
447 if (accum_bits->evaluateAsAbsolute(IVal)) {
448 OS << static_cast<uint64_t>(IVal);
450 accum_bits->
print(OS, MAI);
456 OS <<
"\t\t.amdhsa_reserve_vcc " << ReserveVCC <<
'\n';
458 OS <<
"\t\t.amdhsa_reserve_flat_scratch " << ReserveFlatScr <<
'\n';
466 OS <<
"\t\t.amdhsa_reserve_xnack_mask " <<
getTargetID()->isXnackOnOrAny() <<
'\n';
471 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32_SHIFT,
472 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_32,
473 ".amdhsa_float_round_mode_32");
475 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64_SHIFT,
476 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_ROUND_MODE_16_64,
477 ".amdhsa_float_round_mode_16_64");
479 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32_SHIFT,
480 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_32,
481 ".amdhsa_float_denorm_mode_32");
483 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64_SHIFT,
484 amdhsa::COMPUTE_PGM_RSRC1_FLOAT_DENORM_MODE_16_64,
485 ".amdhsa_float_denorm_mode_16_64");
486 if (IVersion.
Major < 12) {
488 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP_SHIFT,
489 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_DX10_CLAMP,
490 ".amdhsa_dx10_clamp");
492 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE_SHIFT,
493 amdhsa::COMPUTE_PGM_RSRC1_GFX6_GFX11_ENABLE_IEEE_MODE,
494 ".amdhsa_ieee_mode");
496 if (IVersion.
Major >= 9) {
498 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL_SHIFT,
499 amdhsa::COMPUTE_PGM_RSRC1_GFX9_PLUS_FP16_OVFL,
500 ".amdhsa_fp16_overflow");
504 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT_SHIFT,
505 amdhsa::COMPUTE_PGM_RSRC3_GFX90A_TG_SPLIT,
".amdhsa_tg_split");
506 if (IVersion.
Major >= 10) {
508 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE_SHIFT,
509 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_WGP_MODE,
510 ".amdhsa_workgroup_processor_mode");
512 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED_SHIFT,
513 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_MEM_ORDERED,
514 ".amdhsa_memory_ordered");
516 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS_SHIFT,
517 amdhsa::COMPUTE_PGM_RSRC1_GFX10_PLUS_FWD_PROGRESS,
518 ".amdhsa_forward_progress");
520 if (IVersion.
Major >= 10 && IVersion.
Major < 12) {
522 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT_SHIFT,
523 amdhsa::COMPUTE_PGM_RSRC3_GFX10_GFX11_SHARED_VGPR_COUNT,
524 ".amdhsa_shared_vgpr_count");
526 if (IVersion.
Major >= 12) {
528 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN_SHIFT,
529 amdhsa::COMPUTE_PGM_RSRC1_GFX12_PLUS_ENABLE_WG_RR_EN,
530 ".amdhsa_round_robin_scheduling");
535 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION_SHIFT,
536 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INVALID_OPERATION,
537 ".amdhsa_exception_fp_ieee_invalid_op");
540 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE_SHIFT,
541 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_FP_DENORMAL_SOURCE,
542 ".amdhsa_exception_fp_denorm_src");
546 COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO_SHIFT,
547 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_DIVISION_BY_ZERO,
548 ".amdhsa_exception_fp_ieee_div_zero");
551 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW_SHIFT,
552 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_OVERFLOW,
553 ".amdhsa_exception_fp_ieee_overflow");
556 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW_SHIFT,
557 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_UNDERFLOW,
558 ".amdhsa_exception_fp_ieee_underflow");
561 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT_SHIFT,
562 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_IEEE_754_FP_INEXACT,
563 ".amdhsa_exception_fp_ieee_inexact");
566 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO_SHIFT,
567 amdhsa::COMPUTE_PGM_RSRC2_ENABLE_EXCEPTION_INT_DIVIDE_BY_ZERO,
568 ".amdhsa_exception_int_div_zero");
570 OS <<
"\t.end_amdhsa_kernel\n";
608void AMDGPUTargetELFStreamer::EmitNote(
612 auto &
Context = S.getContext();
614 auto NameSZ =
Name.size() + 1;
616 unsigned NoteFlags = 0;
626 S.emitValue(DescSZ, 4);
627 S.emitInt32(NoteType);
629 S.emitValueToAlignment(
Align(4), 0, 1, 0);
631 S.emitValueToAlignment(
Align(4), 0, 1, 0);
635unsigned AMDGPUTargetELFStreamer::getEFlags() {
640 return getEFlagsR600();
642 return getEFlagsAMDGCN();
646unsigned AMDGPUTargetELFStreamer::getEFlagsR600() {
652unsigned AMDGPUTargetELFStreamer::getEFlagsAMDGCN() {
660 return getEFlagsUnknownOS();
662 return getEFlagsAMDHSA();
664 return getEFlagsAMDPAL();
666 return getEFlagsMesa3D();
670unsigned AMDGPUTargetELFStreamer::getEFlagsUnknownOS() {
674 return getEFlagsV3();
677unsigned AMDGPUTargetELFStreamer::getEFlagsAMDHSA() {
681 return getEFlagsV6();
682 return getEFlagsV4();
685unsigned AMDGPUTargetELFStreamer::getEFlagsAMDPAL() {
688 return getEFlagsV3();
691unsigned AMDGPUTargetELFStreamer::getEFlagsMesa3D() {
694 return getEFlagsV3();
697unsigned AMDGPUTargetELFStreamer::getEFlagsV3() {
698 unsigned EFlagsV3 = 0;
713unsigned AMDGPUTargetELFStreamer::getEFlagsV4() {
714 unsigned EFlagsV4 = 0;
753unsigned AMDGPUTargetELFStreamer::getEFlagsV6() {
754 unsigned Flags = getEFlagsV4();
781 " - no ELF flag can represent this version!");
801 Symbol->setType(
Type);
806 MCSymbolELF *SymbolELF = cast<MCSymbolELF>(Symbol);
816 " redeclared as different type");
827 auto *DescBegin =
Context.createTempSymbol();
828 auto *DescEnd =
Context.createTempSymbol();
835 OS.emitLabel(DescBegin);
837 OS.emitLabel(DescEnd);
848 std::string HSAMetadataString;
854 auto *DescBegin =
Context.createTempSymbol();
855 auto *DescEnd =
Context.createTempSymbol();
862 OS.emitLabel(DescBegin);
863 OS.emitBytes(HSAMetadataString);
864 OS.emitLabel(DescEnd);
871 const uint32_t Encoded_s_nop = 0xbf800000;
872 const uint32_t Encoded_s_trap = 0xbf920002;
873 const uint32_t Encoded_s_endpgm = 0xbf810000;
874 const uint32_t TrapInstr = TrapEnabled ? Encoded_s_trap : Encoded_s_endpgm;
876 OS.emitInt32(TrapInstr);
877 for (
int i = 0; i < 63; ++i) {
878 OS.emitInt32(Encoded_s_nop);
884 const uint32_t Encoded_s_code_end = 0xbf9f0000;
885 const uint32_t Encoded_s_nop = 0xbf800000;
886 uint32_t Encoded_pad = Encoded_s_code_end;
896 Encoded_pad = Encoded_s_nop;
903 for (
unsigned I = 0;
I < FillSize;
I += 4)
904 OS.emitInt32(Encoded_pad);
912 uint64_t NextSGPR,
bool ReserveVCC,
bool ReserveFlatScr) {
918 MCSymbolELF *KernelDescriptorSymbol = cast<MCSymbolELF>(
928 KernelDescriptorSymbol->
setSize(
936 Streamer.
emitLabel(KernelDescriptorSymbol);
AMDHSA kernel descriptor MCExpr struct for use in MC layer.
Enums and constants for AMDGPU PT_NOTE sections.
static cl::opt< unsigned > ForceGenericVersion("amdgpu-force-generic-version", cl::desc("Force a specific generic_v<N> flag to be " "added. For testing purposes only."), cl::ReallyHidden, cl::init(0))
AMDHSA kernel descriptor definitions.
MC layer struct for AMDGPUMCKernelCodeT, provides MCExpr functionality where required.
assert(ImpDefSCC.getReg()==AMDGPU::SCC &&ImpDefSCC.isDef())
verify safepoint Safepoint IR Verifier
AMDGPUTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS)
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitISAVersion() override
void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV) override
void EmitDirectiveAMDGCNTarget() override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitDirectiveAMDGCNTarget() override
bool EmitCodeEnd(const MCSubtargetInfo &STI) override
void EmitAMDKernelCodeT(AMDGPU::AMDGPUMCKernelCodeT &Header) override
bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict) override
AMDGPUTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI)
void emitAMDGPULDS(MCSymbol *Sym, unsigned Size, Align Alignment) override
void EmitAmdhsaKernelDescriptor(const MCSubtargetInfo &STI, StringRef KernelName, const AMDGPU::MCKernelDescriptor &KernelDescriptor, uint64_t NextVGPR, uint64_t NextSGPR, bool ReserveVCC, bool ReserveFlatScr) override
MCELFStreamer & getStreamer()
void EmitAMDGPUSymbolType(StringRef SymbolName, unsigned Type) override
bool EmitKernargPreloadHeader(const MCSubtargetInfo &STI, bool TrapEnabled) override
bool EmitISAVersion() override
virtual bool EmitHSAMetadata(msgpack::Document &HSAMetadata, bool Strict)
Emit HSA Metadata.
AMDGPUPALMetadata * getPALMetadata()
virtual void EmitDirectiveAMDHSACodeObjectVersion(unsigned COV)
virtual bool EmitHSAMetadataV3(StringRef HSAMetadataString)
static unsigned getElfMach(StringRef GPU)
MCContext & getContext() const
static StringRef getArchNameFromElfMach(unsigned ElfMach)
const std::optional< AMDGPU::IsaInfo::AMDGPUTargetID > & getTargetID() const
unsigned CodeObjectVersion
This class is intended to be used as a base class for asm properties and features specific to the tar...
MCObjectWriter & getWriter() const
void setELFHeaderEFlags(unsigned Flags)
static const MCBinaryExpr * createAdd(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createMul(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCBinaryExpr * createSub(const MCExpr *LHS, const MCExpr *RHS, MCContext &Ctx)
static const MCConstantExpr * create(int64_t Value, MCContext &Ctx, bool PrintInHex=false, unsigned SizeInBytes=0)
const MCAsmInfo * getAsmInfo() const
Base class for the full range of assembler expressions which are needed for parsing.
void print(raw_ostream &OS, const MCAsmInfo *MAI, bool InParens=false) const
MCAssembler & getAssembler()
virtual void setOverrideABIVersion(uint8_t ABIVersion)
ELF only, override the default ABIVersion in the ELF header.
Streaming machine code generation interface.
MCContext & getContext() const
void emitValue(const MCExpr *Value, unsigned Size, SMLoc Loc=SMLoc())
virtual void emitLabel(MCSymbol *Symbol, SMLoc Loc=SMLoc())
Emit a label for Symbol into the current section.
void emitInt8(uint64_t Value)
Generic base class for all target subtargets.
const Triple & getTargetTriple() const
unsigned getOther() const
void setVisibility(unsigned Visibility)
void setSize(const MCExpr *SS)
bool isBindingSet() const
void setBinding(unsigned Binding) const
unsigned getVisibility() const
unsigned getBinding() const
void setType(unsigned Type) const
void setOther(unsigned Other)
static const MCSymbolRefExpr * create(const MCSymbol *Symbol, MCContext &Ctx)
MCSymbol - Instances of this class represent a symbol name in the MC file, and MCSymbols are created ...
void setExternal(bool Value) const
void setIndex(uint32_t Value) const
Set the (implementation defined) index.
bool declareCommon(uint64_t Size, Align Alignment, bool Target=false)
Declare this symbol as being 'common'.
StringRef - Represent a constant reference to a string, i.e.
OSType getOS() const
Get the parsed operating system type of this triple.
ArchType getArch() const
Get the parsed architecture type of this triple.
Twine - A lightweight data structure for efficiently representing the concatenation of temporary valu...
The instances of the Type class are immutable: once they are created, they are never changed.
An efficient, type-erasing, non-owning reference to a callable.
Simple in-memory representation of a document of msgpack objects with ability to find and create arra...
DocNode & getRoot()
Get ref to the document's root element.
void toYAML(raw_ostream &OS)
Convert MsgPack Document to YAML text.
void writeToBlob(std::string &Blob)
Write a MsgPack document to a binary MsgPack blob.
bool fromYAML(StringRef S)
Read YAML text into the MsgPack document. Returns false on failure.
A raw_ostream that writes to an std::string.
std::string & str()
Returns the string's reference.
#define llvm_unreachable(msg)
Marks that the current location is not supposed to be reachable.
static constexpr unsigned GFX10_1
static constexpr unsigned GFX10_3
static constexpr unsigned GFX11
static constexpr unsigned GFX9
constexpr char AssemblerDirectiveBegin[]
HSA metadata beginning assembler directive.
constexpr char AssemblerDirectiveEnd[]
HSA metadata ending assembler directive.
StringRef getArchNameR600(GPUKind AK)
GPUKind
GPU kinds supported by the AMDGPU target.
bool isHsaAbi(const MCSubtargetInfo &STI)
IsaVersion getIsaVersion(StringRef GPU)
bool isGFX90A(const MCSubtargetInfo &STI)
GPUKind parseArchAMDGCN(StringRef CPU)
bool hasArchitectedFlatScratch(const MCSubtargetInfo &STI)
bool isGFX11Plus(const MCSubtargetInfo &STI)
StringRef getArchNameAMDGCN(GPUKind AK)
unsigned hasKernargPreload(const MCSubtargetInfo &STI)
uint8_t getELFABIVersion(const Triple &T, unsigned CodeObjectVersion)
GPUKind parseArchR600(StringRef CPU)
@ EF_AMDGPU_GENERIC_VERSION_MAX
@ EF_AMDGPU_FEATURE_XNACK_ANY_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX703
@ EF_AMDGPU_MACH_AMDGCN_GFX1035
@ EF_AMDGPU_FEATURE_SRAMECC_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX1031
@ EF_AMDGPU_GENERIC_VERSION_OFFSET
@ EF_AMDGPU_MACH_R600_CAYMAN
@ EF_AMDGPU_FEATURE_SRAMECC_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX704
@ EF_AMDGPU_MACH_AMDGCN_GFX902
@ EF_AMDGPU_MACH_AMDGCN_GFX810
@ EF_AMDGPU_MACH_AMDGCN_GFX1036
@ EF_AMDGPU_MACH_AMDGCN_GFX1102
@ EF_AMDGPU_MACH_R600_RV730
@ EF_AMDGPU_MACH_R600_RV710
@ EF_AMDGPU_MACH_AMDGCN_GFX908
@ EF_AMDGPU_MACH_AMDGCN_GFX1011
@ EF_AMDGPU_MACH_R600_CYPRESS
@ EF_AMDGPU_MACH_AMDGCN_GFX1032
@ EF_AMDGPU_MACH_R600_R600
@ EF_AMDGPU_MACH_AMDGCN_GFX940
@ EF_AMDGPU_MACH_AMDGCN_GFX941
@ EF_AMDGPU_MACH_R600_TURKS
@ EF_AMDGPU_MACH_R600_JUNIPER
@ EF_AMDGPU_FEATURE_SRAMECC_OFF_V4
@ EF_AMDGPU_FEATURE_XNACK_UNSUPPORTED_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX601
@ EF_AMDGPU_MACH_AMDGCN_GFX942
@ EF_AMDGPU_MACH_R600_R630
@ EF_AMDGPU_MACH_R600_REDWOOD
@ EF_AMDGPU_MACH_R600_RV770
@ EF_AMDGPU_FEATURE_XNACK_OFF_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX600
@ EF_AMDGPU_FEATURE_XNACK_V3
@ EF_AMDGPU_MACH_AMDGCN_GFX602
@ EF_AMDGPU_MACH_AMDGCN_GFX1101
@ EF_AMDGPU_MACH_AMDGCN_GFX1100
@ EF_AMDGPU_MACH_AMDGCN_GFX1033
@ EF_AMDGPU_MACH_AMDGCN_GFX801
@ EF_AMDGPU_MACH_AMDGCN_GFX705
@ EF_AMDGPU_MACH_AMDGCN_GFX1010
@ EF_AMDGPU_MACH_R600_RV670
@ EF_AMDGPU_MACH_AMDGCN_GFX701
@ EF_AMDGPU_MACH_AMDGCN_GFX10_3_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX1012
@ EF_AMDGPU_MACH_AMDGCN_GFX1151
@ EF_AMDGPU_MACH_AMDGCN_GFX1030
@ EF_AMDGPU_MACH_R600_CEDAR
@ EF_AMDGPU_MACH_AMDGCN_GFX1200
@ EF_AMDGPU_MACH_AMDGCN_GFX700
@ EF_AMDGPU_MACH_AMDGCN_GFX11_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX803
@ EF_AMDGPU_MACH_AMDGCN_GFX802
@ EF_AMDGPU_MACH_AMDGCN_GFX90C
@ EF_AMDGPU_FEATURE_XNACK_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX900
@ EF_AMDGPU_MACH_AMDGCN_GFX909
@ EF_AMDGPU_MACH_AMDGCN_GFX906
@ EF_AMDGPU_MACH_AMDGCN_GFX9_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX1103
@ EF_AMDGPU_MACH_R600_CAICOS
@ EF_AMDGPU_MACH_AMDGCN_GFX90A
@ EF_AMDGPU_MACH_AMDGCN_GFX1034
@ EF_AMDGPU_MACH_AMDGCN_GFX1013
@ EF_AMDGPU_MACH_AMDGCN_GFX10_1_GENERIC
@ EF_AMDGPU_MACH_AMDGCN_GFX904
@ EF_AMDGPU_MACH_R600_RS880
@ EF_AMDGPU_MACH_AMDGCN_GFX805
@ EF_AMDGPU_MACH_AMDGCN_GFX1201
@ EF_AMDGPU_MACH_AMDGCN_GFX1150
@ EF_AMDGPU_MACH_R600_SUMO
@ EF_AMDGPU_MACH_R600_BARTS
@ EF_AMDGPU_FEATURE_SRAMECC_ANY_V4
@ EF_AMDGPU_FEATURE_SRAMECC_ON_V4
@ EF_AMDGPU_MACH_AMDGCN_GFX702
initializer< Ty > init(const Ty &Val)
std::optional< const char * > toString(const std::optional< DWARFFormValue > &V)
Take an optional DWARFFormValue and try to extract a string value from it.
This is an optimization pass for GlobalISel generic memory operations.
void report_fatal_error(Error Err, bool gen_crash_diag=true)
Report a serious error, calling any installed error handler.
Instruction set architecture version.
const MCExpr * compute_pgm_rsrc2
const MCExpr * kernarg_size
const MCExpr * kernarg_preload
const MCExpr * compute_pgm_rsrc3
const MCExpr * private_segment_fixed_size
static const MCExpr * bits_get(const MCExpr *Src, uint32_t Shift, uint32_t Mask, MCContext &Ctx)
const MCExpr * compute_pgm_rsrc1
const MCExpr * group_segment_fixed_size
const MCExpr * kernel_code_properties
This struct is a compact representation of a valid (non-zero power of two) alignment.
uint64_t value() const
This is a hole in the type system and should not be abused.
uint32_t group_segment_fixed_size
uint32_t compute_pgm_rsrc1
uint32_t private_segment_fixed_size
uint32_t compute_pgm_rsrc2
uint16_t kernel_code_properties
uint32_t compute_pgm_rsrc3
int64_t kernel_code_entry_byte_offset