13#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
14#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRUCTIONSELECTOR_H
21#define GET_GLOBALISEL_PREDICATE_BITSET
22#define AMDGPUSubtarget GCNSubtarget
23#include "AMDGPUGenGlobalISel.inc"
24#undef GET_GLOBALISEL_PREDICATE_BITSET
31struct ImageDimIntrinsicInfo;
34class AMDGPURegisterBankInfo;
35class AMDGPUTargetMachine;
36class BlockFrequencyInfo;
37class ProfileSummaryInfo;
40class MachineIRBuilder;
42class MachineRegisterInfo;
46class TargetRegisterClass;
86 unsigned SubIdx)
const;
88 bool constrainCopyLikeIntrin(
MachineInstr &
MI,
unsigned NewOpc)
const;
125 bool selectDSAppendConsume(
MachineInstr &
MI,
bool IsAppend)
const;
132 bool selectG_INTRINSIC_W_SIDE_EFFECTS(
MachineInstr &
I)
const;
157 std::pair<Register, unsigned> selectVOP3ModsImpl(
MachineOperand &Root,
158 bool IsCanonicalizing =
true,
159 bool AllowAbs =
true,
160 bool OpSel =
false)
const;
164 bool ForceVGPR =
false)
const;
187 std::pair<Register, unsigned>
189 bool IsDOT =
false)
const;
235 std::pair<Register, int> selectFlatOffsetImpl(
MachineOperand &Root,
261 bool isDSOffset2Legal(
Register Base, int64_t Offset0, int64_t Offset1,
262 unsigned Size)
const;
267 std::pair<Register, unsigned>
278 std::pair<Register, unsigned> selectDSReadWrite2Impl(
MachineOperand &Root,
279 unsigned size)
const;
283 std::pair<Register, int64_t>
284 getPtrBaseWithConstantOffset(
Register Root,
290 struct MUBUFAddressData {
295 bool shouldUseAddr64(MUBUFAddressData AddrData)
const;
297 void splitIllegalMUBUFOffset(MachineIRBuilder &
B,
298 Register &SOffset, int64_t &ImmOffset)
const;
300 MUBUFAddressData parseMUBUFAddress(Register Src)
const;
302 bool selectMUBUFAddr64Impl(MachineOperand &Root, Register &VAddr,
303 Register &RSrcReg, Register &SOffset,
306 bool selectMUBUFOffsetImpl(MachineOperand &Root, Register &RSrcReg,
307 Register &SOffset, int64_t &
Offset)
const;
310 selectBUFSOffset(MachineOperand &Root)
const;
313 selectMUBUFAddr64(MachineOperand &Root)
const;
316 selectMUBUFOffset(MachineOperand &Root)
const;
322 std::pair<Register, unsigned> selectVOP3PMadMixModsImpl(MachineOperand &Root,
323 bool &Matched)
const;
327 void renderTruncImm32(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
328 int OpIdx = -1)
const;
330 void renderTruncTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
333 void renderOpSelTImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
336 void renderNegateImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
339 void renderBitcastImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
342 void renderPopcntImm(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
344 void renderExtractCPol(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
346 void renderExtractSWZ(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
348 void renderExtractCpolSetGLC(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
351 void renderFrameIndex(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
354 void renderFPPow2ToExponent(MachineInstrBuilder &MIB,
const MachineInstr &
MI,
357 bool isInlineImmediate(
const APInt &Imm)
const;
358 bool isInlineImmediate(
const APFloat &Imm)
const;
362 bool isUnneededShiftMask(
const MachineInstr &
MI,
unsigned ShAmtBits)
const;
364 const SIInstrInfo &TII;
365 const SIRegisterInfo &TRI;
366 const AMDGPURegisterBankInfo &RBI;
367 const AMDGPUTargetMachine &
TM;
368 const GCNSubtarget &STI;
369 bool EnableLateStructurizeCFG;
370#define GET_GLOBALISEL_PREDICATES_DECL
371#define AMDGPUSubtarget GCNSubtarget
372#include "AMDGPUGenGlobalISel.inc"
373#undef GET_GLOBALISEL_PREDICATES_DECL
374#undef AMDGPUSubtarget
376#define GET_GLOBALISEL_TEMPORARIES_DECL
377#include "AMDGPUGenGlobalISel.inc"
378#undef GET_GLOBALISEL_TEMPORARIES_DECL
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
const char LLVMTargetMachineRef TM
static const char * getName()
bool select(MachineInstr &I) override
Select the (possibly generic) instruction I to only use target-specific opcodes.
void setupMF(MachineFunction &MF, GISelKnownBits *KB, CodeGenCoverage *CoverageInfo, ProfileSummaryInfo *PSI, BlockFrequencyInfo *BFI) override
Setup per-MF executor state.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
BlockFrequencyInfo pass uses BlockFrequencyInfoImpl implementation to estimate IR basic block frequen...
Predicate
This enumeration lists the possible predicates for CmpInst subclasses.
std::optional< SmallVector< std::function< void(MachineInstrBuilder &)>, 4 > > ComplexRendererFns
CodeGenCoverage * CoverageInfo
Representation of each machine instruction.
MachineOperand class - Representation of each machine instruction operand.
MachineRegisterInfo - Keep track of information for virtual and physical registers,...
Analysis providing profile information.
This class implements the register bank concept.
Wrapper class representing virtual and physical registers.
This class consists of common code factored out of the SmallVector class to reduce code duplication b...
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
TargetRegisterInfo base class - We assume that the target defines a static array of TargetRegisterDes...
This is an optimization pass for GlobalISel generic memory operations.