llvm.org GIT mirror llvm / release_39
Merging r288433: ------------------------------------------------------------------------ r288433 | oranevskyy | 2016-12-01 14:58:35 -0800 (Thu, 01 Dec 2016) | 24 lines [ARM] Fix for 64-bit CAS expansion on ARM32 with -O0 Summary: This patch fixes comparison of 64-bit atomic with its expected value in CMP_SWAP_64 expansion. Currently, the low words are compared with CMP, while the high words are compared with SBC. SBC expects the carry flag to be set if CMP detects a difference. CMP might leave the carry unset for unequal arguments though if the first one is >= than the second. This might cause the comparison logic to detect false equality. Example of the broken C++ code: ``` std::atomic<long long> at(2); long long ll = 1; std::atomic_compare_exchange_strong(&at, &ll, 3); ``` Even though the atomic `at` and the expected value `ll` are not equal and `atomic_compare_exchange_strong` returns `false`, `at` is changed to 3. The patch replaces SBC with CMPEQ. Reviewers: t.p.northover Subscribers: aemerson, rengolin, llvm-commits, asl Differential Revision: https://reviews.llvm.org/D27315 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_39@288847 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 8 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
931931 .addReg(DestLo, getKillRegState(Dest.isDead()))
932932 .addReg(DesiredLo, getKillRegState(Desired.isDead())));
933933
934 unsigned SBCrr = IsThumb ? ARM::t2SBCrr : ARM::SBCrr;
935 MIB = BuildMI(LoadCmpBB, DL, TII->get(SBCrr))
936 .addReg(StatusReg, RegState::Define | RegState::Dead)
937 .addReg(DestHi, getKillRegState(Dest.isDead()))
938 .addReg(DesiredHi, getKillRegState(Desired.isDead()));
939 AddDefaultPred(MIB);
940 MIB.addReg(ARM::CPSR, RegState::Kill);
934 BuildMI(LoadCmpBB, DL, TII->get(CMPrr))
935 .addReg(DestHi, getKillRegState(Dest.isDead()))
936 .addReg(DesiredHi, getKillRegState(Desired.isDead()))
937 .addImm(ARMCC::EQ).addReg(ARM::CPSR, RegState::Kill);
941938
942939 unsigned Bcc = IsThumb ? ARM::tBcc : ARM::Bcc;
943940 BuildMI(LoadCmpBB, DL, TII->get(Bcc))
6868 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
6969 ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
7070 ; CHECK: cmp [[OLDLO]], r6
71 ; CHECK: sbcs{{(\.w)?}} [[STATUS:r[0-9]+]], [[OLDHI]], r7
71 ; CHECK: cmpeq [[OLDHI]], r7
7272 ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
73 ; CHECK: strexd [[STATUS]], r4, r5, [r0]
73 ; CHECK: strexd [[STATUS:r[0-9]+]], r4, r5, [r0]
7474 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
7575 ; CHECK: bne [[RETRY]]
7676 ; CHECK: [[DONE]]:
8686 ; CHECK: [[RETRY:.LBB[0-9]+_[0-9]+]]:
8787 ; CHECK: ldrexd [[OLDLO:r[0-9]+]], [[OLDHI:r[0-9]+]], [r0]
8888 ; CHECK: cmp [[OLDLO]], {{r[0-9]+}}
89 ; CHECK: sbcs{{(\.w)?}} [[STATUS:r[0-9]+]], [[OLDHI]], {{r[0-9]+}}
89 ; CHECK: cmpeq [[OLDHI]], {{r[0-9]+}}
9090 ; CHECK: bne [[DONE:.LBB[0-9]+_[0-9]+]]
91 ; CHECK: strexd [[STATUS]], {{r[0-9]+}}, {{r[0-9]+}}, [r0]
91 ; CHECK: strexd [[STATUS:r[0-9]+]], {{r[0-9]+}}, {{r[0-9]+}}, [r0]
9292 ; CHECK: cmp{{(\.w)?}} [[STATUS]], #0
9393 ; CHECK: bne [[RETRY]]
9494 ; CHECK: [[DONE]]: