llvm.org GIT mirror llvm / master
[X86] Remove OpSizeIgnore, it's not implemented any differently than OpSizeFixed. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@330532 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper an hour ago
3 changed file(s) with 3 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
368368 // OpSize - OpSizeFixed implies instruction never needs a 0x66 prefix.
369369 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
370370 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
371 // prefix in 16-bit mode. OpSizeIgnore means that the instruction may
372 // take a optional 0x66 byte but should not emit with one.
371 // prefix in 16-bit mode.
373372 OpSizeShift = 7,
374373 OpSizeMask = 0x3 << OpSizeShift,
375374
376375 OpSizeFixed = 0 << OpSizeShift,
377376 OpSize16 = 1 << OpSizeShift,
378377 OpSize32 = 2 << OpSizeShift,
379 OpSizeIgnore = 3 << OpSizeShift,
380378
381379 // AsSize - AdSizeX implies this instruction determines its need of 0x67
382380 // prefix from a normal ModRM memory operand. The other types indicate that
165165 def OpSizeFixed : OperandSize<0>; // Never needs a 0x66 prefix.
166166 def OpSize16 : OperandSize<1>; // Needs 0x66 prefix in 32-bit mode.
167167 def OpSize32 : OperandSize<2>; // Needs 0x66 prefix in 16-bit mode.
168 def OpSizeIgnore : OperandSize<3>; // Takes 0x66 prefix, never emits.
169168
170169 // Address size for encodings that change based on mode.
171170 class AddressSize val> {
180179 // emitter that various prefix bytes are required.
181180 class OpSize16 { OperandSize OpSize = OpSize16; }
182181 class OpSize32 { OperandSize OpSize = OpSize32; }
183 class OpSizeIgnore { OperandSize OpSize = OpSizeIgnore; }
184182 class AdSize16 { AddressSize AdSize = AdSize16; }
185183 class AdSize32 { AddressSize AdSize = AdSize32; }
186184 class AdSize64 { AddressSize AdSize = AdSize64; }
170170 "mov{q}\t{$src, $dst|$dst, $src}", []>;
171171 let mayStore = 1 in {
172172 def MOV16ms : I<0x8C, MRMDestMem, (outs), (ins i16mem:$dst, SEGMENT_REG:$src),
173 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSizeIgnore;
173 "mov{w}\t{$src, $dst|$dst, $src}", []>;
174174 }
175175 def MOV16sr : I<0x8E, MRMSrcReg, (outs SEGMENT_REG:$dst), (ins GR16:$src),
176176 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSize16;
180180 "mov{q}\t{$src, $dst|$dst, $src}", []>;
181181 let mayLoad = 1 in {
182182 def MOV16sm : I<0x8E, MRMSrcMem, (outs SEGMENT_REG:$dst), (ins i16mem:$src),
183 "mov{w}\t{$src, $dst|$dst, $src}", []>, OpSizeIgnore;
183 "mov{w}\t{$src, $dst|$dst, $src}", []>;
184184 }
185185 } // SchedRW
186186