llvm.org GIT mirror llvm / ffd5316
[ARM] VFPv2 only supports 16 D registers. r361845 changed the way we handle "D16" vs. "D32" targets; there used to be a negative "d16" which removed instructions from the instruction set, and now there's a "d32" feature which adds instructions to the instruction set. This is good, but there was an oversight in the implementation: the behavior of VFPv2 was changed. In particular, the "vfp2" feature was changed to imply "d32". This is wrong: VFPv2 only supports 16 D registers. In practice, this means if you specify -mfpu=vfpv2, the compiler will generate illegal instructions. This patch gets rid of "vfp2d16" and "vfp2d16sp", and fixes "vfp2" and "vfp2sp" so they don't imply "d32". Differential Revision: https://reviews.llvm.org/D67375 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372186 91177308-0d34-0410-b5e6-96231b3b80d8 Eli Friedman 10 months ago
12 changed file(s) with 49 addition(s) and 43 deletion(s). Raw diff Collapse all Expand all
202202 default:
203203 break;
204204 case ARMBuildAttrs::Not_Allowed:
205 Features.AddFeature("vfp2d16sp", false);
205 Features.AddFeature("vfp2sp", false);
206206 Features.AddFeature("vfp3d16sp", false);
207207 Features.AddFeature("vfp4d16sp", false);
208208 break;
175175 // exist).
176176
177177 {"+fpregs", "-fpregs", FPUVersion::VFPV2, FPURestriction::SP_D16},
178 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::None},
179 {"+vfp2d16", "-vfp2d16", FPUVersion::VFPV2, FPURestriction::D16},
180 {"+vfp2d16sp", "-vfp2d16sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
181 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::None},
178 {"+vfp2", "-vfp2", FPUVersion::VFPV2, FPURestriction::D16},
179 {"+vfp2sp", "-vfp2sp", FPUVersion::VFPV2, FPURestriction::SP_D16},
182180 {"+vfp3", "-vfp3", FPUVersion::VFPV3, FPURestriction::None},
183181 {"+vfp3d16", "-vfp3d16", FPUVersion::VFPV3, FPURestriction::D16},
184182 {"+vfp3d16sp", "-vfp3d16sp", FPUVersion::VFPV3, FPURestriction::SP_D16},
194192 {"+fp-armv8sp", "-fp-armv8sp", FPUVersion::VFPV5, FPURestriction::None},
195193 {"+fullfp16", "-fullfp16", FPUVersion::VFPV5_FULLFP16, FPURestriction::SP_D16},
196194 {"+fp64", "-fp64", FPUVersion::VFPV2, FPURestriction::D16},
197 {"+d32", "-d32", FPUVersion::VFPV2, FPURestriction::None},
195 {"+d32", "-d32", FPUVersion::VFPV3, FPURestriction::None},
198196 };
199197
200198 for (const auto &Info: FPUFeatureInfoList) {
5656 "Extend FP to 32 double registers">;
5757
5858 multiclass VFPver
59 list prev = [],
60 list otherimplies = []> {
59 list prev,
60 list otherimplies,
61 list vfp2prev = []> {
6162 def _D16_SP: SubtargetFeature<
6263 name#"d16sp", query#"D16SP", "true",
6364 description#" with only 16 d-registers and no double precision",
64 !foreach(v, prev, !cast(v # "_D16_SP")) # otherimplies>;
65 !foreach(v, prev, !cast(v # "_D16_SP")) #
66 !foreach(v, vfp2prev, !cast(v # "_SP")) #
67 otherimplies>;
6568 def _SP: SubtargetFeature<
6669 name#"sp", query#"SP", "true",
6770 description#" with no double precision",
7174 name#"d16", query#"D16", "true",
7275 description#" with only 16 d-registers",
7376 !foreach(v, prev, !cast(v # "_D16")) #
77 vfp2prev #
7478 otherimplies # [FeatureFP64, !cast(NAME # "_D16_SP")]>;
7579 def "": SubtargetFeature<
7680 name, query, "true", description,
7983 !cast(NAME # "_SP")]>;
8084 }
8185
82 defm FeatureVFP2: VFPver<"vfp2", "HasVFPv2", "Enable VFP2 instructions",
83 [], [FeatureFPRegs]>;
86 def FeatureVFP2_SP : SubtargetFeature<"vfp2sp", "HasVFPv2SP", "true",
87 "Enable VFP2 instructions with "
88 "no double precision",
89 [FeatureFPRegs]>;
90
91 def FeatureVFP2 : SubtargetFeature<"vfp2", "HasVFPv2", "true",
92 "Enable VFP2 instructions",
93 [FeatureFP64, FeatureVFP2_SP]>;
8494
8595 defm FeatureVFP3: VFPver<"vfp3", "HasVFPv3", "Enable VFP3 instructions",
86 [FeatureVFP2]>;
96 [], [], [FeatureVFP2]>;
8797
8898 def FeatureNEON : SubtargetFeature<"neon", "HasNEON", "true",
8999 "Enable NEON instructions",
97107 [FeatureVFP3], [FeatureFP16]>;
98108
99109 defm FeatureFPARMv8: VFPver<"fp-armv8", "HasFPARMv8", "Enable ARMv8 FP",
100 [FeatureVFP4]>;
110 [FeatureVFP4], []>;
101111
102112 def FeatureFullFP16 : SubtargetFeature<"fullfp16", "HasFullFP16", "true",
103113 "Enable full half-precision "
7070 AssemblerPredicate<"HasV8_5aOps", "armv8.5a">;
7171 def NoVFP : Predicate<"!Subtarget->hasVFP2Base()">;
7272 def HasVFP2 : Predicate<"Subtarget->hasVFP2Base()">,
73 AssemblerPredicate<"FeatureVFP2_D16_SP", "VFP2">;
73 AssemblerPredicate<"FeatureVFP2_SP", "VFP2">;
7474 def HasVFP3 : Predicate<"Subtarget->hasVFP3Base()">,
7575 AssemblerPredicate<"FeatureVFP3_D16_SP", "VFP3">;
7676 def HasVFP4 : Predicate<"Subtarget->hasVFP4Base()">,
179179 bool HasVFPv3SP = false;
180180 bool HasVFPv4SP = false;
181181 bool HasFPARMv8SP = false;
182 bool HasVFPv2D16 = false;
183182 bool HasVFPv3D16 = false;
184183 bool HasVFPv4D16 = false;
185184 bool HasFPARMv8D16 = false;
186 bool HasVFPv2D16SP = false;
187185 bool HasVFPv3D16SP = false;
188186 bool HasVFPv4D16SP = false;
189187 bool HasFPARMv8D16SP = false;
605603
606604 bool hasARMOps() const { return !NoARM; }
607605
608 bool hasVFP2Base() const { return HasVFPv2D16SP; }
606 bool hasVFP2Base() const { return HasVFPv2SP; }
609607 bool hasVFP3Base() const { return HasVFPv3D16SP; }
610608 bool hasVFP4Base() const { return HasVFPv4D16SP; }
611609 bool hasFPARMv8Base() const { return HasFPARMv8D16SP; }
1172411724 { ARM::AEK_CRYPTO, {Feature_HasV8Bit},
1172511725 {ARM::FeatureCrypto, ARM::FeatureNEON, ARM::FeatureFPARMv8} },
1172611726 { ARM::AEK_FP, {Feature_HasV8Bit},
11727 {ARM::FeatureVFP2_D16_SP, ARM::FeatureFPARMv8} },
11727 {ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
1172811728 { (ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM),
1172911729 {Feature_HasV7Bit, Feature_IsNotMClassBit},
1173011730 {ARM::FeatureHWDivThumb, ARM::FeatureHWDivARM} },
1173111731 { ARM::AEK_MP, {Feature_HasV7Bit, Feature_IsNotMClassBit},
1173211732 {ARM::FeatureMP} },
1173311733 { ARM::AEK_SIMD, {Feature_HasV8Bit},
11734 {ARM::FeatureNEON, ARM::FeatureVFP2_D16_SP, ARM::FeatureFPARMv8} },
11734 {ARM::FeatureNEON, ARM::FeatureVFP2_SP, ARM::FeatureFPARMv8} },
1173511735 { ARM::AEK_SEC, {Feature_HasV6KBit}, {ARM::FeatureTrustZone} },
1173611736 // FIXME: Only available in A-class, isel not predicated
1173711737 { ARM::AEK_VIRT, {Feature_HasV7Bit}, {ARM::FeatureVirtualization} },
248248 : ARM::FK_VFPV3_D16)
249249 : (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
250250 : ARM::FK_VFPV3XD)));
251 else if (STI.hasFeature(ARM::FeatureVFP2_D16_SP))
251 else if (STI.hasFeature(ARM::FeatureVFP2_SP))
252252 emitFPU(ARM::FK_VFPV2);
253253 }
254254
255255 // ABI_HardFP_use attribute to indicate single precision FP.
256 if (STI.hasFeature(ARM::FeatureVFP2_D16_SP) && !STI.hasFeature(ARM::FeatureFP64))
256 if (STI.hasFeature(ARM::FeatureVFP2_SP) && !STI.hasFeature(ARM::FeatureFP64))
257257 emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
258258 ARMBuildAttrs::HardFPSinglePrecision);
259259
1010 define void @test_gep_s16() { ret void }
1111
1212 attributes #0 = { "target-features"="+vfp2" }
13 attributes #1 = { "target-features"="-vfp2d16sp" }
13 attributes #1 = { "target-features"="-vfp2sp" }
1414 ...
1515 ---
1616 name: test_legal_loads_stores
3333 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-DEFAULT-FAST
3434 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
3535 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-neon,-d32 | FileCheck %s --check-prefix=CORTEX-A5-NONEON
36 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2d16sp | FileCheck %s --check-prefix=CORTEX-A5-NOFPU
37 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2d16sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST
36 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2sp | FileCheck %s --check-prefix=CORTEX-A5-NOFPU
37 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a5 -mattr=-vfp2sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A5-NOFPU-FAST
3838 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A8-SOFT
3939 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=soft -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A8-SOFT-FAST
4040 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a8 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-A8-HARD
4949 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT
5050 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a9 -float-abi=soft | FileCheck %s --check-prefix=CORTEX-A9-SOFT
5151 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-DEFAULT-FAST
52 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2d16sp | FileCheck %s --check-prefix=CORTEX-A12-NOFPU
53 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2d16sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-NOFPU-FAST
52 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2sp | FileCheck %s --check-prefix=CORTEX-A12-NOFPU
53 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -mattr=-vfp2sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A12-NOFPU-FAST
5454 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a12 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
5555 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 | FileCheck %s --check-prefix=CORTEX-A15
5656 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A15-FAST
5757 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
5858 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 | FileCheck %s --check-prefix=CORTEX-A17-DEFAULT
5959 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-FAST
60 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2d16sp | FileCheck %s --check-prefix=CORTEX-A17-NOFPU
61 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2d16sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST
60 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2sp | FileCheck %s --check-prefix=CORTEX-A17-NOFPU
61 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a17 -mattr=-vfp2sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A17-NOFPU-FAST
6262
6363 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -enable-no-trapping-fp-math | FileCheck %s --check-prefix=NO-TRAPPING-MATH
6464 ; RUN: llc < %s -mtriple=armv7-linux-gnueabi -mcpu=cortex-a15 -denormal-fp-math=ieee | FileCheck %s --check-prefix=DENORMAL-IEEE
9595 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard | FileCheck %s --check-prefix=CORTEX-M4-HARD
9696 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -float-abi=hard -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M4-HARD-FAST
9797 ; RUN: llc < %s -mtriple=thumbv7m-linux-gnueabi -mcpu=cortex-m4 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
98 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2d16sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT
99 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2d16sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-NOFPU-FAST
98 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2sp | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SOFT
99 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-vfp2sp -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-NOFPU-FAST
100100 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-fp64 | FileCheck %s --check-prefix=CORTEX-M7 --check-prefix=CORTEX-M7-SINGLE
101101 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 -mattr=-fp64 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-M7-FAST
102102 ; RUN: llc < %s -mtriple=thumbv7em-linux-gnueabi -mcpu=cortex-m7 | FileCheck %s --check-prefix=CORTEX-M7-DOUBLE
156156 ; RUN: llc < %s -mtriple=armv8.1a-linux-gnueabi -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
157157 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 | FileCheck %s --check-prefix=CORTEX-A7-CHECK
158158 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-CHECK-FAST
159 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2d16sp,-vfp3,-vfp4,-neon,-fp16 | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
160 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2d16sp,-vfp3,-vfp4,-neon,-fp16 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST
159 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2sp,-vfp3,-vfp4,-neon,-fp16 | FileCheck %s --check-prefix=CORTEX-A7-NOFPU
160 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=-vfp2sp,-vfp3,-vfp4,-neon,-fp16 -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-NOFPU-FAST
161161 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon | FileCheck %s --check-prefix=CORTEX-A7-FPUV4
162162 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -enable-sign-dependent-rounding-fp-math | FileCheck %s --check-prefix=DYN-ROUNDING
163163 ; RUN: llc < %s -mtriple=armv7-none-linux-gnueabi -mcpu=cortex-a7 -mattr=+vfp4,-neon -enable-unsafe-fp-math -frame-pointer=all -enable-no-infs-fp-math -enable-no-nans-fp-math -fp-contract=fast | FileCheck %s --check-prefix=CORTEX-A7-FPUV4-FAST
229229 ; RUN: llc < %s -mtriple=armv5-none-linux-gnueabi -mcpu=arm1022e -mattr=+strict-align | FileCheck %s --check-prefix=STRICT-ALIGN
230230
231231 ; ARMv8-R
232 ; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-vfp2d16sp,-fp16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NOFPU
232 ; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-vfp2sp,-fp16 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NOFPU
233233 ; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 -mattr=-neon,-fp64,-d32 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-SP
234234 ; RUN: llc < %s -mtriple=arm-none-none-eabi -mcpu=cortex-r52 | FileCheck %s --check-prefix=ARMv8R --check-prefix=ARMv8R-NEON
235235
None ; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfp2d16sp %s -o - | FileCheck %s -check-prefixes=COMMON,NOVFP
0 ; RUN: llc -mtriple=armv7-none-eabi -mattr=-neon,-vfp2sp %s -o - | FileCheck %s -check-prefixes=COMMON,NOVFP
11 ; RUN: llc -mtriple=armv7-none-eabi -mattr=+neon %s -float-abi=hard -o - | FileCheck %s -check-prefixes=COMMON,VFP
22
33 ; The intent here is to test "X", which says that any operand whatsoever is allowed.
4242 ret void
4343 }
4444
45 attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m4" "target-features"="+armv7e-m,+dsp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2d16sp,+vfp3d16sp,+vfp4d16sp,-aes,-crc,-crypto,-dotprod,-fp16fml,-fullfp16,-hwdiv-arm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" }
45 attributes #0 = { noinline nounwind optnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="cortex-m4" "target-features"="+armv7e-m,+dsp,+fp16,+fpregs,+hwdiv,+thumb-mode,+vfp2sp,+vfp3d16sp,+vfp4d16sp,-aes,-crc,-crypto,-dotprod,-fp16fml,-fullfp16,-hwdiv-arm,-lob,-mve,-mve.fp,-ras,-sb,-sha2" "unsafe-fp-math"="false" "use-soft-float"="false" }
1212 fldmeax sp!, {s0}
1313
1414 @ CHECK-LABEL: aliases
15 @ CHECK: error: operand must be a list of registers in range [d0, d31]
15 @ CHECK: error: operand must be a list of registers in range [d0, d15]
1616 @ CHECK: fstmeax sp!, {s0}
1717 @ CHECK: ^
18 @ CHECK: error: operand must be a list of registers in range [d0, d31]
18 @ CHECK: error: operand must be a list of registers in range [d0, d15]
1919 @ CHECK: fldmfdx sp!, {s0}
2020 @ CHECK: ^
2121
22 @ CHECK: error: operand must be a list of registers in range [d0, d31]
22 @ CHECK: error: operand must be a list of registers in range [d0, d15]
2323 @ CHECK: fstmfdx sp!, {s0}
2424 @ CHECK: ^
25 @ CHECK: error: operand must be a list of registers in range [d0, d31]
25 @ CHECK: error: operand must be a list of registers in range [d0, d15]
2626 @ CHECK: fldmeax sp!, {s0}
2727 @ CHECK: ^
2828
3030 fstmiaxhs r0, {s0}
3131 fstmiaxls r0, {s0}
3232 fstmiaxvs r0, {s0}
33 @ CHECK: error: operand must be a list of registers in range [d0, d31]
33 @ CHECK: error: operand must be a list of registers in range [d0, d15]
3434 @ CHECK: fstmiaxcs r0, {s0}
3535 @ CHECK: ^
36 @ CHECK: error: operand must be a list of registers in range [d0, d31]
36 @ CHECK: error: operand must be a list of registers in range [d0, d15]
3737 @ CHECK: fstmiaxhs r0, {s0}
3838 @ CHECK: ^
39 @ CHECK: error: operand must be a list of registers in range [d0, d31]
39 @ CHECK: error: operand must be a list of registers in range [d0, d15]
4040 @ CHECK: fstmiaxls r0, {s0}
4141 @ CHECK: ^
42 @ CHECK: error: operand must be a list of registers in range [d0, d31]
42 @ CHECK: error: operand must be a list of registers in range [d0, d15]
4343 @ CHECK: fstmiaxvs r0, {s0}
4444 @ CHECK: ^
4545