llvm.org GIT mirror llvm / ffc658b
ARM VLDR/VSTR instructions don't need a size suffix. Canonicallize on the non-suffixed form, but continue to accept assembly that has any correctly sized type suffix. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@144583 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 8 years ago
24 changed file(s) with 107 addition(s) and 114 deletion(s). Raw diff Collapse all Expand all
19951995 class VFPDataTypeInstAlias :
19961996 InstAlias;
19971997 multiclass VFPDT32InstAlias {
1998 def _32 : VFPDataTypeInstAlias;
19981999 def I32 : VFPDataTypeInstAlias;
19992000 def S32 : VFPDataTypeInstAlias;
20002001 def U32 : VFPDataTypeInstAlias;
20022003 def F : VFPDataTypeInstAlias;
20032004 }
20042005 multiclass VFPDT64InstAlias {
2006 def _64 : VFPDataTypeInstAlias;
20052007 def I64 : VFPDataTypeInstAlias;
20062008 def S64 : VFPDataTypeInstAlias;
20072009 def U64 : VFPDataTypeInstAlias;
6868 let canFoldAsLoad = 1, isReMaterializable = 1 in {
6969
7070 def VLDRD : ADI5<0b1101, 0b01, (outs DPR:$Dd), (ins addrmode5:$addr),
71 IIC_fpLoad64, "vldr", ".64\t$Dd, $addr",
71 IIC_fpLoad64, "vldr", "\t$Dd, $addr",
7272 [(set DPR:$Dd, (f64 (load addrmode5:$addr)))]>;
7373
7474 def VLDRS : ASI5<0b1101, 0b01, (outs SPR:$Sd), (ins addrmode5:$addr),
75 IIC_fpLoad32, "vldr", ".32\t$Sd, $addr",
75 IIC_fpLoad32, "vldr", "\t$Sd, $addr",
7676 [(set SPR:$Sd, (load addrmode5:$addr))]> {
7777 // Some single precision VFP instructions may be executed on both NEON and VFP
7878 // pipelines.
8282 } // End of 'let canFoldAsLoad = 1, isReMaterializable = 1 in'
8383
8484 def VSTRD : ADI5<0b1101, 0b00, (outs), (ins DPR:$Dd, addrmode5:$addr),
85 IIC_fpStore64, "vstr", ".64\t$Dd, $addr",
85 IIC_fpStore64, "vstr", "\t$Dd, $addr",
8686 [(store (f64 DPR:$Dd), addrmode5:$addr)]>;
8787
8888 def VSTRS : ASI5<0b1101, 0b00, (outs), (ins SPR:$Sd, addrmode5:$addr),
89 IIC_fpStore32, "vstr", ".32\t$Sd, $addr",
89 IIC_fpStore32, "vstr", "\t$Sd, $addr",
9090 [(store SPR:$Sd, addrmode5:$addr)]> {
9191 // Some single precision VFP instructions may be executed on both NEON and VFP
9292 // pipelines.
11621162
11631163 def : VFP2InstAlias<"fmstat${p}", (FMSTAT pred:$p)>;
11641164
1165 // The size suffix is optional for VLDR/VSTR
1166 def : VFP2InstAlias<"vldr$p $Dd, $addr",
1167 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1168 def : VFP2InstAlias<"vldr$p $Sd, $addr",
1169 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1170 def : VFP2InstAlias<"vstr$p $Dd, $addr",
1171 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1172 def : VFP2InstAlias<"vstr$p $Sd, $addr",
1173 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1174 // The suffix can also by typed.
1175 defm : VFPDT32InstAlias<"vldr$p", "$Sd, $addr",
1165 // VLDR/VSTR accept an optional type suffix.
1166 defm : VFPDT32InstAlias<"vldr${p}", "$Sd, $addr",
11761167 (VLDRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1177 defm : VFPDT32InstAlias<"vstr$p", "$Sd, $addr",
1168 defm : VFPDT32InstAlias<"vstr${p}", "$Sd, $addr",
11781169 (VSTRS SPR:$Sd, addrmode5:$addr, pred:$p)>;
1179 defm : VFPDT64InstAlias<"vldr$p", "$Dd, $addr",
1170 defm : VFPDT64InstAlias<"vldr${p}", "$Dd, $addr",
11801171 (VLDRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
1181 defm : VFPDT64InstAlias<"vstr$p", "$Dd, $addr",
1172 defm : VFPDT64InstAlias<"vstr${p}", "$Dd, $addr",
11821173 (VSTRD DPR:$Dd, addrmode5:$addr, pred:$p)>;
88 br i1 %4, label %bb1, label %bb2
99
1010 bb1:
11 ;CHECK: vstrhi.64
11 ;CHECK: vstrhi
1212 store double %1, double* %y
1313 br label %bb2
1414
55 %arg0_poly16x4_t = alloca <4 x i16> ; <<4 x i16>*> [#uses=1]
66 %out_poly16_t = alloca i16 ; [#uses=1]
77 %"alloca point" = bitcast i32 0 to i32 ; [#uses=0]
8 ; CHECK: vldr.64
8 ; CHECK: vldr
99 %0 = load <4 x i16>* %arg0_poly16x4_t, align 8 ; <<4 x i16>> [#uses=1]
1010 %1 = extractelement <4 x i16> %0, i32 1 ; [#uses=1]
1111 store i16 %1, i16* %out_poly16_t, align 2
99 %4 = ashr i32 %3, 30
1010 %.sum = add i32 %4, 4
1111 %5 = getelementptr inbounds float* %table, i32 %.sum
12 ;CHECK: vldr.32 s
12 ;CHECK: vldr s
1313 %6 = load float* %5, align 4
1414 %tmp11 = insertelement <4 x float> undef, float %6, i32 0
1515 %7 = shl i32 %packedValue, 18
1616 %8 = ashr i32 %7, 30
1717 %.sum12 = add i32 %8, 4
1818 %9 = getelementptr inbounds float* %table, i32 %.sum12
19 ;CHECK: vldr.32 s
19 ;CHECK: vldr s
2020 %10 = load float* %9, align 4
2121 %tmp9 = insertelement <4 x float> %tmp11, float %10, i32 1
2222 %11 = shl i32 %packedValue, 20
2323 %12 = ashr i32 %11, 30
2424 %.sum13 = add i32 %12, 4
2525 %13 = getelementptr inbounds float* %table, i32 %.sum13
26 ;CHECK: vldr.32 s
26 ;CHECK: vldr s
2727 %14 = load float* %13, align 4
2828 %tmp7 = insertelement <4 x float> %tmp9, float %14, i32 2
2929 %15 = shl i32 %packedValue, 22
3030 %16 = ashr i32 %15, 30
3131 %.sum14 = add i32 %16, 4
3232 %17 = getelementptr inbounds float* %table, i32 %.sum14
33 ;CHECK: vldr.32 s
33 ;CHECK: vldr s
3434 %18 = load float* %17, align 4
3535 %tmp5 = insertelement <4 x float> %tmp7, float %18, i32 3
3636 %19 = fmul <4 x float> %tmp5, %2
0 ; RUN: llc -march=arm -mcpu=cortex-a8 < %s | FileCheck %s
11
22 ; Should trigger a NEON store.
3 ; CHECK: vstr.64
3 ; CHECK: vstr
44 define void @f_0_12(i8* nocapture %c) nounwind optsize {
55 entry:
66 call void @llvm.memset.p0i8.i64(i8* %c, i8 0, i64 12, i32 8, i1 false)
2525 ; ARM: t1b
2626 ; THUMB: t1b
2727 %cmp = fcmp oeq float %a, -0.000000e+00
28 ; ARM: vldr.32
28 ; ARM: vldr
2929 ; ARM: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}}
30 ; THUMB: vldr.32
30 ; THUMB: vldr
3131 ; THUMB: vcmpe.f32 s{{[0-9]+}}, s{{[0-9]+}}
3232 br i1 %cmp, label %if.then, label %if.end
3333
6262 ; ARM: t2b
6363 ; THUMB: t2b
6464 %cmp = fcmp oeq double %a, -0.000000e+00
65 ; ARM: vldr.64
65 ; ARM: vldr
6666 ; ARM: vcmpe.f64 d{{[0-9]+}}, d{{[0-9]+}}
67 ; THUMB: vldr.64
67 ; THUMB: vldr
6868 ; THUMB: vcmpe.f64 d{{[0-9]+}}, d{{[0-9]+}}
6969 br i1 %cmp, label %if.then, label %if.end
7070
4141
4242 define double @h(double* %v) {
4343 ;CHECK: h:
44 ;CHECK: vldr.64
44 ;CHECK: vldr
4545 ;CHECK-NEXT: vmov
4646 entry:
4747 %tmp = load double* %v ; [#uses=1]
1313 ; FINITE: beq
1414
1515 ; NAN: t1:
16 ; NAN: vldr.32 s0,
17 ; NAN: vldr.32 s1,
16 ; NAN: vldr s0,
17 ; NAN: vldr s1,
1818 ; NAN: vcmpe.f32 s1, s0
1919 ; NAN: vmrs apsr_nzcv, fpscr
2020 ; NAN: beq
77
88 define float @f2(float* %v, float %u) {
99 ; CHECK: f2:
10 ; CHECK: vldr.32{{.*}}[
10 ; CHECK: vldr{{.*}}[
1111 %tmp = load float* %v ; [#uses=1]
1212 %tmp1 = fadd float %tmp, %u ; [#uses=1]
1313 ret float %tmp1
1515
1616 define float @f2offset(float* %v, float %u) {
1717 ; CHECK: f2offset:
18 ; CHECK: vldr.32{{.*}}, #4]
18 ; CHECK: vldr{{.*}}, #4]
1919 %addr = getelementptr float* %v, i32 1
2020 %tmp = load float* %addr
2121 %tmp1 = fadd float %tmp, %u
2424
2525 define float @f2noffset(float* %v, float %u) {
2626 ; CHECK: f2noffset:
27 ; CHECK: vldr.32{{.*}}, #-4]
27 ; CHECK: vldr{{.*}}, #-4]
2828 %addr = getelementptr float* %v, i32 -1
2929 %tmp = load float* %addr
3030 %tmp1 = fadd float %tmp, %u
3333
3434 define void @f3(float %a, float %b, float* %v) {
3535 ; CHECK: f3:
36 ; CHECK: vstr.32{{.*}}[
36 ; CHECK: vstr{{.*}}[
3737 %tmp = fadd float %a, %b ; [#uses=1]
3838 store float %tmp, float* %v
3939 ret void
33 ; constant offset addressing, so that each of the following stores
44 ; uses the same register.
55
6 ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32]
7 ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64]
8 ; CHECK: vstr.32 s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96]
6 ; CHECK: vstr s{{.*}}, [{{(r[0-9]+)|(lr)}}, #32]
7 ; CHECK: vstr s{{.*}}, [{{(r[0-9]+)|(lr)}}, #64]
8 ; CHECK: vstr s{{.*}}, [{{(r[0-9]+)|(lr)}}, #96]
99
1010 ; We can also save a register in the outer loop, but that requires
1111 ; performing LSR on the outer loop.
None ; RUN: llc < %s -march=arm -mattr=+neon | grep vldr.64 | count 4
1 ; RUN: llc < %s -march=arm -mattr=+neon | grep vstr.64
0 ; RUN: llc < %s -march=arm -mattr=+neon | grep vldr | count 4
1 ; RUN: llc < %s -march=arm -mattr=+neon | grep vstr
22 ; RUN: llc < %s -march=arm -mattr=+neon | grep vmov
33
44 define void @t1(<2 x i32>* %r, <4 x i16>* %a, <4 x i16>* %b) nounwind {
154154
155155 define <8 x i8> @t6(i8* %A, <8 x i8>* %B) nounwind {
156156 ; CHECK: t6:
157 ; CHECK: vldr.64
157 ; CHECK: vldr
158158 ; CHECK: vorr d[[D0:[0-9]+]], d[[D1:[0-9]+]]
159159 ; CHECK-NEXT: vld2.8 {d[[D1]][1], d[[D0]][1]}
160160 %tmp1 = load <8 x i8>* %B ; <<8 x i8>> [#uses=2]
239239 ; PR7157
240240 define arm_aapcs_vfpcc float @t9(%0* nocapture, %3* nocapture) nounwind {
241241 ; CHECK: t9:
242 ; CHECK: vldr.64
242 ; CHECK: vldr
243243 ; CHECK-NOT: vmov d{{.*}}, d16
244244 ; CHECK: vmov.i32 d17
245245 ; CHECK-NEXT: vstmia r0, {d16, d17}
1111 ;
1212 ; CHECK: f1
1313 ; CHECK: vmov s1, r0
14 ; CHECK: vldr.32 s0, LCPI
14 ; CHECK: vldr s0, LCPI
1515 ; The vector must be spilled:
16 ; CHECK: vstr.64 d0,
16 ; CHECK: vstr d0,
1717 ; CHECK: asm clobber d0
1818 ; And reloaded after the asm:
19 ; CHECK: vldr.64 [[D16:d[0-9]+]],
20 ; CHECK: vstr.64 [[D16]], [r1]
19 ; CHECK: vldr [[D16:d[0-9]+]],
20 ; CHECK: vstr [[D16]], [r1]
2121 define void @f1(float %x, <2 x float>* %p) {
2222 %v1 = insertelement <2 x float> undef, float %x, i32 1
2323 %v2 = insertelement <2 x float> %v1, float 0x400921FB60000000, i32 0
3636 ; virtual register. It doesn't read the old value.
3737 ;
3838 ; CHECK: f2
39 ; CHECK: vldr.32 s0, LCPI
39 ; CHECK: vldr s0, LCPI
4040 ; The vector must not be spilled:
41 ; CHECK-NOT: vstr.64
41 ; CHECK-NOT: vstr
4242 ; CHECK: asm clobber d0
4343 ; But instead rematerialize after the asm:
44 ; CHECK: vldr.32 [[S0:s[0-9]+]], LCPI
45 ; CHECK: vstr.64 [[D0:d[0-9]+]], [r0]
44 ; CHECK: vldr [[S0:s[0-9]+]], LCPI
45 ; CHECK: vstr [[D0:d[0-9]+]], [r0]
4646 define void @f2(<2 x float>* %p) {
4747 %v2 = insertelement <2 x float> undef, float 0x400921FB60000000, i32 0
4848 %y = call double asm sideeffect "asm clobber $0", "=w,0,~{d1},~{d2},~{d3},~{d4},~{d5},~{d6},~{d7},~{d8},~{d9},~{d10},~{d11},~{d12},~{d13},~{d14},~{d15},~{d16},~{d17},~{d18},~{d19},~{d20},~{d21},~{d22},~{d23},~{d24},~{d25},~{d26},~{d27},~{d28},~{d29},~{d30},~{d31}"(<2 x float> %v2) nounwind
11
22 define <8 x i8> @v_bsli8(<8 x i8>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
33 ;CHECK: v_bsli8:
4 ;CHECK: vldr.64
5 ;CHECK: vldr.64
4 ;CHECK: vldr
5 ;CHECK: vldr
66 ;CHECK: vbsl
77 %tmp1 = load <8 x i8>* %A
88 %tmp2 = load <8 x i8>* %B
1515
1616 define <4 x i16> @v_bsli16(<4 x i16>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
1717 ;CHECK: v_bsli16:
18 ;CHECK: vldr.64
19 ;CHECK: vldr.64
18 ;CHECK: vldr
19 ;CHECK: vldr
2020 ;CHECK: vbsl
2121 %tmp1 = load <4 x i16>* %A
2222 %tmp2 = load <4 x i16>* %B
2929
3030 define <2 x i32> @v_bsli32(<2 x i32>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
3131 ;CHECK: v_bsli32:
32 ;CHECK: vldr.64
33 ;CHECK: vldr.64
32 ;CHECK: vldr
33 ;CHECK: vldr
3434 ;CHECK: vbsl
3535 %tmp1 = load <2 x i32>* %A
3636 %tmp2 = load <2 x i32>* %B
4343
4444 define <1 x i64> @v_bsli64(<1 x i64>* %A, <1 x i64>* %B, <1 x i64>* %C) nounwind {
4545 ;CHECK: v_bsli64:
46 ;CHECK: vldr.64
47 ;CHECK: vldr.64
48 ;CHECK: vldr.64
46 ;CHECK: vldr
47 ;CHECK: vldr
48 ;CHECK: vldr
4949 ;CHECK: vbsl
5050 %tmp1 = load <1 x i64>* %A
5151 %tmp2 = load <1 x i64>* %B
253253 ;CHECK: redundantVdup:
254254 ;CHECK: vmov.i8
255255 ;CHECK-NOT: vdup.8
256 ;CHECK: vstr.64
256 ;CHECK: vstr
257257 define void @redundantVdup(<8 x i8>* %ptr) nounwind {
258258 %1 = insertelement <8 x i8> undef, i8 -128, i32 0
259259 %2 = shufflevector <8 x i8> %1, <8 x i8> undef, <8 x i32> zeroinitializer
7979 ; so they are not split up into i32 values. Radar 8755338.
8080 define void @i64_buildvector(i64* %ptr, <2 x i64>* %vp) nounwind {
8181 ; CHECK: i64_buildvector
82 ; CHECK: vldr.64
82 ; CHECK: vldr
8383 %t0 = load i64* %ptr, align 4
8484 %t1 = insertelement <2 x i64> undef, i64 %t0, i32 0
8585 store <2 x i64> %t1, <2 x i64>* %vp
8888
8989 define void @i64_insertelement(i64* %ptr, <2 x i64>* %vp) nounwind {
9090 ; CHECK: i64_insertelement
91 ; CHECK: vldr.64
91 ; CHECK: vldr
9292 %t0 = load i64* %ptr, align 4
9393 %vec = load <2 x i64>* %vp
9494 %t1 = insertelement <2 x i64> %vec, i64 %t0, i32 0
9898
9999 define void @i64_extractelement(i64* %ptr, <2 x i64>* %vp) nounwind {
100100 ; CHECK: i64_extractelement
101 ; CHECK: vstr.64
101 ; CHECK: vstr
102102 %vec = load <2 x i64>* %vp
103103 %t1 = extractelement <2 x i64> %vec, i32 0
104104 store i64 %t1, i64* %ptr
137137 ; Make sure this doesn't crash
138138 define arm_aapcscc void @test_elem_mismatch(<2 x i64>* nocapture %src, <4 x i16>* nocapture %dest) nounwind {
139139 ; CHECK: test_elem_mismatch:
140 ; CHECK: vstr.64
140 ; CHECK: vstr
141141 %tmp0 = load <2 x i64>* %src, align 16
142142 %tmp1 = bitcast <2 x i64> %tmp0 to <4 x i32>
143143 %tmp2 = extractelement <4 x i32> %tmp1, i32 0
22
33 ; The 0.0 constant is loaded from the constant pool and kept in a register.
44 ; CHECK: %entry
5 ; CHECK: vldr.32 s
5 ; CHECK: vldr s
66 ; The float loop variable is initialized with a vmovs from the constant register.
77 ; The vmovs is first widened to a vmovd, and then converted to a vorr because of the v2f32 vadd.f32.
88 ; CHECK: vorr [[DL:d[0-9]+]], [[DN:d[0-9]+]]
44 entry:
55 ; -- The loop following the load should only use a single add-literation
66 ; instruction.
7 ; CHECK: ldr.64
7 ; CHECK: vldr
88 ; CHECK: adds r{{[0-9]+.*}}#1
99 ; CHECK-NOT: adds
1010 ; CHECK: subsections_via_symbols
2222 %4 = insertelement <2 x double> %2, double %V.0.ph, i32 1 ; <<2 x double>> [#uses=2]
2323 ; Constant pool load followed by add.
2424 ; Then clobber the loaded register, not the sum.
25 ; CHECK: vldr.64 [[LDR:d.*]],
25 ; CHECK: vldr [[LDR:d.*]],
2626 ; CHECK: LPC0_0:
2727 ; CHECK: vadd.f64 [[ADD:d.*]], [[LDR]], [[LDR]]
2828 ; CHECK-NOT: vmov.f64 [[ADD]]
171171 @ CHECK: vmov r0, r1, d16 @ encoding: [0x30,0x0b,0x51,0xec]
172172 vmov r0, r1, d16
173173
174 @ CHECK: vldr.64 d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
175 @ CHECK: vldr.32 s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
176 @ CHECK: vldr.64 d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
174 @ CHECK: vldr d17, [r0] @ encoding: [0x00,0x1b,0xd0,0xed]
175 @ CHECK: vldr s0, [lr] @ encoding: [0x00,0x0a,0x9e,0xed]
176 @ CHECK: vldr d0, [lr] @ encoding: [0x00,0x0b,0x9e,0xed]
177177
178178 vldr.64 d17, [r0]
179 vldr s0, [lr]
180 vldr d0, [lr]
181
182 @ CHECK: vldr.64 d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
183 @ CHECK: vldr.64 d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
179 vldr.i32 s0, [lr]
180 vldr.d d0, [lr]
181
182 @ CHECK: vldr d1, [r2, #32] @ encoding: [0x08,0x1b,0x92,0xed]
183 @ CHECK: vldr d1, [r2, #-32] @ encoding: [0x08,0x1b,0x12,0xed]
184184 vldr.64 d1, [r2, #32]
185 vldr.64 d1, [r2, #-32]
186
187 @ CHECK: vldr.64 d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
185 vldr.f64 d1, [r2, #-32]
186
187 @ CHECK: vldr d2, [r3] @ encoding: [0x00,0x2b,0x93,0xed]
188188 vldr.64 d2, [r3]
189189
190 @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
191 @ CHECK: vldr.64 d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
192 @ CHECK: vldr.64 d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed]
190 @ CHECK: vldr d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
191 @ CHECK: vldr d3, [pc] @ encoding: [0x00,0x3b,0x9f,0xed]
192 @ CHECK: vldr d3, [pc, #-0] @ encoding: [0x00,0x3b,0x1f,0xed]
193193 vldr.64 d3, [pc]
194194 vldr.64 d3, [pc,#0]
195195 vldr.64 d3, [pc,#-0]
196196
197 @ CHECK: vldr.32 s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed]
197 @ CHECK: vldr s13, [r0] @ encoding: [0x00,0x6a,0xd0,0xed]
198198 vldr.32 s13, [r0]
199199
200 @ CHECK: vldr.32 s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed]
201 @ CHECK: vldr.32 s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed]
200 @ CHECK: vldr s1, [r2, #32] @ encoding: [0x08,0x0a,0xd2,0xed]
201 @ CHECK: vldr s1, [r2, #-32] @ encoding: [0x08,0x0a,0x52,0xed]
202202 vldr.32 s1, [r2, #32]
203203 vldr.32 s1, [r2, #-32]
204204
205 @ CHECK: vldr.32 s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed]
205 @ CHECK: vldr s2, [r3] @ encoding: [0x00,0x1a,0x93,0xed]
206206 vldr.32 s2, [r3]
207207
208 @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
209 @ CHECK: vldr.32 s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
210 @ CHECK: vldr.32 s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed]
208 @ CHECK: vldr s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
209 @ CHECK: vldr s5, [pc] @ encoding: [0x00,0x2a,0xdf,0xed]
210 @ CHECK: vldr s5, [pc, #-0] @ encoding: [0x00,0x2a,0x5f,0xed]
211211 vldr.32 s5, [pc]
212212 vldr.32 s5, [pc,#0]
213213 vldr.32 s5, [pc,#-0]
214214
215 @ CHECK: vstr.64 d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
216 @ CHECK: vstr.64 d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
217 @ CHECK: vstr.64 d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
218 @ CHECK: vstr.32 s0, [lr] @ encoding: [0x00,0x0a,0x8e,0xed]
219 @ CHECK: vstr.64 d0, [lr] @ encoding: [0x00,0x0b,0x8e,0xed]
215 @ CHECK: vstr d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
216 @ CHECK: vstr d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
217 @ CHECK: vstr d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
218 @ CHECK: vstr s0, [lr] @ encoding: [0x00,0x0a,0x8e,0xed]
219 @ CHECK: vstr d0, [lr] @ encoding: [0x00,0x0b,0x8e,0xed]
220220
221221 vstr.64 d4, [r1]
222222 vstr.64 d4, [r1, #24]
224224 vstr s0, [lr]
225225 vstr d0, [lr]
226226
227 @ CHECK: vstr.32 s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed]
228 @ CHECK: vstr.32 s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed]
229 @ CHECK: vstr.32 s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed]
227 @ CHECK: vstr s4, [r1] @ encoding: [0x00,0x2a,0x81,0xed]
228 @ CHECK: vstr s4, [r1, #24] @ encoding: [0x06,0x2a,0x81,0xed]
229 @ CHECK: vstr s4, [r1, #-24] @ encoding: [0x06,0x2a,0x01,0xed]
230230 vstr.32 s4, [r1]
231231 vstr.32 s4, [r1, #24]
232232 vstr.32 s4, [r1, #-24]
214214 # CHECK: vldmdb r2!, {s7, s8, s9, s10, s11}
215215 0x05 0x3a 0x72 0xed
216216
217 # CHECK: vldr.32 s23, [r2, #660]
217 # CHECK: vldr s23, [r2, #660]
218218 0xa5 0xba 0xd2 0xed
219219
220220 # CHECK: strtvc r5, [r3], r0, lsr #20
151151 # CHECK: vmov r0, r1, d16
152152
153153 0x00 0x1b 0xd0 0xed
154 # CHECK: vldr.64 d17, [r0]
154 # CHECK: vldr d17, [r0]
155155
156156 0x08 0x1b 0x92 0xed
157157 0x08 0x1b 0x12 0xed
158 # CHECK: vldr.64 d1, [r2, #32]
159 # CHECK: vldr.64 d1, [r2, #-32]
158 # CHECK: vldr d1, [r2, #32]
159 # CHECK: vldr d1, [r2, #-32]
160160
161161 0x00 0x2b 0x93 0xed
162 # CHECK: vldr.64 d2, [r3]
162 # CHECK: vldr d2, [r3]
163163
164164 0x00 0x3b 0x9f 0xed
165 # CHECK: vldr.64 d3, [pc]
165 # CHECK: vldr d3, [pc]
166166
167167 0x00 0x6a 0xd0 0xed
168 # CHECK: vldr.32 s13, [r0]
168 # CHECK: vldr s13, [r0]
169169
170170 0x08 0x0a 0xd2 0xed
171171 0x08 0x0a 0x52 0xed
172 # CHECK: vldr.32 s1, [r2, #32]
173 # CHECK: vldr.32 s1, [r2, #-32]
172 # CHECK: vldr s1, [r2, #32]
173 # CHECK: vldr s1, [r2, #-32]
174174
175175 0x00 0x1a 0x93 0xed
176 # CHECK: vldr.32 s2, [r3]
176 # CHECK: vldr s2, [r3]
177177
178178 0x00 0x2a 0xdf 0xed
179 # CHECK: vldr.32 s5, [pc]
179 # CHECK: vldr s5, [pc]
180180
181181 0x00 0x4b 0x81 0xed
182182 0x06 0x4b 0x81 0xed
183183 0x06 0x4b 0x01 0xed
184 # CHECK: vstr.64 d4, [r1]
185 # CHECK: vstr.64 d4, [r1, #24]
186 # CHECK: vstr.64 d4, [r1, #-24]
184 # CHECK: vstr d4, [r1]
185 # CHECK: vstr d4, [r1, #24]
186 # CHECK: vstr d4, [r1, #-24]
187187
188188 0x00 0x2a 0x81 0xed
189189 0x06 0x2a 0x81 0xed
190190 0x06 0x2a 0x01 0xed
191 # CHECK: vstr.32 s4, [r1]
192 # CHECK: vstr.32 s4, [r1, #24]
193 # CHECK: vstr.32 s4, [r1, #-24]
191 # CHECK: vstr s4, [r1]
192 # CHECK: vstr s4, [r1, #24]
193 # CHECK: vstr s4, [r1, #-24]
194194
195195 0x0c 0x2b 0x91 0xec
196196 0x06 0x1a 0x91 0xec