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[ARM] Add Thumb2 ADD with SP narrowing from 3 operand to 2 Differential Revision: http://reviews.llvm.org/D11131 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242035 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Douglass 5 years ago
2 changed file(s) with 30 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
54855485 auto Op4Reg = Op4.getReg();
54865486
54875487 // For most Thumb2 cases we just generate the 3 operand form and reduce
5488 // it in processInstruction(), but for ADD involving PC the the 3 operand
5489 // form won't accept PC so we do the transformation here.
5488 // it in processInstruction(), but the 3 operand form of ADD (t2ADDrr)
5489 // won't accept SP or PC so we do the transformation here taking care
5490 // with immediate range in the 'add sp, sp #imm' case.
54905491 auto &Op5 = static_cast(*Operands[5]);
54915492 if (isThumbTwo()) {
5492 if (Mnemonic != "add" ||
5493 !(Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5494 (Op5.isReg() && Op5.getReg() == ARM::PC)))
5493 if (Mnemonic != "add")
5494 return;
5495 bool TryTransform = Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
5496 (Op5.isReg() && Op5.getReg() == ARM::PC);
5497 if (!TryTransform) {
5498 TryTransform = (Op3Reg == ARM::SP || Op4Reg == ARM::SP ||
5499 (Op5.isReg() && Op5.getReg() == ARM::SP)) &&
5500 !(Op3Reg == ARM::SP && Op4Reg == ARM::SP &&
5501 Op5.isImm() && !Op5.isImm0_508s4());
5502 }
5503 if (!TryTransform)
54955504 return;
54965505 } else if (!isThumbOne())
54975506 return;
7272 // CHECK: add pc, r2 @ encoding: [0x97,0x44]
7373 ADD pc, r2, pc // T2
7474 // CHECK: add pc, r2 @ encoding: [0x97,0x44]
75 ADD pc, pc, sp // T2
76 // CHECK: add pc, sp @ encoding: [0xef,0x44]
77 ADD pc, sp, pc // T2
78 // CHECK: add pc, sp, pc @ encoding: [0xef,0x44]
7579
7680 // ADD (SP plus immediate) A8.8.9
7781 ADD sp, sp, #20 // T2
7882 // FIXME: ARMARM says 'add sp, sp, #20'
79 // CHECK: add sp, #20 @ encoding: [0x05,0xb0]
83 // CHECK: add sp, #20 @ encoding: [0x05,0xb0]
84 ADD sp, sp, #508 // T2
85 // CHECK: add sp, #508 @ encoding: [0x7f,0xb0]
86 ADD sp, sp, #512 // T3
87 // CHECK: add.w sp, sp, #512 @ encoding: [0x0d,0xf5,0x00,0x7d]
8088
8189 // ADD (SP plus register) A8.8.10 (commutative)
8290 ADD r9, sp, r9 // T1
8391 // CHECK: add r9, sp, r9 @ encoding: [0xe9,0x44]
92 ADD r9, r9, sp // T1
93 // FIXME: ARMARM says 'add r9, sp, r9'
94 // CHECK: add r9, sp @ encoding: [0xe9,0x44]
8495 ADD sp, sp, r10 // T2
8596 // CHECK: add sp, r10 @ encoding: [0xd5,0x44]
97 ADD sp, r10, sp // T2
98 // CHECK: add sp, r10 @ encoding: [0xd5,0x44]
99 ADD sp, sp, pc // T2
100 // CHECK: add sp, pc @ encoding: [0xfd,0x44]
86101
87102 // AND (commutative)
88103 ANDS r0, r2, r1 // Must be wide - 3 distinct registers