llvm.org GIT mirror llvm / ffc0e73
Change createAsmParser to take a MCSubtargetInfo instead of triple, CPU, and feature string. Parsing some asm directives can change subtarget state (e.g. .code 16) and it must be reflected in other modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance must be shared. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@134795 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
30 changed file(s) with 387 addition(s) and 72 deletion(s). Raw diff Collapse all Expand all
3333 const unsigned *ForwardingPathes; // Forwarding pathes
3434 unsigned NumFeatures; // Number of processor features
3535 unsigned NumProcs; // Number of processors
36 uint64_t FeatureBits; // Feature bits for current CPU
36
37 uint64_t FeatureBits; // Feature bits for current CPU + FS
3738
3839 public:
3940 void InitMCSubtargetInfo(StringRef CPU, StringRef FS,
5354 /// feature string), recompute and return feature bits.
5455 uint64_t ReInitMCSubtargetInfo(StringRef CPU, StringRef FS);
5556
57 /// ToggleFeature - Toggle a feature and returns the re-computed feature
58 /// bits. This version does not change the implied bits.
59 uint64_t ToggleFeature(uint64_t FB);
60
61 /// ToggleFeature - Toggle a feature and returns the re-computed feature
62 /// bits. This version will also change all implied bits.
63 uint64_t ToggleFeature(StringRef FS);
64
5665 /// getInstrItineraryForCPU - Get scheduling itinerary of a CPU.
5766 ///
5867 InstrItineraryData getInstrItineraryForCPU(StringRef CPU) const;
8181 /// Adding Features.
8282 void AddFeature(const StringRef String, bool IsEnabled = true);
8383
84 /// ToggleFeature - Toggle a feature and returns the newly updated feature
85 /// bits.
86 uint64_t ToggleFeature(uint64_t Bits, const StringRef String,
87 const SubtargetFeatureKV *FeatureTable,
88 size_t FeatureTableSize);
89
8490 /// Get feature bits of a CPU.
8591 uint64_t getFeatureBits(const StringRef CPU,
8692 const SubtargetFeatureKV *CPUTable,
3535 class MCInstrInfo;
3636 class MCRegisterInfo;
3737 class MCStreamer;
38 class MCSubtargetInfo;
3839 class TargetAsmBackend;
3940 class TargetAsmLexer;
4041 class TargetAsmParser;
6869 StringRef TT);
6970 typedef MCInstrInfo *(*MCInstrInfoCtorFnTy)(void);
7071 typedef MCRegisterInfo *(*MCRegInfoCtorFnTy)(void);
72 typedef MCSubtargetInfo *(*MCSubtargetInfoCtorFnTy)(StringRef TT,
73 StringRef CPU,
74 StringRef Features);
7175 typedef TargetMachine *(*TargetMachineCtorTy)(const Target &T,
7276 const std::string &TT,
7377 const std::string &CPU,
7882 const std::string &TT);
7983 typedef TargetAsmLexer *(*AsmLexerCtorTy)(const Target &T,
8084 const MCAsmInfo &MAI);
81 typedef TargetAsmParser *(*AsmParserCtorTy)(StringRef TT,
82 StringRef CPU, StringRef Features,
85 typedef TargetAsmParser *(*AsmParserCtorTy)(MCSubtargetInfo &STI,
8386 MCAsmParser &P);
8487 typedef MCDisassembler *(*MCDisassemblerCtorTy)(const Target &T);
8588 typedef MCInstPrinter *(*MCInstPrinterCtorTy)(const Target &T,
136139 /// if registered.
137140 MCRegInfoCtorFnTy MCRegInfoCtorFn;
138141
142 /// MCSubtargetInfoCtorFn - Constructor function for this target's
143 /// MCSubtargetInfo, if registered.
144 MCSubtargetInfoCtorFnTy MCSubtargetInfoCtorFn;
145
139146 /// TargetMachineCtorFn - Construction function for this target's
140147 /// TargetMachine, if registered.
141148 TargetMachineCtorTy TargetMachineCtorFn;
259266 if (!MCRegInfoCtorFn)
260267 return 0;
261268 return MCRegInfoCtorFn();
269 }
270
271 /// createMCSubtargetInfo - Create a MCSubtargetInfo implementation.
272 ///
273 /// \arg Triple - This argument is used to determine the target machine
274 /// feature set; it should always be provided. Generally this should be
275 /// either the target triple from the module, or the target triple of the
276 /// host if that does not exist.
277 /// \arg CPU - This specifies the name of the target CPU.
278 /// \arg Features - This specifies the string representation of the
279 /// additional target features.
280 MCSubtargetInfo *createMCSubtargetInfo(StringRef Triple, StringRef CPU,
281 StringRef Features) const {
282 if (!MCSubtargetInfoCtorFn)
283 return 0;
284 return MCSubtargetInfoCtorFn(Triple, CPU, Features);
262285 }
263286
264287 /// createTargetMachine - Create a target specific machine implementation
298321 ///
299322 /// \arg Parser - The target independent parser implementation to use for
300323 /// parsing and lexing.
301 TargetAsmParser *createAsmParser(StringRef Triple, StringRef CPU,
302 StringRef Features,
324 TargetAsmParser *createAsmParser(MCSubtargetInfo &STI,
303325 MCAsmParser &Parser) const {
304326 if (!AsmParserCtorFn)
305327 return 0;
306 return AsmParserCtorFn(Triple, CPU, Features, Parser);
328 return AsmParserCtorFn(STI, Parser);
307329 }
308330
309331 /// createAsmPrinter - Create a target specific assembly printer pass. This
505527 T.MCRegInfoCtorFn = Fn;
506528 }
507529
530 /// RegisterMCSubtargetInfo - Register a MCSubtargetInfo implementation for
531 /// the given target.
532 ///
533 /// Clients are responsible for ensuring that registration doesn't occur
534 /// while another thread is attempting to access the registry. Typically
535 /// this is done by initializing all targets at program startup.
536 ///
537 /// @param T - The target being registered.
538 /// @param Fn - A function to construct a MCSubtargetInfo for the target.
539 static void RegisterMCSubtargetInfo(Target &T,
540 Target::MCSubtargetInfoCtorFnTy Fn) {
541 // Ignore duplicate registration.
542 if (!T.MCSubtargetInfoCtorFn)
543 T.MCSubtargetInfoCtorFn = Fn;
544 }
545
508546 /// RegisterTargetMachine - Register a TargetMachine implementation for the
509547 /// given target.
510548 ///
781819 }
782820 };
783821
822 /// RegisterMCSubtargetInfo - Helper template for registering a target
823 /// subtarget info implementation. This invokes the static "Create" method
824 /// on the class to actually do the construction. Usage:
825 ///
826 /// extern "C" void LLVMInitializeFooTarget() {
827 /// extern Target TheFooTarget;
828 /// RegisterMCSubtargetInfo X(TheFooTarget);
829 /// }
830 template
831 struct RegisterMCSubtargetInfo {
832 RegisterMCSubtargetInfo(Target &T) {
833 TargetRegistry::RegisterMCSubtargetInfo(T, &Allocator);
834 }
835 private:
836 static MCSubtargetInfo *Allocator(StringRef TT, StringRef CPU,
837 StringRef FS) {
838 return new MCSubtargetInfoImpl();
839 }
840 };
841
842 /// RegisterMCSubtargetInfoFn - Helper template for registering a target
843 /// subtarget info implementation. This invokes the specified function to
844 /// do the construction. Usage:
845 ///
846 /// extern "C" void LLVMInitializeFooTarget() {
847 /// extern Target TheFooTarget;
848 /// RegisterMCSubtargetInfoFn X(TheFooTarget, TheFunction);
849 /// }
850 struct RegisterMCSubtargetInfoFn {
851 RegisterMCSubtargetInfoFn(Target &T, Target::MCSubtargetInfoCtorFnTy Fn) {
852 TargetRegistry::RegisterMCSubtargetInfo(T, Fn);
853 }
854 };
855
784856 /// RegisterTargetMachine - Helper template for registering a target machine
785857 /// implementation, for use in the target machine initialization
786858 /// function. Usage:
858930 }
859931
860932 private:
861 static TargetAsmParser *Allocator(StringRef TT, StringRef CPU,
862 StringRef FS, MCAsmParser &P) {
863 return new AsmParserImpl(TT, CPU, FS, P);
933 static TargetAsmParser *Allocator(MCSubtargetInfo &STI, MCAsmParser &P) {
934 return new AsmParserImpl(STI, P);
864935 }
865936 };
866937
2525 #define LLVM_TARGET(TargetName) void LLVMInitialize##TargetName##Target();
2626 #include "llvm/Config/Targets.def"
2727
28 #define LLVM_TARGET(TargetName) \
29 void LLVMInitialize##TargetName##MCSubtargetInfo();
30 #include "llvm/Config/Targets.def"
31
2832 // Declare all of the available assembly printer initialization functions.
2933 #define LLVM_ASM_PRINTER(TargetName) void LLVMInitialize##TargetName##AsmPrinter();
3034 #include "llvm/Config/AsmPrinters.def"
3438 #include "llvm/Config/AsmParsers.def"
3539
3640 // Declare all of the available disassembler initialization functions.
37 #define LLVM_DISASSEMBLER(TargetName) void LLVMInitialize##TargetName##Disassembler();
41 #define LLVM_DISASSEMBLER(TargetName) \
42 void LLVMInitialize##TargetName##Disassembler();
3843 #include "llvm/Config/Disassemblers.def"
3944 }
4045
5964 InitializeAllTargetInfos();
6065
6166 #define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##Target();
67 #include "llvm/Config/Targets.def"
68 }
69
70 /// InitializeAllMCSubtargetInfos - The main program should call this function
71 /// if it wants access to all available subtarget infos for targets that LLVM
72 /// is configured to support, to make them available via the TargetRegistry.
73 ///
74 /// It is legal for a client to make multiple calls to this function.
75 inline void InitializeAllMCSubtargetInfos() {
76 #define LLVM_TARGET(TargetName) LLVMInitialize##TargetName##MCSubtargetInfo();
6277 #include "llvm/Config/Targets.def"
6378 }
6479
2020 #include "llvm/CodeGen/MachineModuleInfo.h"
2121 #include "llvm/MC/MCAsmInfo.h"
2222 #include "llvm/MC/MCStreamer.h"
23 #include "llvm/MC/MCSubtargetInfo.h"
2324 #include "llvm/MC/MCSymbol.h"
2425 #include "llvm/Target/TargetAsmParser.h"
2526 #include "llvm/Target/TargetMachine.h"
111112 OutContext, OutStreamer,
112113 *MAI));
113114
114 OwningPtr
115 TAP(TM.getTarget().createAsmParser(TM.getTargetTriple(),
116 TM.getTargetCPU(),
117 TM.getTargetFeatureString(),
118 *Parser));
115 // FIXME: It would be nice if we can avoid createing a new instance of
116 // MCSubtargetInfo here given TargetSubtargetInfo is available. However,
117 // we have to watch out for asm directives which can change subtarget
118 // state. e.g. .code 16, .code 32.
119 OwningPtr
120 STI(TM.getTarget().createMCSubtargetInfo(TM.getTargetTriple(),
121 TM.getTargetCPU(),
122 TM.getTargetFeatureString()));
123 OwningPtr TAP(TM.getTarget().createAsmParser(*STI, *Parser));
119124 if (!TAP)
120125 report_fatal_error("Inline asm not supported by this streamer because"
121126 " we don't have an asm parser for this target\n");
2222 #include "llvm/MC/MCInst.h"
2323 #include "llvm/MC/MCInstPrinter.h"
2424 #include "llvm/MC/MCStreamer.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
2526 #include "llvm/MC/MCParser/AsmLexer.h"
2627 #include "llvm/MC/MCParser/MCAsmParser.h"
2728 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
372373 *AsmInfo));
373374
374375 StringRef triple = tripleFromArch(Key.Arch);
375 OwningPtr<TargetAsmParser> TargetParser(Tgt->createAsmParser(triple, "", "",
376 OwningPtr<MCSubtargetInfo> STI(Tgt->createMCSubtargetInfo(triple, "", ""));
377 OwningPtr TargetParser(Tgt->createAsmParser(*STI,
376378 *genericParser));
377379
378380 AsmToken OpcodeToken = genericParser->Lex();
4747 return FeatureBits;
4848 }
4949
50 /// ToggleFeature - Toggle a feature and returns the re-computed feature
51 /// bits. This version does not change the implied bits.
52 uint64_t MCSubtargetInfo::ToggleFeature(uint64_t FB) {
53 FeatureBits ^= FB;
54 return FeatureBits;
55 }
56
57 /// ToggleFeature - Toggle a feature and returns the re-computed feature
58 /// bits. This version will also change all implied bits.
59 uint64_t MCSubtargetInfo::ToggleFeature(StringRef FS) {
60 SubtargetFeatures Features;
61 FeatureBits = Features.ToggleFeature(FeatureBits, FS,
62 ProcFeatures, NumFeatures);
63 return FeatureBits;
64 }
65
66
5067 InstrItineraryData
5168 MCSubtargetInfo::getInstrItineraryForCPU(StringRef CPU) const {
5269 assert(ProcItins && "Instruction itineraries information not available!");
223223 }
224224 }
225225
226 /// ToggleFeature - Toggle a feature and returns the newly updated feature
227 /// bits.
228 uint64_t
229 SubtargetFeatures::ToggleFeature(uint64_t Bits, const StringRef Feature,
230 const SubtargetFeatureKV *FeatureTable,
231 size_t FeatureTableSize) {
232 // Find feature in table.
233 const SubtargetFeatureKV *FeatureEntry =
234 Find(StripFlag(Feature), FeatureTable, FeatureTableSize);
235 // If there is a match
236 if (FeatureEntry) {
237 if ((Bits & FeatureEntry->Value) == FeatureEntry->Value) {
238 Bits &= ~FeatureEntry->Value;
239
240 // For each feature that implies this, clear it.
241 ClearImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize);
242 } else {
243 Bits |= FeatureEntry->Value;
244
245 // For each feature that this implies, set it.
246 SetImpliedBits(Bits, FeatureEntry, FeatureTable, FeatureTableSize);
247 }
248 } else {
249 errs() << "'" << Feature
250 << "' is not a recognized feature for this target"
251 << " (ignoring feature)\n";
252 }
253
254 return Bits;
255 }
256
257
226258 /// getFeatureBits - Get feature bits a CPU.
227259 ///
228260 uint64_t SubtargetFeatures::getFeatureBits(const StringRef CPU,
4040 class ARMOperand;
4141
4242 class ARMAsmParser : public TargetAsmParser {
43 MCSubtargetInfo &STI;
4344 MCAsmParser &Parser;
44 /// STI, ARM_STI, Thumb_STI - Subtarget info for ARM and Thumb modes. STI
45 /// points to either ARM_STI or Thumb_STI depending on the mode.
46 const MCSubtargetInfo *STI;
47 OwningPtr ARM_STI;
48 OwningPtr Thumb_STI;
4945
5046 MCAsmParser &getParser() const { return Parser; }
5147 MCAsmLexer &getLexer() const { return Parser.getLexer(); }
9086
9187 bool isThumb() const {
9288 // FIXME: Can tablegen auto-generate this?
93 return (STI->getFeatureBits() & ARM::ModeThumb) != 0;
89 return (STI.getFeatureBits() & ARM::ModeThumb) != 0;
9490 }
9591 bool isThumbOne() const {
96 return isThumb() && (STI->getFeatureBits() & ARM::FeatureThumb2) == 0;
92 return isThumb() && (STI.getFeatureBits() & ARM::FeatureThumb2) == 0;
9793 }
9894 void SwitchMode() {
99 STI = isThumb() ? ARM_STI.get() : Thumb_STI.get();
100 setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
95 unsigned FB = ComputeAvailableFeatures(STI.ToggleFeature(ARM::ModeThumb));
96 setAvailableFeatures(FB);
10197 }
10298
10399 /// @name Auto-generated Match Functions
134130 const SmallVectorImpl &);
135131
136132 public:
137 ARMAsmParser(StringRef TT, StringRef CPU, StringRef FS, MCAsmParser &_Parser)
138 : TargetAsmParser(), Parser(_Parser) {
133 ARMAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
134 : TargetAsmParser(), STI(_STI), Parser(_Parser) {
139135 MCAsmParserExtension::Initialize(_Parser);
140136
141 STI = ARM_MC::createARMMCSubtargetInfo(TT, CPU, FS);
142 // FIXME: Design a better way to create two subtargets with only difference
143 // being a feature change.
144 if (isThumb()) {
145 Thumb_STI.reset(STI);
146 assert(TT.startswith("thumb") && "Unexpected Triple string for Thumb!");
147 Twine ARM_TT = "arm" + TT.substr(5);
148 ARM_STI.reset(ARM_MC::createARMMCSubtargetInfo(ARM_TT.str(), CPU, FS));
149 } else {
150 ARM_STI.reset(STI);
151 assert(TT.startswith("arm") && "Unexpected Triple string for ARM!");
152 Twine Thumb_TT = "thumb" + TT.substr(3);
153 Thumb_STI.reset(ARM_MC::createARMMCSubtargetInfo(Thumb_TT.str(),CPU, FS));
154 }
155
156137 // Initialize the set of available features.
157 setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
138 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
158139 }
159140
160141 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
22362217 Parser.Lex();
22372218
22382219 if (Val == 16) {
2239 if (!isThumb()) SwitchMode();
2220 if (!isThumb())
2221 SwitchMode();
22402222 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
22412223 } else {
2242 if (isThumb()) SwitchMode();
2224 if (isThumb())
2225 SwitchMode();
22432226 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
22442227 }
22452228
111111
112112 // Force static initialization.
113113 extern "C" void LLVMInitializeARMMCInstrInfo() {
114 RegisterMCInstrInfo X(TheARMTarget);
115 RegisterMCInstrInfo Y(TheThumbTarget);
116
117114 TargetRegistry::RegisterMCInstrInfo(TheARMTarget, createARMMCInstrInfo);
118115 TargetRegistry::RegisterMCInstrInfo(TheThumbTarget, createARMMCInstrInfo);
119116 }
120117
121118 extern "C" void LLVMInitializeARMMCRegInfo() {
122 RegisterMCRegInfo X(TheARMTarget);
123 RegisterMCRegInfo Y(TheThumbTarget);
124
125119 TargetRegistry::RegisterMCRegInfo(TheARMTarget, createARMMCRegisterInfo);
126120 TargetRegistry::RegisterMCRegInfo(TheThumbTarget, createARMMCRegisterInfo);
127121 }
122
123 extern "C" void LLVMInitializeARMMCSubtargetInfo() {
124 TargetRegistry::RegisterMCSubtargetInfo(TheARMTarget,
125 ARM_MC::createARMMCSubtargetInfo);
126 TargetRegistry::RegisterMCSubtargetInfo(TheThumbTarget,
127 ARM_MC::createARMMCSubtargetInfo);
128 }
1212
1313 #include "AlphaSubtarget.h"
1414 #include "Alpha.h"
15 #include "llvm/Target/TargetRegistry.h"
1516
1617 #define GET_SUBTARGETINFO_ENUM
1718 #define GET_SUBTARGETINFO_MC_DESC
3435 // Initialize scheduling itinerary for the specified CPU.
3536 InstrItins = getInstrItineraryForCPU(CPUName);
3637 }
38
39 MCSubtargetInfo *createAlphaMCSubtargetInfo(StringRef TT, StringRef CPU,
40 StringRef FS) {
41 MCSubtargetInfo *X = new MCSubtargetInfo();
42 InitAlphaMCSubtargetInfo(X, CPU, FS);
43 return X;
44 }
45
46 extern "C" void LLVMInitializeAlphaMCSubtargetInfo() {
47 TargetRegistry::RegisterMCSubtargetInfo(TheAlphaTarget,
48 createAlphaMCSubtargetInfo);
49 }
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "BlackfinSubtarget.h"
14 #include "Blackfin.h"
15 #include "llvm/Target/TargetRegistry.h"
1416
1517 #define GET_SUBTARGETINFO_ENUM
1618 #define GET_SUBTARGETINFO_MC_DESC
4143 // Parse features string.
4244 ParseSubtargetFeatures(CPUName, FS);
4345 }
46
47 MCSubtargetInfo *createBlackfinMCSubtargetInfo(StringRef TT, StringRef CPU,
48 StringRef FS) {
49 MCSubtargetInfo *X = new MCSubtargetInfo();
50 InitBlackfinMCSubtargetInfo(X, CPU, FS);
51 return X;
52 }
53
54 extern "C" void LLVMInitializeBlackfinMCSubtargetInfo() {
55 TargetRegistry::RegisterMCSubtargetInfo(TheBlackfinTarget,
56 createBlackfinMCSubtargetInfo);
57 }
3636 #include "llvm/Transforms/Scalar.h"
3737 #include "llvm/MC/MCAsmInfo.h"
3838 #include "llvm/MC/MCContext.h"
39 #include "llvm/MC/MCSubtargetInfo.h"
3940 #include "llvm/MC/MCSymbol.h"
4041 #include "llvm/Target/TargetData.h"
4142 #include "llvm/Target/TargetRegistry.h"
5859 extern "C" void LLVMInitializeCBackendTarget() {
5960 // Register the target.
6061 RegisterTargetMachine X(TheCBackendTarget);
62 }
63
64 extern "C" void LLVMInitializeCBackendMCSubtargetInfo() {
65 RegisterMCSubtargetInfo X(TheCBackendTarget);
6166 }
6267
6368 namespace {
5353 ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/Disassemblers.def.in
5454 ${LLVM_BINARY_DIR}/include/llvm/Config/Disassemblers.def
5555 )
56
57 # Produce llvm/Config/MCSubtargetInfos.def
58 configure_file(
59 ${LLVM_MAIN_INCLUDE_DIR}/llvm/Config/MCSubtargetInfos.def.in
60 ${LLVM_BINARY_DIR}/include/llvm/Config/MCSubtargtInfos.def
61 )
1313 #include "SPUSubtarget.h"
1414 #include "SPU.h"
1515 #include "SPURegisterInfo.h"
16 #include "llvm/Target/TargetRegistry.h"
1617 #include "llvm/ADT/SmallVector.h"
1718
1819 #define GET_SUBTARGETINFO_ENUM
6465 CriticalPathRCs.push_back(&SPU::VECREGRegClass);
6566 return OptLevel >= CodeGenOpt::Default;
6667 }
68
69 MCSubtargetInfo *createSPUMCSubtargetInfo(StringRef TT, StringRef CPU,
70 StringRef FS) {
71 MCSubtargetInfo *X = new MCSubtargetInfo();
72 InitSPUMCSubtargetInfo(X, CPU, FS);
73 return X;
74 }
75
76 extern "C" void LLVMInitializeCellSPUMCSubtargetInfo() {
77 TargetRegistry::RegisterMCSubtargetInfo(TheCellSPUTarget,
78 createSPUMCSubtargetInfo);
79 }
2222 #include "llvm/Pass.h"
2323 #include "llvm/PassManager.h"
2424 #include "llvm/TypeSymbolTable.h"
25 #include "llvm/MC/MCSubtargetInfo.h"
2526 #include "llvm/ADT/SmallPtrSet.h"
2627 #include "llvm/Support/CommandLine.h"
2728 #include "llvm/Support/ErrorHandling.h"
7273 extern "C" void LLVMInitializeCppBackendTarget() {
7374 // Register the target.
7475 RegisterTargetMachine X(TheCppBackendTarget);
76 }
77
78 extern "C" void LLVMInitializeCppBackendMCSubtargetInfo() {
79 RegisterMCSubtargetInfo X(TheCppBackendTarget);
7580 }
7681
7782 namespace {
6262
6363
6464 public:
65 MBlazeAsmParser(StringRef TT, StringRef CPU, StringRef FS,
66 MCAsmParser &_Parser)
65 MBlazeAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
6766 : TargetAsmParser(), Parser(_Parser) {}
6867
6968 virtual bool ParseInstruction(StringRef Name, SMLoc NameLoc,
1414 #include "MBlaze.h"
1515 #include "MBlazeRegisterInfo.h"
1616 #include "llvm/Support/CommandLine.h"
17 #include "llvm/Target/TargetRegistry.h"
1718
1819 #define GET_SUBTARGETINFO_ENUM
1920 #define GET_SUBTARGETINFO_MC_DESC
6162 CriticalPathRCs.push_back(&MBlaze::GPRRegClass);
6263 return HasItin && OptLevel >= CodeGenOpt::Default;
6364 }
65
66 MCSubtargetInfo *createMBlazeMCSubtargetInfo(StringRef TT, StringRef CPU,
67 StringRef FS) {
68 MCSubtargetInfo *X = new MCSubtargetInfo();
69 InitMBlazeMCSubtargetInfo(X, CPU, FS);
70 return X;
71 }
72
73 extern "C" void LLVMInitializeMBlazeMCSubtargetInfo() {
74 TargetRegistry::RegisterMCSubtargetInfo(TheMBlazeTarget,
75 createMBlazeMCSubtargetInfo);
76 }
1212
1313 #include "MSP430Subtarget.h"
1414 #include "MSP430.h"
15 #include "llvm/Target/TargetRegistry.h"
1516
1617 #define GET_SUBTARGETINFO_ENUM
1718 #define GET_SUBTARGETINFO_MC_DESC
3031 // Parse features string.
3132 ParseSubtargetFeatures(CPUName, FS);
3233 }
34
35 MCSubtargetInfo *createMSP430MCSubtargetInfo(StringRef TT, StringRef CPU,
36 StringRef FS) {
37 MCSubtargetInfo *X = new MCSubtargetInfo();
38 InitMSP430MCSubtargetInfo(X, CPU, FS);
39 return X;
40 }
41
42 extern "C" void LLVMInitializeMSP430MCSubtargetInfo() {
43 TargetRegistry::RegisterMCSubtargetInfo(TheMSP430Target,
44 createMSP430MCSubtargetInfo);
45 }
1212
1313 #include "MipsSubtarget.h"
1414 #include "Mips.h"
15 #include "llvm/Target/TargetRegistry.h"
1516
1617 #define GET_SUBTARGETINFO_ENUM
1718 #define GET_SUBTARGETINFO_MC_DESC
6061 HasCondMov = true;
6162 }
6263 }
64
65 MCSubtargetInfo *createMipsMCSubtargetInfo(StringRef TT, StringRef CPU,
66 StringRef FS) {
67 MCSubtargetInfo *X = new MCSubtargetInfo();
68 InitMipsMCSubtargetInfo(X, CPU, FS);
69 return X;
70 }
71
72 extern "C" void LLVMInitializeMipsMCSubtargetInfo() {
73 TargetRegistry::RegisterMCSubtargetInfo(TheMipsTarget,
74 createMipsMCSubtargetInfo);
75 }
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "PTXSubtarget.h"
14 #include "PTX.h"
1415 #include "llvm/Support/ErrorHandling.h"
16 #include "llvm/Target/TargetRegistry.h"
1517
1618 #define GET_SUBTARGETINFO_ENUM
1719 #define GET_SUBTARGETINFO_MC_DESC
6365 case PTX_VERSION_2_3: return "2.3";
6466 }
6567 }
68
69
70 MCSubtargetInfo *createPTXMCSubtargetInfo(StringRef TT, StringRef CPU,
71 StringRef FS) {
72 MCSubtargetInfo *X = new MCSubtargetInfo();
73 InitPTXMCSubtargetInfo(X, CPU, FS);
74 return X;
75 }
76
77 extern "C" void LLVMInitializePTXMCSubtargetInfo() {
78 TargetRegistry::RegisterMCSubtargetInfo(ThePTX32Target,
79 createPTXMCSubtargetInfo);
80 TargetRegistry::RegisterMCSubtargetInfo(ThePTX64Target,
81 createPTXMCSubtargetInfo);
82 }
1414 #include "PPC.h"
1515 #include "llvm/GlobalValue.h"
1616 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetRegistry.h"
1718 #include
1819
1920 #define GET_SUBTARGETINFO_ENUM
139140 return GV->hasWeakLinkage() || GV->hasLinkOnceLinkage() ||
140141 GV->hasCommonLinkage() || isDecl;
141142 }
143
144 MCSubtargetInfo *createPPCMCSubtargetInfo(StringRef TT, StringRef CPU,
145 StringRef FS) {
146 MCSubtargetInfo *X = new MCSubtargetInfo();
147 InitPPCMCSubtargetInfo(X, CPU, FS);
148 return X;
149 }
150
151 extern "C" void LLVMInitializePowerPCMCSubtargetInfo() {
152 TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
153 createPPCMCSubtargetInfo);
154 TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
155 createPPCMCSubtargetInfo);
156 }
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "SparcSubtarget.h"
14 #include "Sparc.h"
15 #include "llvm/Target/TargetRegistry.h"
1416
1517 #define GET_SUBTARGETINFO_ENUM
1618 #define GET_SUBTARGETINFO_MC_DESC
4143 // Parse features string.
4244 ParseSubtargetFeatures(CPUName, FS);
4345 }
46
47 MCSubtargetInfo *createSparcMCSubtargetInfo(StringRef TT, StringRef CPU,
48 StringRef FS) {
49 MCSubtargetInfo *X = new MCSubtargetInfo();
50 InitSparcMCSubtargetInfo(X, CPU, FS);
51 return X;
52 }
53
54 extern "C" void LLVMInitializeSparcMCSubtargetInfo() {
55 TargetRegistry::RegisterMCSubtargetInfo(TheSparcTarget,
56 createSparcMCSubtargetInfo);
57 }
1414 #include "SystemZ.h"
1515 #include "llvm/GlobalValue.h"
1616 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetRegistry.h"
1718
1819 #define GET_SUBTARGETINFO_ENUM
1920 #define GET_SUBTARGETINFO_MC_DESC
5253
5354 return false;
5455 }
56
57 MCSubtargetInfo *createSystemZMCSubtargetInfo(StringRef TT, StringRef CPU,
58 StringRef FS) {
59 MCSubtargetInfo *X = new MCSubtargetInfo();
60 InitSystemZMCSubtargetInfo(X, CPU, FS);
61 return X;
62 }
63
64 extern "C" void LLVMInitializeSystemZMCSubtargetInfo() {
65 TargetRegistry::RegisterMCSubtargetInfo(TheSystemZTarget,
66 createSystemZMCSubtargetInfo);
67 }
3636 struct X86Operand;
3737
3838 class X86ATTAsmParser : public TargetAsmParser {
39 MCSubtargetInfo &STI;
3940 MCAsmParser &Parser;
40 OwningPtr STI;
4141
4242 private:
4343 MCAsmParser &getParser() const { return Parser; }
6565
6666 bool is64Bit() {
6767 // FIXME: Can tablegen auto-generate this?
68 return (STI->getFeatureBits() & X86::Mode64Bit) != 0;
68 return (STI.getFeatureBits() & X86::Mode64Bit) != 0;
6969 }
7070
7171 /// @name Auto-generated Matcher Functions
7777 /// }
7878
7979 public:
80 X86ATTAsmParser(StringRef TT, StringRef CPU, StringRef FS,
81 MCAsmParser &parser)
82 : TargetAsmParser(), Parser(parser),
83 STI(X86_MC::createX86MCSubtargetInfo(TT, CPU, FS)) {
80 X86ATTAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser)
81 : TargetAsmParser(), STI(sti), Parser(parser) {
8482
8583 // Initialize the set of available features.
86 setAvailableFeatures(ComputeAvailableFeatures(STI->getFeatureBits()));
84 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
8785 }
8886 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
8987
144144
145145 // Force static initialization.
146146 extern "C" void LLVMInitializeX86MCInstrInfo() {
147 RegisterMCInstrInfo X(TheX86_32Target);
148 RegisterMCInstrInfo Y(TheX86_64Target);
149
150147 TargetRegistry::RegisterMCInstrInfo(TheX86_32Target, createX86MCInstrInfo);
151148 TargetRegistry::RegisterMCInstrInfo(TheX86_64Target, createX86MCInstrInfo);
152149 }
153150
154151 extern "C" void LLVMInitializeX86MCRegInfo() {
155 RegisterMCRegInfo X(TheX86_32Target);
156 RegisterMCRegInfo Y(TheX86_64Target);
157
158152 TargetRegistry::RegisterMCRegInfo(TheX86_32Target, createX86MCRegisterInfo);
159153 TargetRegistry::RegisterMCRegInfo(TheX86_64Target, createX86MCRegisterInfo);
160154 }
155
156
157 extern "C" void LLVMInitializeX86MCSubtargetInfo() {
158 TargetRegistry::RegisterMCSubtargetInfo(TheX86_32Target,
159 X86_MC::createX86MCSubtargetInfo);
160 TargetRegistry::RegisterMCSubtargetInfo(TheX86_64Target,
161 X86_MC::createX86MCSubtargetInfo);
162 }
1212
1313 #include "XCoreSubtarget.h"
1414 #include "XCore.h"
15 #include "llvm/Target/TargetRegistry.h"
1516
1617 #define GET_SUBTARGETINFO_ENUM
1718 #define GET_SUBTARGETINFO_MC_DESC
2627 : XCoreGenSubtargetInfo(TT, CPU, FS)
2728 {
2829 }
30
31
32 MCSubtargetInfo *createXCoreMCSubtargetInfo(StringRef TT, StringRef CPU,
33 StringRef FS) {
34 MCSubtargetInfo *X = new MCSubtargetInfo();
35 InitXCoreMCSubtargetInfo(X, CPU, FS);
36 return X;
37 }
38
39 extern "C" void LLVMInitializeXCoreMCSubtargetInfo() {
40 TargetRegistry::RegisterMCSubtargetInfo(TheXCoreTarget,
41 createXCoreMCSubtargetInfo);
42 }
200200
201201 // Initialize targets first, so that --version shows registered targets.
202202 InitializeAllTargets();
203 InitializeAllMCSubtargetInfos();
203204 InitializeAllAsmPrinters();
204205 InitializeAllAsmParsers();
205206
1818 #include "llvm/MC/MCInstPrinter.h"
1919 #include "llvm/MC/MCSectionMachO.h"
2020 #include "llvm/MC/MCStreamer.h"
21 #include "llvm/MC/MCSubtargetInfo.h"
2122 #include "llvm/MC/SubtargetFeature.h"
2223 #include "llvm/Target/TargetAsmBackend.h"
2324 #include "llvm/Target/TargetAsmParser.h"
339340 TM->getTargetLowering()->getObjFileLowering();
340341 const_cast(TLOF).Initialize(Ctx, *TM);
341342
343 OwningPtr
344 STI(TheTarget->createMCSubtargetInfo(TripleName, MCPU, FeaturesStr));
345
342346 // FIXME: There is a bit of code duplication with addPassesToEmitFile.
343347 if (FileType == OFT_AssemblyFile) {
344348 MCInstPrinter *IP =
370374
371375 OwningPtr Parser(createMCAsmParser(*TheTarget, SrcMgr, Ctx,
372376 *Str.get(), *MAI));
373 OwningPtr
374 TAP(TheTarget->createAsmParser(TripleName, MCPU, FeaturesStr, *Parser));
377 OwningPtr TAP(TheTarget->createAsmParser(*STI, *Parser));
375378 if (!TAP) {
376379 errs() << ProgName
377380 << ": error: this target does not support assembly parsing.\n";
447450 llvm::InitializeAllTargetInfos();
448451 // FIXME: We shouldn't need to initialize the Target(Machine)s.
449452 llvm::InitializeAllTargets();
453 llvm::InitializeAllMCSubtargetInfos();
450454 llvm::InitializeAllAsmPrinters();
451455 llvm::InitializeAllAsmParsers();
452456 llvm::InitializeAllDisassemblers();
3434 #include "llvm/MC/MCInst.h"
3535 #include "llvm/MC/MCParser/MCAsmParser.h"
3636 #include "llvm/MC/MCStreamer.h"
37 #include "llvm/MC/MCSubtargetInfo.h"
3738 #include "llvm/MC/MCSymbol.h"
3839 #include "llvm/MC/SubtargetFeature.h"
3940 #include "llvm/Target/TargetAsmParser.h"
617618 OwningPtr Parser(createMCAsmParser(_target->getTarget(), SrcMgr,
618619 Context, *Streamer,
619620 *_target->getMCAsmInfo()));
621 OwningPtr STI(_target->getTarget().
622 createMCSubtargetInfo(_target->getTargetTriple(),
623 _target->getTargetCPU(),
624 _target->getTargetFeatureString()));
620625 OwningPtr
621 TAP(_target->getTarget().createAsmParser(_target->getTargetTriple(),
622 _target->getTargetCPU(),
623 _target->getTargetFeatureString(),
624 *Parser.get()));
626 TAP(_target->getTarget().createAsmParser(*STI, *Parser.get()));
625627 Parser->setTargetParser(*TAP);
626628 int Res = Parser->Run(false);
627629 if (Res)