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No more noResults. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@40132 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
14 changed file(s) with 49 addition(s) and 58 deletion(s). Raw diff Collapse all Expand all
653653 "ldm${p}${addr:submode} $addr, $dst1",
654654 []>;
655655
656 let isCall = 1, noResults = 1,
656 let isCall = 1,
657657 Defs = [R0, R1, R2, R3, R12, LR,
658658 D0, D1, D2, D3, D4, D5, D6, D7, CPSR] in {
659659 def BL : AXI<(outs), (ins i32imm:$func, variable_ops),
676676 }
677677 }
678678
679 let isBranch = 1, isTerminator = 1, noResults = 1 in {
679 let isBranch = 1, isTerminator = 1 in {
680680 // B is "predicable" since it can be xformed into a Bcc.
681681 let isBarrier = 1 in {
682682 let isPredicable = 1 in
189189 def tPOP_RET : TI<(outs reglist:$dst1, variable_ops), (ins),
190190 "pop $dst1", []>;
191191
192 let isCall = 1, noResults = 1,
192 let isCall = 1,
193193 Defs = [R0, R1, R2, R3, LR,
194194 D0, D1, D2, D3, D4, D5, D6, D7] in {
195195 def tBL : TIx2<(outs), (ins i32imm:$func, variable_ops),
208208 [(ARMcall_nolink GPR:$func)]>;
209209 }
210210
211 let isBranch = 1, isTerminator = 1, noResults = 1 in {
211 let isBranch = 1, isTerminator = 1 in {
212212 let isBarrier = 1 in {
213213 let isPredicable = 1 in
214214 def tB : TI<(outs), (ins brtarget:$target), "b $target",
226226
227227 // FIXME: should be able to write a pattern for ARMBrcond, but can't use
228228 // a two-value operand where a dag node expects two operands. :(
229 let isBranch = 1, isTerminator = 1, noResults = 1 in
229 let isBranch = 1, isTerminator = 1 in
230230 def tBcc : TI<(outs), (ins brtarget:$target, pred:$cc), "b$cc $target",
231231 [/*(ARMbrcond bb:$target, imm:$cc)*/]>;
232232
9696 //3.3.2
9797 def target : Operand {}
9898
99 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
99 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
100100 class BFormN opcode, dag OL, string asmstr, InstrItinClass itin>
101101 : InstAlpha {
102102 let OutOperandList = (ops);
368368 def : Pat<(setune GPRC:$X, immUExt8:$Y), (CMPEQi (CMPEQ GPRC:$X, immUExt8:$Y), 0)>;
369369
370370
371 let isReturn = 1, isTerminator = 1, noResults = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in {
371 let isReturn = 1, isTerminator = 1, Ra = 31, Rb = 26, disp = 1, Uses = [R26] in {
372372 def RETDAG : MbrForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", s_jsr>; //Return from subroutine
373373 def RETDAGp : MbrpForm< 0x1A, 0x02, (ops), "ret $$31,($$26),1", [(retflag)], s_jsr>; //Return from subroutine
374374 }
375375
376 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1,
376 let isBranch = 1, isTerminator = 1, isBarrier = 1,
377377 Ra = 31, disp = 0 in
378378 def JMP : MbrpForm< 0x1A, 0x00, (ops GPRC:$RS), "jmp $$31,($RS),0",
379379 [(brind GPRC:$RS)], s_jsr>; //Jump
380380
381 let isCall = 1, noResults = 1, Ra = 26,
381 let isCall = 1, Ra = 26,
382382 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
383383 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
384384 F0, F1,
386386 F20, F21, F22, F23, F24, F25, F26, F27, F28, F29, F30], Uses = [R29] in {
387387 def BSR : BFormD<0x34, "bsr $$26,$$$DISP..ng", [], s_jsr>; //Branch to subroutine
388388 }
389 let isCall = 1, noResults = 1, Ra = 26, Rb = 27, disp = 0,
389 let isCall = 1, Ra = 26, Rb = 27, disp = 0,
390390 Defs = [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19,
391391 R20, R21, R22, R23, R24, R25, R26, R27, R28, R29,
392392 F0, F1,
395395 def JSR : MbrForm< 0x1A, 0x01, (ops ), "jsr $$26,($$27),0", s_jsr>; //Jump to subroutine
396396 }
397397
398 let isCall = 1, noResults = 1, Ra = 23, Rb = 27, disp = 0,
398 let isCall = 1, Ra = 23, Rb = 27, disp = 0,
399399 Defs = [R23, R24, R25, R27, R28], Uses = [R24, R25, R27] in
400400 def JSRs : MbrForm< 0x1A, 0x01, (ops ), "jsr $$23,($$27),0", s_jsr>; //Jump to div or rem
401401
785785 : BFormN
786786 !strconcat(asmstr, " $R,$dst"), s_fbr>;
787787
788 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, noResults = 1 in {
788 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1 in {
789789 let Ra = 31 in
790790 def BR : BFormD<0x30, "br $$31,$DISP", [(br bb:$DISP)], s_ubr>;
791791
538538 def SUBIMM8 : AForm<0x03, 0x0b, (outs GR:$dst), (ins s8imm:$imm, GR:$src2),
539539 "sub $dst = $imm, $src2">, isA;
540540
541 let isStore = 1, noResults = 1 in {
541 let isStore = 1 in {
542542 def ST1 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
543543 "st1 [$dstPtr] = $value">, isM;
544544 def ST2 : AForm<0x03, 0x0b, (outs), (ins GR:$dstPtr, GR:$value),
686686 (GETFSIG (FCVTFXUTRUNC FP:$src))>;
687687
688688
689 let isTerminator = 1, isBranch = 1, noResults = 1 in {
689 let isTerminator = 1, isBranch = 1 in {
690690 def BRL_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins i64imm:$dst),
691691 "(p0) brl.cond.sptk $dst">, isB;
692692 def BRLCOND_NOTCALL : RawForm<0x03, 0xb0, (outs), (ins PR:$qp, i64imm:$dst),
695695 "($qp) br.cond.sptk $dst">, isB;
696696 }
697697
698 let isCall = 1, noResults = 1, /* isTerminator = 1, isBranch = 1, */
698 let isCall = 1, /* isTerminator = 1, isBranch = 1, */
699699 Uses = [out0,out1,out2,out3,out4,out5,out6,out7],
700700 // all calls clobber non-callee-saved registers, and for now, they are these:
701701 Defs = [r2,r3,r8,r9,r10,r11,r14,r15,r16,r17,r18,r19,r20,r21,r22,r23,r24,
732732 }
733733
734734 // Return branch:
735 let isTerminator = 1, isReturn = 1, noResults = 1 in
735 let isTerminator = 1, isReturn = 1 in
736736 def RET : AForm_DAG<0x03, 0x0b, (outs), (ins),
737737 "br.ret.sptk.many rp",
738738 [(retflag)]>, isB; // return
207207 [(OpNode CPURegs:$dst, addr:$addr)]>;
208208
209209 // Conditional Branch
210 let isBranch = 1, noResults=1, isTerminator=1 in
210 let isBranch = 1, isTerminator=1 in
211211 class CBranch op, string instr_asm, PatFrag cond_op>:
212212 FI< op,
213213 (outs),
233233 [(set CPURegs:$dst, (cond_op CPURegs:$b, imm_type:$c))]>;
234234
235235 // Unconditional branch
236 let hasCtrlDep=1, noResults=1, isTerminator=1 in
236 let hasCtrlDep=1, isTerminator=1 in
237237 class JumpFJ op, string instr_asm>:
238238 FJ< op,
239239 (outs),
241241 !strconcat(instr_asm, " $target"),
242242 [(br bb:$target)]>;
243243
244 let hasCtrlDep=1, noResults=1, isTerminator=1, rd=0 in
244 let hasCtrlDep=1, isTerminator=1, rd=0 in
245245 class JumpFR op, bits<6> func, string instr_asm>:
246246 FR< op,
247247 func,
406406
407407 // Ret instruction - as mips does not have "ret" a
408408 // jr $ra must be generated.
409 let isReturn=1, isTerminator=1, hasDelaySlot=1, noResults=1,
409 let isReturn=1, isTerminator=1, hasDelaySlot=1,
410410 isBarrier=1, hasCtrlDep=1, rs=0, rt=0, shamt=0 in
411411 {
412412 def RET : FR <0x00, 0x02, (outs), (ins CPURegs:$target),
6969 PPC970_Unit_BRU;
7070
7171 // Macho ABI Calls.
72 let isCall = 1, noResults = 1, PPC970_Unit = 7,
72 let isCall = 1, PPC970_Unit = 7,
7373 // All calls clobber the PPC64 non-callee saved registers.
7474 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
7575 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
8888
8989 // ELF 64 ABI Calls = Macho ABI Calls
9090 // Used to define BL8_ELF and BLA8_ELF
91 let isCall = 1, noResults = 1, PPC970_Unit = 7,
91 let isCall = 1, PPC970_Unit = 7,
9292 // All calls clobber the PPC64 non-callee saved registers.
9393 Defs = [X0,X2,X3,X4,X5,X6,X7,X8,X9,X10,X11,X12,
9494 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
437437
438438 }
439439
440 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
440 let isStore = 1, PPC970_Unit = 2 in {
441441 // Truncating stores.
442442 def STB8 : DForm_1<38, (outs), (ins G8RC:$rS, memri:$src),
443443 "stb $rS, $src", LdStGeneral,
504504
505505 }
506506
507 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
507 let isStore = 1, PPC970_Unit = 2 in {
508508
509509 def STDUX : XForm_8<31, 181, (outs), (ins G8RC:$rS, memrr:$dst),
510510 "stdux $rS, $dst", LdStSTD,
159159 def IMPLICIT_DEF_VRRC : Pseudo<(outs VRRC:$rD), (ins),"; IMPLICIT_DEF_VRRC $rD",
160160 [(set VRRC:$rD, (v4i32 (undef)))]>;
161161
162 let noResults = 1 in {
163162 def DSS : DSS_Form<822, (outs), (ins u5imm:$A, u5imm:$STRM,u5imm:$ZERO1,u5imm:$ZERO2),
164163 "dss $STRM, $A", LdStGeneral /*FIXME*/, []>;
165164 def DST : DSS_Form<342, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
166165 "dst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
167166 def DSTST : DSS_Form<374, (outs), (ins u5imm:$T, u5imm:$STRM, GPRC:$rA, GPRC:$rB),
168167 "dstst $rA, $rB, $STRM, $T", LdStGeneral /*FIXME*/, []>;
169 }
170168
171169 def MFVSCR : VXForm_4<1540, (outs VRRC:$vD), (ins),
172170 "mfvcr $vD", LdStGeneral,
202200 [(set VRRC:$vD, (int_ppc_altivec_lvsr xoaddr:$src))]>,
203201 PPC970_Unit_LSU;
204202
205 let isStore = 1, noResults = 1, PPC970_Unit = 2 in { // Stores.
203 let isStore = 1, PPC970_Unit = 2 in { // Stores.
206204 def STVEBX: XForm_8<31, 135, (outs), (ins VRRC:$rS, memrr:$dst),
207205 "stvebx $rS, $dst", LdStGeneral,
208206 [(int_ppc_altivec_stvebx VRRC:$rS, xoaddr:$dst)]>;
344344 []>;
345345 }
346346
347 let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
347 let isTerminator = 1, isBarrier = 1, PPC970_Unit = 7 in {
348348 let isReturn = 1 in
349349 def BLR : XLForm_2_br<19, 16, 0, (outs), (ins pred:$p),
350350 "b${p:cc}lr ${p:reg}", BrB,
358358 def MovePCtoLR : Pseudo<(outs), (ins piclabel:$label), "bl $label", []>,
359359 PPC970_Unit_BRU;
360360
361 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
362 noResults = 1, PPC970_Unit = 7 in {
361 let isBranch = 1, isTerminator = 1, hasCtrlDep = 1, PPC970_Unit = 7 in {
363362 let isBarrier = 1 in {
364363 def B : IForm<18, 0, 0, (outs), (ins target:$dst),
365364 "b $dst", BrB,
375374 }
376375
377376 // Macho ABI Calls.
378 let isCall = 1, noResults = 1, PPC970_Unit = 7,
377 let isCall = 1, PPC970_Unit = 7,
379378 // All calls clobber the non-callee saved registers...
380379 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
381380 F0,F1,F2,F3,F4,F5,F6,F7,F8,F9,F10,F11,F12,F13,
396395 }
397396
398397 // ELF ABI Calls.
399 let isCall = 1, noResults = 1, PPC970_Unit = 7,
398 let isCall = 1, PPC970_Unit = 7,
400399 // All calls clobber the non-callee saved registers...
401400 Defs = [R0,R2,R3,R4,R5,R6,R7,R8,R9,R10,R11,R12,
402401 F0,F1,F2,F3,F4,F5,F6,F7,F8,
541540 //
542541
543542 // Unindexed (r+i) Stores.
544 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
543 let isStore = 1, PPC970_Unit = 2 in {
545544 def STB : DForm_1<38, (outs), (ins GPRC:$rS, memri:$src),
546545 "stb $rS, $src", LdStGeneral,
547546 [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
598597
599598 // Indexed (r+r) Stores.
600599 //
601 let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
600 let isStore = 1, PPC970_Unit = 2 in {
602601 def STBX : XForm_8<31, 215, (outs), (ins GPRC:$rS, memrr:$dst),
603602 "stbx $rS, $dst", LdStGeneral,
604603 [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
266266
267267 // Section A.3 - Synthetic Instructions, p. 85
268268 // special cases of JMPL:
269 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
269 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
270270 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
271271 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>;
272272 }
463463 let isBranch = 1;
464464 let isTerminator = 1;
465465 let hasDelaySlot = 1;
466 let noResults = 1;
467466 }
468467
469468 let isBarrier = 1 in
485484 let isBranch = 1;
486485 let isTerminator = 1;
487486 let hasDelaySlot = 1;
488 let noResults = 1;
489487 }
490488
491489 // FIXME: the encoding for the JIT should look at the condition field.
497495 // Section B.24 - Call and Link Instruction, p. 125
498496 // This is the only Format 1 instruction
499497 let Uses = [O0, O1, O2, O3, O4, O5],
500 hasDelaySlot = 1, isCall = 1, noResults = 1,
498 hasDelaySlot = 1, isCall = 1,
501499 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
502500 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
503501 def CALL : InstSP<(outs), (ins calltarget:$dst),
191191 bit hasDelaySlot = 0; // Does this instruction have an delay slot?
192192 bit usesCustomDAGSchedInserter = 0; // Pseudo instr needing special help.
193193 bit hasCtrlDep = 0; // Does this instruction r/w ctrl-flow chains?
194 bit noResults = 0; // Does this instruction produce no results?
195194 bit isNotDuplicable = 0; // Is it unsafe to duplicate this instruction?
196195
197196 InstrItinClass Itinerary = NoItinerary;// Execution steps used for scheduling.
136136 def FpGETRESULT64 : FpI_<(outs RFP64:$dst), (ins), SpecialFP,
137137 [(set RFP64:$dst, X86fpget)]>; // FPR = ST(0)
138138
139 let noResults = 1 in {
140 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
141 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
142
143 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
144 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
145 }
139 def FpSETRESULT32 : FpI_<(outs), (ins RFP32:$src), SpecialFP,
140 [(X86fpset RFP32:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
141
142 def FpSETRESULT64 : FpI_<(outs), (ins RFP64:$src), SpecialFP,
143 [(X86fpset RFP64:$src)]>, Imp<[], [ST0]>;// ST(0) = FPR
144
146145 // FpI - Floating Point Psuedo Instruction template. Predicated on FPStack.
147146 class FpI pattern> :
148147 FpI_, Requires<[FPStack]>;
402402
403403 // Return instructions.
404404 let isTerminator = 1, isReturn = 1, isBarrier = 1,
405 hasCtrlDep = 1, noResults = 1 in {
405 hasCtrlDep = 1 in {
406406 def RET : I<0xC3, RawFrm, (outs), (ins), "ret", [(X86retflag 0)]>;
407407 def RETI : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt), "ret $amt",
408408 [(X86retflag imm:$amt)]>;
409409 }
410410
411411 // All branches are RawFrm, Void, Branch, and Terminators
412 let isBranch = 1, isTerminator = 1, noResults = 1 in
412 let isBranch = 1, isTerminator = 1 in
413413 class IBr opcode, dag ins, string asm, list pattern> :
414414 I;
415415
417417 let isBranch = 1, isBarrier = 1 in
418418 def JMP : IBr<0xE9, (ins brtarget:$dst), "jmp $dst", [(br bb:$dst)]>;
419419
420 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
420 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
421421 def JMP32r : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp{l} {*}$dst",
422422 [(brind GR32:$dst)]>;
423423 def JMP32m : I<0xFF, MRM4m, (outs), (ins i32mem:$dst), "jmp{l} {*}$dst",
463463 //===----------------------------------------------------------------------===//
464464 // Call Instructions...
465465 //
466 let isCall = 1, noResults = 1 in
466 let isCall = 1 in
467467 // All calls clobber the non-callee saved registers...
468468 let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
469469 MM0, MM1, MM2, MM3, MM4, MM5, MM6, MM7,
477477 }
478478
479479 // Tail call stuff.
480 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
480 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
481481 def TAILJMPd : IBr<0xE9, (ins i32imm:$dst), "jmp ${dst:call} # TAIL CALL",
482482 []>;
483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
483 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
484484 def TAILJMPr : I<0xFF, MRM4r, (outs), (ins GR32:$dst), "jmp {*}$dst # TAIL CALL",
485485 []>;
486 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, noResults = 1 in
486 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in
487487 def TAILJMPm : I<0xFF, MRM4m, (outs), (ins i32mem:$dst),
488488 "jmp {*}$dst # TAIL CALL", []>;
489489
25052505 // EH Pseudo Instructions
25062506 //
25072507 let isTerminator = 1, isReturn = 1, isBarrier = 1,
2508 hasCtrlDep = 1, noResults = 1 in {
2508 hasCtrlDep = 1 in {
25092509 def EH_RETURN : I<0xC3, RawFrm, (outs), (ins GR32:$addr),
25102510 "ret #eh_return, addr: $addr",
25112511 [(X86ehret GR32:$addr)]>;
116116 //===----------------------------------------------------------------------===//
117117 // Call Instructions...
118118 //
119 let isCall = 1, noResults = 1 in
119 let isCall = 1 in
120120 // All calls clobber the non-callee saved registers...
121121 let Defs = [RAX, RCX, RDX, RSI, RDI, R8, R9, R10, R11,
122122 FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0,
132132 }
133133
134134 // Branches
135 let isBranch = 1, isTerminator = 1, noResults = 1, isBarrier = 1 in {
135 let isBranch = 1, isTerminator = 1, isBarrier = 1 in {
136136 def JMP64r : I<0xFF, MRM4r, (outs), (ins GR64:$dst), "jmp{q} {*}$dst",
137137 [(brind GR64:$dst)]>;
138138 def JMP64m : I<0xFF, MRM4m, (outs), (ins i64mem:$dst), "jmp{q} {*}$dst",
596596
597597 // Temporary hack: there is no patterns associated with these instructions
598598 // so we have to tell tblgen that these do not produce results.
599 let noResults = 1 in {
600599 def SHLD64mrCL : RI<0xA5, MRMDestMem, (outs), (ins i64mem:$dst, GR64:$src2),
601600 "shld{q} {%cl, $src2, $dst|$dst, $src2, %CL}", []>,
602601 Imp<[CL],[]>, TB;
611610 (outs), (ins i64mem:$dst, GR64:$src2, i8imm:$src3),
612611 "shrd{q} {$src3, $src2, $dst|$dst, $src2, $src3}", []>,
613612 TB;
614 } // noResults
615613
616614 //===----------------------------------------------------------------------===//
617615 // Logical Instructions...