llvm.org GIT mirror llvm / ff7ef15
[X86] Support folding to andnps with SSE1 only. With SSE1 only, we emit FAND and FXOR nodes for v4f32. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@318968 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 2 years ago
2 changed file(s) with 6 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
3503235032
3503335033 // Vector types are handled in combineANDXORWithAllOnesIntoANDNP().
3503435034 if (!((VT == MVT::f32 && Subtarget.hasSSE1()) ||
35035 (VT == MVT::f64 && Subtarget.hasSSE2())))
35035 (VT == MVT::f64 && Subtarget.hasSSE2()) ||
35036 (VT == MVT::v4f32 && Subtarget.hasSSE1() && !Subtarget.hasSSE2())))
3503635037 return SDValue();
3503735038
3503835039 auto isAllOnesConstantFP = [](SDValue V) {
35040 if (V.getSimpleValueType().isVector())
35041 return ISD::isBuildVectorAllOnes(V.getNode());
3503935042 auto *C = dyn_cast(V);
3504035043 return C && C->getConstantFPValue()->isAllOnesValue();
3504135044 };
5454 define <4 x float> @test_mm_andnot_ps(<4 x float> %a0, <4 x float> %a1) nounwind {
5555 ; X32-LABEL: test_mm_andnot_ps:
5656 ; X32: # BB#0:
57 ; X32-NEXT: xorps {{\.LCPI.*}}, %xmm0
58 ; X32-NEXT: andps %xmm1, %xmm0
57 ; X32-NEXT: andnps %xmm1, %xmm0
5958 ; X32-NEXT: retl
6059 ;
6160 ; X64-LABEL: test_mm_andnot_ps:
6261 ; X64: # BB#0:
63 ; X64-NEXT: xorps {{.*}}(%rip), %xmm0
64 ; X64-NEXT: andps %xmm1, %xmm0
62 ; X64-NEXT: andnps %xmm1, %xmm0
6563 ; X64-NEXT: retq
6664 %arg0 = bitcast <4 x float> %a0 to <4 x i32>
6765 %arg1 = bitcast <4 x float> %a1 to <4 x i32>