llvm.org GIT mirror llvm / ff6222e
TBAA: remove !tbaa from testing cases if not used. This will make it easier to turn on struct-path aware TBAA since the metadata format will change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@180745 91177308-0d34-0410-b5e6-96231b3b80d8 Manman Ren 6 years ago
11 changed file(s) with 32 addition(s) and 69 deletion(s). Raw diff Collapse all Expand all
1414
1515 for.body: ; preds = %for.cond
1616 %v.5 = select i1 undef, i32 undef, i32 0
17 %0 = load i8* undef, align 1, !tbaa !0
17 %0 = load i8* undef, align 1
1818 %conv88 = zext i8 %0 to i32
1919 %sub89 = sub nsw i32 0, %conv88
2020 %v.8 = select i1 undef, i32 undef, i32 %sub89
21 %1 = load i8* null, align 1, !tbaa !0
21 %1 = load i8* null, align 1
2222 %conv108 = zext i8 %1 to i32
23 %2 = load i8* undef, align 1, !tbaa !0
23 %2 = load i8* undef, align 1
2424 %conv110 = zext i8 %2 to i32
2525 %sub111 = sub nsw i32 %conv108, %conv110
2626 %cmp112 = icmp slt i32 %sub111, 0
4343 %s.10 = phi i32 [ %add172, %for.body ], [ 0, %for.cond ]
4444 ret i32 %s.10
4545 }
46
47 !0 = metadata !{metadata !"omnipotent char", metadata !1}
48 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}
1717 br i1 %tmp, label %bb4, label %bb67
1818
1919 bb4: ; preds = %bb3
20 %tmp5 = load <4 x i32>* undef, align 16, !tbaa !0
20 %tmp5 = load <4 x i32>* undef, align 16
2121 %tmp6 = and <4 x i32> %tmp5,
2222 %tmp7 = or <4 x i32> %tmp6,
2323 %tmp8 = bitcast <4 x i32> %tmp7 to <4 x float>
4040 %tmp24 = trunc i128 %tmp23 to i64
4141 %tmp25 = insertvalue [2 x i64] undef, i64 %tmp24, 0
4242 %tmp26 = insertvalue [2 x i64] %tmp25, i64 0, 1
43 %tmp27 = load float* undef, align 4, !tbaa !2
43 %tmp27 = load float* undef, align 4
4444 %tmp28 = insertelement <4 x float> undef, float %tmp27, i32 3
45 %tmp29 = load <4 x i32>* undef, align 16, !tbaa !0
45 %tmp29 = load <4 x i32>* undef, align 16
4646 %tmp30 = and <4 x i32> %tmp29,
4747 %tmp31 = or <4 x i32> %tmp30,
4848 %tmp32 = bitcast <4 x i32> %tmp31 to <4 x float>
5151 %tmp35 = fmul <4 x float> %tmp34, undef
5252 %tmp36 = fmul <4 x float> %tmp35, undef
5353 %tmp37 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
54 %tmp38 = load float* undef, align 4, !tbaa !2
54 %tmp38 = load float* undef, align 4
5555 %tmp39 = insertelement <2 x float> undef, float %tmp38, i32 0
5656 %tmp40 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
57 %tmp41 = load float* undef, align 4, !tbaa !2
57 %tmp41 = load float* undef, align 4
5858 %tmp42 = insertelement <4 x float> undef, float %tmp41, i32 3
5959 %tmp43 = shufflevector <2 x float> %tmp39, <2 x float> undef, <4 x i32> zeroinitializer
6060 %tmp44 = fmul <4 x float> %tmp33, %tmp43
6363 %tmp47 = fmul <4 x float> %tmp46, %tmp36
6464 %tmp48 = fadd <4 x float> undef, %tmp47
6565 %tmp49 = call arm_aapcs_vfpcc i8* undef(i8* undef) nounwind
66 %tmp50 = load float* undef, align 4, !tbaa !2
66 %tmp50 = load float* undef, align 4
6767 %tmp51 = insertelement <4 x float> undef, float %tmp50, i32 3
6868 %tmp52 = call arm_aapcs_vfpcc float* null(i8* undef) nounwind
69 %tmp54 = load float* %tmp52, align 4, !tbaa !2
69 %tmp54 = load float* %tmp52, align 4
7070 %tmp55 = insertelement <4 x float> undef, float %tmp54, i32 3
7171 %tmp56 = fsub <4 x float> , %tmp22
7272 %tmp57 = call <4 x float> @llvm.arm.neon.vmins.v4f32(<4 x float> %tmp56, <4 x float> %tmp55) nounwind
9898 declare <4 x float> @llvm.arm.neon.vrecps.v4f32(<4 x float>, <4 x float>) nounwind readnone
9999
100100 declare <4 x float> @llvm.arm.neon.vrecpe.v4f32(<4 x float>) nounwind readnone
101
102 !0 = metadata !{metadata !"omnipotent char", metadata !1}
103 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}
104 !2 = metadata !{metadata !"float", metadata !0}
66 ; This test case is exercising REG_SEQUENCE, and chains of REG_SEQUENCE.
77 define arm_aapcs_vfpcc void @foo(i8* nocapture %arg, i8* %arg1) nounwind align 2 {
88 bb:
9 %tmp = load <2 x float>* undef, align 8, !tbaa !0
9 %tmp = load <2 x float>* undef, align 8
1010 %tmp2 = extractelement <2 x float> %tmp, i32 0
1111 %tmp3 = insertelement <4 x float> undef, float %tmp2, i32 0
1212 %tmp4 = insertelement <4 x float> %tmp3, float 0.000000e+00, i32 1
6969 declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
7070 declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
7171 declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounwind
72
73 !0 = metadata !{metadata !"omnipotent char", metadata !1}
74 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}
5555 %tmp39 = shufflevector <2 x i64> %tmp38, <2 x i64> undef, <1 x i32> zeroinitializer
5656 %tmp40 = bitcast <1 x i64> %tmp39 to <2 x float>
5757 %tmp41 = shufflevector <2 x float> %tmp40, <2 x float> undef, <4 x i32>
58 %tmp42 = load <4 x float>* null, align 16, !tbaa !0
58 %tmp42 = load <4 x float>* null, align 16
5959 %tmp43 = fmul <4 x float> %tmp42, %tmp41
60 %tmp44 = load <4 x float>* undef, align 16, !tbaa !0
60 %tmp44 = load <4 x float>* undef, align 16
6161 %tmp45 = fadd <4 x float> undef, %tmp43
6262 %tmp46 = fadd <4 x float> undef, %tmp45
6363 %tmp47 = bitcast <4 x float> %tmp36 to <2 x i64>
107107 %tmp89 = fmul <4 x float> undef, %tmp88
108108 %tmp90 = fadd <4 x float> %tmp89, undef
109109 %tmp91 = fadd <4 x float> undef, %tmp90
110 store <4 x float> %tmp91, <4 x float>* undef, align 16, !tbaa !0
110 store <4 x float> %tmp91, <4 x float>* undef, align 16
111111 unreachable
112112
113113 bb92: ; preds = %bb2
115115 }
116116
117117 declare arm_aapcs_vfpcc void @bar(i8* noalias nocapture sret, [8 x i64]) nounwind uwtable inlinehint
118
119 !0 = metadata !{metadata !"omnipotent char", metadata !1}
120 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}
88 ;
99 %2 = shufflevector <1 x i64> zeroinitializer, <1 x i64> undef, <2 x i32>
1010 %3 = bitcast <2 x i64> %2 to <4 x float>
11 store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0
12 store <4 x float> zeroinitializer, <4 x float>* undef, align 16, !tbaa !0
13 store <4 x float> %3, <4 x float>* undef, align 16, !tbaa !0
11 store <4 x float> zeroinitializer, <4 x float>* undef, align 16
12 store <4 x float> zeroinitializer, <4 x float>* undef, align 16
13 store <4 x float> %3, <4 x float>* undef, align 16
1414 %4 = insertelement <4 x float> %3, float 8.000000e+00, i32 2
15 store <4 x float> %4, <4 x float>* undef, align 16, !tbaa !0
15 store <4 x float> %4, <4 x float>* undef, align 16
1616 unreachable
1717
1818 ;
1919 ret void
2020 }
21
22 !0 = metadata !{metadata !"omnipotent char", metadata !1}
23 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}
1919 %tmp15 = shufflevector <2 x float> %tmp14, <2 x float> undef, <4 x i32> zeroinitializer
2020 %tmp16 = fmul <4 x float> zeroinitializer, %tmp15
2121 %tmp17 = fadd <4 x float> %tmp16, %arg
22 store <4 x float> %tmp17, <4 x float>* undef, align 8, !tbaa !0
22 store <4 x float> %tmp17, <4 x float>* undef, align 8
2323 br label %bb18
2424
2525 bb18: ; preds = %bb5, %bb4
2626 ret void
2727 }
28
29 !0 = metadata !{metadata !"omnipotent char", metadata !1}
30 !1 = metadata !{metadata !"Simple C/C++ TBAA", null}
2525 ; CHECK: Successors:
2626 define i32 @f1(i32* nocapture %p1, i32* nocapture %p2) nounwind {
2727 entry:
28 store volatile i32 65540, i32* %p1, align 4, !tbaa !0
29 %0 = load volatile i32* %p2, align 4, !tbaa !0
28 store volatile i32 65540, i32* %p1, align 4
29 %0 = load volatile i32* %p2, align 4
3030 ret i32 %0
3131 }
3232
3333 define i32 @f2(i32* nocapture %p1, i32* nocapture %p2) nounwind {
3434 entry:
35 store i32 65540, i32* %p1, align 4, !tbaa !0
36 %0 = load i32* %p2, align 4, !tbaa !0
35 store i32 65540, i32* %p1, align 4
36 %0 = load i32* %p2, align 4
3737 ret i32 %0
3838 }
39
40 !0 = metadata !{metadata !"int", metadata !1}
41 !1 = metadata !{metadata !"omnipotent char", metadata !2}
42 !2 = metadata !{metadata !"Simple C/C++ TBAA"}
128128 %45 = fmul <4 x float> undef, undef
129129 %46 = fmul <4 x float> %45, %43
130130 %47 = fmul <4 x float> undef, %44
131 %48 = load <4 x float>* undef, align 8, !tbaa !1
131 %48 = load <4 x float>* undef, align 8
132132 %49 = bitcast <4 x float> %48 to <2 x i64>
133133 %50 = shufflevector <2 x i64> %49, <2 x i64> undef, <1 x i32>
134134 %51 = bitcast <1 x i64> %50 to <2 x float>
144144 %61 = fmul <4 x float> %59, %60
145145 %62 = fmul <4 x float> %61,
146146 %63 = fadd <4 x float> %47, %62
147 store <4 x float> %46, <4 x float>* undef, align 8, !tbaa !1
147 store <4 x float> %46, <4 x float>* undef, align 8
148148 call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
149149 call arm_aapcs_vfpcc void @bar(%0* undef, float 0.000000e+00) nounwind
150 store <4 x float> %63, <4 x float>* undef, align 8, !tbaa !1
150 store <4 x float> %63, <4 x float>* undef, align 8
151151 unreachable
152152
153153 ;
169169 declare arm_aapcs_vfpcc void @bar(%0*, float)
170170
171171 !0 = metadata !{metadata !"branch_weights", i32 64, i32 4}
172 !1 = metadata !{metadata !"omnipotent char", metadata !2}
173 !2 = metadata !{metadata !"Simple C/C++ TBAA"}
55 ;CHECK: foo:
66 define i32 @foo(i32* %a) nounwind optsize {
77 entry:
8 %0 = load i32* %a, align 4, !tbaa !0
8 %0 = load i32* %a, align 4
99 %arrayidx1 = getelementptr inbounds i32* %a, i32 1
10 %1 = load i32* %arrayidx1, align 4, !tbaa !0
10 %1 = load i32* %arrayidx1, align 4
1111 %arrayidx2 = getelementptr inbounds i32* %a, i32 2
12 %2 = load i32* %arrayidx2, align 4, !tbaa !0
12 %2 = load i32* %arrayidx2, align 4
1313 %add.ptr = getelementptr inbounds i32* %a, i32 3
1414 ;Make sure we do not have a duplicated register in the front of the reg list
1515 ;EXPECTED: ldm [[BASE:r[0-9]+]]!, {[[REG:r[0-9]+]], {{r[0-9]+}},
2121 }
2222
2323 declare void @bar(i32*) optsize
24
25 !0 = metadata !{metadata !"int", metadata !1}
26 !1 = metadata !{metadata !"omnipotent char", metadata !2}
27 !2 = metadata !{metadata !"Simple C/C++ TBAA"}
3131 %BestCost.011 = phi i32 [ -1, %entry ], [ %BestCost.1, %if.end8 ]
3232 %BestIdx.010 = phi i32 [ 0, %entry ], [ %BestIdx.1, %if.end8 ]
3333 %arrayidx = getelementptr inbounds i32* %a, i32 %i.012
34 %0 = load i32* %arrayidx, align 4, !tbaa !0
34 %0 = load i32* %arrayidx, align 4
3535 %mul = mul i32 %0, %0
3636 %sub = add nsw i32 %i.012, -5
3737 %cmp2 = icmp eq i32 %sub, %Pref
5252 if.end8: ; preds = %if.else, %if.then
5353 %BestIdx.1 = phi i32 [ %i.0.BestIdx.0, %if.then ], [ %BestIdx.0.i.0, %if.else ]
5454 %BestCost.1 = phi i32 [ %mul.BestCost.0, %if.then ], [ %BestCost.0.mul, %if.else ]
55 store i32 %mul, i32* %arrayidx, align 4, !tbaa !0
55 store i32 %mul, i32* %arrayidx, align 4
5656 %inc = add i32 %i.012, 1
5757 %cmp = icmp eq i32 %inc, 11
5858 br i1 %cmp, label %for.end, label %for.body
6060 for.end: ; preds = %if.end8
6161 ret i32 %BestIdx.1
6262 }
63
64 !0 = metadata !{metadata !"int", metadata !1}
65 !1 = metadata !{metadata !"omnipotent char", metadata !2}
66 !2 = metadata !{metadata !"Simple C/C++ TBAA", null}
1818 entry:
1919 %exception.i = tail call i8* @__cxa_allocate_exception(i32 4) nounwind
2020 %0 = bitcast i8* %exception.i to i32*
21 store i32 42, i32* %0, align 4, !tbaa !0
21 store i32 42, i32* %0, align 4
2222 invoke void @__cxa_throw(i8* %exception.i, i8* bitcast (i8** @_ZTIi to i8*), i8* null) noreturn
2323 to label %unreachable.i unwind label %lpad.i
2424
7070 declare i8* @__cxa_begin_catch(i8*)
7171
7272 declare void @__cxa_end_catch()
73
74 !0 = metadata !{metadata !"int", metadata !1}
75 !1 = metadata !{metadata !"omnipotent char", metadata !2}
76 !2 = metadata !{metadata !"Simple C/C++ TBAA"}