llvm.org GIT mirror llvm / ff528b6
[MCTargetAsmParser] Move the member varialbes that reference MCSubtargetInfo in the subclasses into MCTargetAsmParser and define a member function getSTI. This is done in preparation for making changes to shrink the size of MCRelaxableFragment. (see http://reviews.llvm.org/D14346). git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@253124 91177308-0d34-0410-b5e6-96231b3b80d8 Akira Hatanaka 4 years ago
12 changed file(s) with 147 addition(s) and 119 deletion(s). Raw diff Collapse all Expand all
1919 class MCInst;
2020 class MCParsedAsmOperand;
2121 class MCStreamer;
22 class MCSubtargetInfo;
2223 class SMLoc;
2324 class StringRef;
2425 template class SmallVectorImpl;
9192 MCTargetAsmParser(const MCTargetAsmParser &) = delete;
9293 void operator=(const MCTargetAsmParser &) = delete;
9394 protected: // Can only create subclasses.
94 MCTargetAsmParser(MCTargetOptions const &);
95 MCTargetAsmParser(MCTargetOptions const &, MCSubtargetInfo &STI);
9596
9697 /// AvailableFeatures - The current set of available features.
9798 uint64_t AvailableFeatures;
106107 /// Set of options which affects instrumentation of inline assembly.
107108 MCTargetOptions MCOptions;
108109
110 /// Current STI.
111 MCSubtargetInfo &STI;
112
109113 public:
110114 ~MCTargetAsmParser() override;
115
116 const MCSubtargetInfo &getSTI() const;
111117
112118 uint64_t getAvailableFeatures() const { return AvailableFeatures; }
113119 void setAvailableFeatures(uint64_t Value) { AvailableFeatures = Value; }
66 //
77 //===----------------------------------------------------------------------===//
88
9 #include "llvm/MC/MCContext.h"
910 #include "llvm/MC/MCTargetAsmParser.h"
1011 using namespace llvm;
1112
12 MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions)
13 : AvailableFeatures(0), ParsingInlineAsm(false), MCOptions(MCOptions)
13 MCTargetAsmParser::MCTargetAsmParser(MCTargetOptions const &MCOptions,
14 MCSubtargetInfo &STI)
15 : AvailableFeatures(0), ParsingInlineAsm(false), MCOptions(MCOptions),
16 STI(STI)
1417 {
1518 }
1619
1720 MCTargetAsmParser::~MCTargetAsmParser() {
1821 }
22
23 const MCSubtargetInfo &MCTargetAsmParser::getSTI() const {
24 return STI;
25 }
4242 class AArch64AsmParser : public MCTargetAsmParser {
4343 private:
4444 StringRef Mnemonic; ///< Instruction mnemonic.
45 MCSubtargetInfo &STI;
4645
4746 // Map of register aliases registers via the .req directive.
4847 StringMap > RegisterReqs;
116115 };
117116 AArch64AsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
118117 const MCInstrInfo &MII, const MCTargetOptions &Options)
119 : MCTargetAsmParser(Options), STI(STI) {
118 : MCTargetAsmParser(Options, STI) {
120119 MCAsmParserExtension::Initialize(Parser);
121120 MCStreamer &S = getParser().getStreamer();
122121 if (S.getTargetStreamer() == nullptr)
123122 new AArch64TargetStreamer(S);
124123
125124 // Initialize the set of available features.
126 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
125 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
127126 }
128127
129128 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
20422041 bool Valid;
20432042 auto Mapper = AArch64PRFM::PRFMMapper();
20442043 StringRef Name =
2045 Mapper.toString(MCE->getValue(), STI.getFeatureBits(), Valid);
2044 Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid);
20462045 Operands.push_back(AArch64Operand::CreatePrefetch(prfop, Name,
20472046 S, getContext()));
20482047 return MatchOperand_Success;
20562055 bool Valid;
20572056 auto Mapper = AArch64PRFM::PRFMMapper();
20582057 unsigned prfop =
2059 Mapper.fromString(Tok.getString(), STI.getFeatureBits(), Valid);
2058 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
20602059 if (!Valid) {
20612060 TokError("pre-fetch hint expected");
20622061 return MatchOperand_ParseFail;
26702669 bool Valid;
26712670 auto Mapper = AArch64DB::DBarrierMapper();
26722671 StringRef Name =
2673 Mapper.toString(MCE->getValue(), STI.getFeatureBits(), Valid);
2672 Mapper.toString(MCE->getValue(), getSTI().getFeatureBits(), Valid);
26742673 Operands.push_back( AArch64Operand::CreateBarrier(MCE->getValue(), Name,
26752674 ExprLoc, getContext()));
26762675 return MatchOperand_Success;
26842683 bool Valid;
26852684 auto Mapper = AArch64DB::DBarrierMapper();
26862685 unsigned Opt =
2687 Mapper.fromString(Tok.getString(), STI.getFeatureBits(), Valid);
2686 Mapper.fromString(Tok.getString(), getSTI().getFeatureBits(), Valid);
26882687 if (!Valid) {
26892688 TokError("invalid barrier option name");
26902689 return MatchOperand_ParseFail;
27132712
27142713 bool IsKnown;
27152714 auto MRSMapper = AArch64SysReg::MRSMapper();
2716 uint32_t MRSReg = MRSMapper.fromString(Tok.getString(), STI.getFeatureBits(),
2717 IsKnown);
2715 uint32_t MRSReg = MRSMapper.fromString(Tok.getString(),
2716 getSTI().getFeatureBits(), IsKnown);
27182717 assert(IsKnown == (MRSReg != -1U) &&
27192718 "register should be -1 if and only if it's unknown");
27202719
27212720 auto MSRMapper = AArch64SysReg::MSRMapper();
2722 uint32_t MSRReg = MSRMapper.fromString(Tok.getString(), STI.getFeatureBits(),
2723 IsKnown);
2721 uint32_t MSRReg = MSRMapper.fromString(Tok.getString(),
2722 getSTI().getFeatureBits(), IsKnown);
27242723 assert(IsKnown == (MSRReg != -1U) &&
27252724 "register should be -1 if and only if it's unknown");
27262725
27272726 auto PStateMapper = AArch64PState::PStateMapper();
27282727 uint32_t PStateField =
2729 PStateMapper.fromString(Tok.getString(), STI.getFeatureBits(), IsKnown);
2728 PStateMapper.fromString(Tok.getString(),
2729 getSTI().getFeatureBits(), IsKnown);
27302730 assert(IsKnown == (PStateField != -1U) &&
27312731 "register should be -1 if and only if it's unknown");
27322732
39893989 return true;
39903990
39913991 Inst.setLoc(IDLoc);
3992 Out.EmitInstruction(Inst, STI);
3992 Out.EmitInstruction(Inst, getSTI());
39933993 return false;
39943994 }
39953995 case Match_MissingFeature: {
42024202 Inst.setOpcode(AArch64::TLSDESCCALL);
42034203 Inst.addOperand(MCOperand::createExpr(Expr));
42044204
4205 getParser().getStreamer().EmitInstruction(Inst, STI);
4205 getParser().getStreamer().EmitInstruction(Inst, getSTI());
42064206 return false;
42074207 }
42084208
326326 };
327327
328328 class AMDGPUAsmParser : public MCTargetAsmParser {
329 MCSubtargetInfo &STI;
330329 const MCInstrInfo &MII;
331330 MCAsmParser &Parser;
332331
333332 unsigned ForcedEncodingSize;
334333
335334 bool isVI() const {
336 return STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
335 return getSTI().getFeatureBits()[AMDGPU::FeatureVolcanicIslands];
337336 }
338337
339338 bool hasSGPR102_SGPR103() const {
367366 AMDGPUAsmParser(MCSubtargetInfo &STI, MCAsmParser &_Parser,
368367 const MCInstrInfo &MII,
369368 const MCTargetOptions &Options)
370 : MCTargetAsmParser(Options), STI(STI), MII(MII), Parser(_Parser),
369 : MCTargetAsmParser(Options, STI), MII(MII), Parser(_Parser),
371370 ForcedEncodingSize(0) {
372
373 if (STI.getFeatureBits().none()) {
371 if (getSTI().getFeatureBits().none()) {
374372 // Set default features.
375373 STI.ToggleFeature("SOUTHERN_ISLANDS");
376374 }
377375
378 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
376 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
379377 }
380378
381379 AMDGPUTargetStreamer &getTargetStreamer() {
602600 default: break;
603601 case Match_Success:
604602 Inst.setLoc(IDLoc);
605 Out.EmitInstruction(Inst, STI);
603 Out.EmitInstruction(Inst, getSTI());
606604 return false;
607605 case Match_MissingFeature:
608606 return Error(IDLoc, "instruction not supported on this GPU");
696694 // If this directive has no arguments, then use the ISA version for the
697695 // targeted GPU.
698696 if (getLexer().is(AsmToken::EndOfStatement)) {
699 AMDGPU::IsaVersion Isa = AMDGPU::getIsaVersion(STI.getFeatureBits());
697 AMDGPU::IsaVersion Isa = AMDGPU::getIsaVersion(getSTI().getFeatureBits());
700698 getTargetStreamer().EmitDirectiveHSACodeObjectISA(Isa.Major, Isa.Minor,
701699 Isa.Stepping,
702700 "AMD", "AMDGPU");
908906 bool AMDGPUAsmParser::ParseDirectiveAMDKernelCodeT() {
909907
910908 amd_kernel_code_t Header;
911 AMDGPU::initDefaultAMDKernelCodeT(Header, STI.getFeatureBits());
909 AMDGPU::initDefaultAMDKernelCodeT(Header, getSTI().getFeatureBits());
912910
913911 while (true) {
914912
128128 };
129129
130130 class ARMAsmParser : public MCTargetAsmParser {
131 MCSubtargetInfo &STI;
132131 const MCInstrInfo &MII;
133132 const MCRegisterInfo *MRI;
134133 UnwindContext UC;
246245 OperandVector &Operands);
247246 bool isThumb() const {
248247 // FIXME: Can tablegen auto-generate this?
249 return STI.getFeatureBits()[ARM::ModeThumb];
248 return getSTI().getFeatureBits()[ARM::ModeThumb];
250249 }
251250 bool isThumbOne() const {
252 return isThumb() && !STI.getFeatureBits()[ARM::FeatureThumb2];
251 return isThumb() && !getSTI().getFeatureBits()[ARM::FeatureThumb2];
253252 }
254253 bool isThumbTwo() const {
255 return isThumb() && STI.getFeatureBits()[ARM::FeatureThumb2];
254 return isThumb() && getSTI().getFeatureBits()[ARM::FeatureThumb2];
256255 }
257256 bool hasThumb() const {
258 return STI.getFeatureBits()[ARM::HasV4TOps];
257 return getSTI().getFeatureBits()[ARM::HasV4TOps];
259258 }
260259 bool hasV6Ops() const {
261 return STI.getFeatureBits()[ARM::HasV6Ops];
260 return getSTI().getFeatureBits()[ARM::HasV6Ops];
262261 }
263262 bool hasV6MOps() const {
264 return STI.getFeatureBits()[ARM::HasV6MOps];
263 return getSTI().getFeatureBits()[ARM::HasV6MOps];
265264 }
266265 bool hasV7Ops() const {
267 return STI.getFeatureBits()[ARM::HasV7Ops];
266 return getSTI().getFeatureBits()[ARM::HasV7Ops];
268267 }
269268 bool hasV8Ops() const {
270 return STI.getFeatureBits()[ARM::HasV8Ops];
269 return getSTI().getFeatureBits()[ARM::HasV8Ops];
271270 }
272271 bool hasARM() const {
273 return !STI.getFeatureBits()[ARM::FeatureNoARM];
272 return !getSTI().getFeatureBits()[ARM::FeatureNoARM];
274273 }
275274 bool hasDSP() const {
276 return STI.getFeatureBits()[ARM::FeatureDSP];
275 return getSTI().getFeatureBits()[ARM::FeatureDSP];
277276 }
278277 bool hasD16() const {
279 return STI.getFeatureBits()[ARM::FeatureD16];
278 return getSTI().getFeatureBits()[ARM::FeatureD16];
280279 }
281280 bool hasV8_1aOps() const {
282 return STI.getFeatureBits()[ARM::HasV8_1aOps];
281 return getSTI().getFeatureBits()[ARM::HasV8_1aOps];
283282 }
284283
285284 void SwitchMode() {
287286 setAvailableFeatures(FB);
288287 }
289288 bool isMClass() const {
290 return STI.getFeatureBits()[ARM::FeatureMClass];
289 return getSTI().getFeatureBits()[ARM::FeatureMClass];
291290 }
292291
293292 /// @name Auto-generated Match Functions
350349
351350 ARMAsmParser(MCSubtargetInfo &STI, MCAsmParser &Parser,
352351 const MCInstrInfo &MII, const MCTargetOptions &Options)
353 : MCTargetAsmParser(Options), STI(STI), MII(MII), UC(Parser) {
352 : MCTargetAsmParser(Options, STI), MII(MII), UC(Parser) {
354353 MCAsmParserExtension::Initialize(Parser);
355354
356355 // Cache the MCRegisterInfo.
86108609 return false;
86118610
86128611 Inst.setLoc(IDLoc);
8613 Out.EmitInstruction(Inst, STI);
8612 Out.EmitInstruction(Inst, getSTI());
86148613 return false;
86158614 case Match_MissingFeature: {
86168615 assert(ErrorInfo && "Unknown missing feature!");
91659164
91669165 // FIXME: This is using table-gen data, but should be moved to
91679166 // ARMTargetParser once that is table-gen'd.
9168 if (!STI.isCPUStringValid(CPU)) {
9167 if (!getSTI().isCPUStringValid(CPU)) {
91699168 Error(L, "Unknown CPU name");
91709169 return false;
91719170 }
7575 return static_cast(TS);
7676 }
7777
78 MCSubtargetInfo &STI;
7978 MCAsmParser &Parser;
8079 MCAssembler *Assembler;
8180 MCInstrInfo const &MCII;
135134 public:
136135 HexagonAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
137136 const MCInstrInfo &MII, const MCTargetOptions &Options)
138 : MCTargetAsmParser(Options), STI(_STI), Parser(_Parser),
137 : MCTargetAsmParser(Options, _STI), Parser(_Parser),
139138 MCII (MII), MCB(HexagonMCInstrInfo::createBundle()), InBrackets(false) {
140 setAvailableFeatures(
141 ComputeAvailableFeatures(_STI.getFeatureBits()));
139 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
142140
143141 MCAsmParserExtension::Initialize(_Parser);
144142
626624
627625 // Check the bundle for errors.
628626 const MCRegisterInfo *RI = getContext().getRegisterInfo();
629 HexagonMCChecker Check(MCII, STI, MCB, MCB, *RI);
630
631 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, STI, getContext(),
632 MCB, &Check);
627 HexagonMCChecker Check(MCII, getSTI(), MCB, MCB, *RI);
628
629 bool CheckOk = HexagonMCInstrInfo::canonicalizePacket(MCII, getSTI(),
630 getContext(), MCB,
631 &Check);
633632
634633 while (Check.getNextErrInfo() == true) {
635634 unsigned Reg = Check.getErrRegister();
714713 // Empty packets are valid yet aren't emitted
715714 return false;
716715 }
717 Out.EmitInstruction(MCB, STI);
716 Out.EmitInstruction(MCB, getSTI());
718717 } else {
719718 // If compounding and duplexing didn't reduce the size below
720719 // 4 or less we have a packet that is too big.
106106 return static_cast(TS);
107107 }
108108
109 MCSubtargetInfo &STI;
110109 MipsABIInfo ABI;
111110 SmallVector, 2> AssemblerOptions;
112111 MCSymbol *CurrentFn; // Pointer to the function being parsed. It may be a
355354 }
356355
357356 void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
358 if (!(STI.getFeatureBits()[Feature])) {
357 if (!(getSTI().getFeatureBits()[Feature])) {
359358 setAvailableFeatures(
360359 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
361360 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
363362 }
364363
365364 void clearFeatureBits(uint64_t Feature, StringRef FeatureString) {
366 if (STI.getFeatureBits()[Feature]) {
365 if (getSTI().getFeatureBits()[Feature]) {
367366 setAvailableFeatures(
368367 ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
369368 AssemblerOptions.back()->setFeatures(STI.getFeatureBits());
372371
373372 void setModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
374373 setFeatureBits(Feature, FeatureString);
375 AssemblerOptions.front()->setFeatures(STI.getFeatureBits());
374 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
376375 }
377376
378377 void clearModuleFeatureBits(uint64_t Feature, StringRef FeatureString) {
379378 clearFeatureBits(Feature, FeatureString);
380 AssemblerOptions.front()->setFeatures(STI.getFeatureBits());
379 AssemblerOptions.front()->setFeatures(getSTI().getFeatureBits());
381380 }
382381
383382 public:
390389
391390 MipsAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
392391 const MCInstrInfo &MII, const MCTargetOptions &Options)
393 : MCTargetAsmParser(Options), STI(sti),
392 : MCTargetAsmParser(Options, sti),
394393 ABI(MipsABIInfo::computeTargetABI(Triple(sti.getTargetTriple()),
395394 sti.getCPU(), Options)) {
396395 MCAsmParserExtension::Initialize(parser);
398397 parser.addAliasForDirective(".asciiz", ".asciz");
399398
400399 // Initialize the set of available features.
401 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
400 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
402401
403402 // Remember the initial assembler options. The user can not modify these.
404403 AssemblerOptions.push_back(
405 llvm::make_unique(STI.getFeatureBits()));
404 llvm::make_unique(getSTI().getFeatureBits()));
406405
407406 // Create an assembler options environment for the user to modify.
408407 AssemblerOptions.push_back(
409 llvm::make_unique(STI.getFeatureBits()));
408 llvm::make_unique(getSTI().getFeatureBits()));
410409
411410 getTargetStreamer().updateABIInfo(*this);
412411
432431 /// True if all of $fcc0 - $fcc7 exist for the current ISA.
433432 bool hasEightFccRegisters() const { return hasMips4() || hasMips32(); }
434433
435 bool isGP64bit() const { return STI.getFeatureBits()[Mips::FeatureGP64Bit]; }
436 bool isFP64bit() const { return STI.getFeatureBits()[Mips::FeatureFP64Bit]; }
434 bool isGP64bit() const {
435 return getSTI().getFeatureBits()[Mips::FeatureGP64Bit];
436 }
437 bool isFP64bit() const {
438 return getSTI().getFeatureBits()[Mips::FeatureFP64Bit];
439 }
437440 const MipsABIInfo &getABI() const { return ABI; }
438441 bool isABI_N32() const { return ABI.IsN32(); }
439442 bool isABI_N64() const { return ABI.IsN64(); }
440443 bool isABI_O32() const { return ABI.IsO32(); }
441 bool isABI_FPXX() const { return STI.getFeatureBits()[Mips::FeatureFPXX]; }
444 bool isABI_FPXX() const {
445 return getSTI().getFeatureBits()[Mips::FeatureFPXX];
446 }
442447
443448 bool useOddSPReg() const {
444 return !(STI.getFeatureBits()[Mips::FeatureNoOddSPReg]);
449 return !(getSTI().getFeatureBits()[Mips::FeatureNoOddSPReg]);
445450 }
446451
447452 bool inMicroMipsMode() const {
448 return STI.getFeatureBits()[Mips::FeatureMicroMips];
449 }
450 bool hasMips1() const { return STI.getFeatureBits()[Mips::FeatureMips1]; }
451 bool hasMips2() const { return STI.getFeatureBits()[Mips::FeatureMips2]; }
452 bool hasMips3() const { return STI.getFeatureBits()[Mips::FeatureMips3]; }
453 bool hasMips4() const { return STI.getFeatureBits()[Mips::FeatureMips4]; }
454 bool hasMips5() const { return STI.getFeatureBits()[Mips::FeatureMips5]; }
453 return getSTI().getFeatureBits()[Mips::FeatureMicroMips];
454 }
455 bool hasMips1() const {
456 return getSTI().getFeatureBits()[Mips::FeatureMips1];
457 }
458 bool hasMips2() const {
459 return getSTI().getFeatureBits()[Mips::FeatureMips2];
460 }
461 bool hasMips3() const {
462 return getSTI().getFeatureBits()[Mips::FeatureMips3];
463 }
464 bool hasMips4() const {
465 return getSTI().getFeatureBits()[Mips::FeatureMips4];
466 }
467 bool hasMips5() const {
468 return getSTI().getFeatureBits()[Mips::FeatureMips5];
469 }
455470 bool hasMips32() const {
456 return STI.getFeatureBits()[Mips::FeatureMips32];
471 return getSTI().getFeatureBits()[Mips::FeatureMips32];
457472 }
458473 bool hasMips64() const {
459 return STI.getFeatureBits()[Mips::FeatureMips64];
474 return getSTI().getFeatureBits()[Mips::FeatureMips64];
460475 }
461476 bool hasMips32r2() const {
462 return STI.getFeatureBits()[Mips::FeatureMips32r2];
477 return getSTI().getFeatureBits()[Mips::FeatureMips32r2];
463478 }
464479 bool hasMips64r2() const {
465 return STI.getFeatureBits()[Mips::FeatureMips64r2];
480 return getSTI().getFeatureBits()[Mips::FeatureMips64r2];
466481 }
467482 bool hasMips32r3() const {
468 return (STI.getFeatureBits()[Mips::FeatureMips32r3]);
483 return (getSTI().getFeatureBits()[Mips::FeatureMips32r3]);
469484 }
470485 bool hasMips64r3() const {
471 return (STI.getFeatureBits()[Mips::FeatureMips64r3]);
486 return (getSTI().getFeatureBits()[Mips::FeatureMips64r3]);
472487 }
473488 bool hasMips32r5() const {
474 return (STI.getFeatureBits()[Mips::FeatureMips32r5]);
489 return (getSTI().getFeatureBits()[Mips::FeatureMips32r5]);
475490 }
476491 bool hasMips64r5() const {
477 return (STI.getFeatureBits()[Mips::FeatureMips64r5]);
492 return (getSTI().getFeatureBits()[Mips::FeatureMips64r5]);
478493 }
479494 bool hasMips32r6() const {
480 return STI.getFeatureBits()[Mips::FeatureMips32r6];
495 return getSTI().getFeatureBits()[Mips::FeatureMips32r6];
481496 }
482497 bool hasMips64r6() const {
483 return STI.getFeatureBits()[Mips::FeatureMips64r6];
484 }
485
486 bool hasDSP() const { return STI.getFeatureBits()[Mips::FeatureDSP]; }
487 bool hasDSPR2() const { return STI.getFeatureBits()[Mips::FeatureDSPR2]; }
488 bool hasDSPR3() const { return STI.getFeatureBits()[Mips::FeatureDSPR3]; }
489 bool hasMSA() const { return STI.getFeatureBits()[Mips::FeatureMSA]; }
498 return getSTI().getFeatureBits()[Mips::FeatureMips64r6];
499 }
500
501 bool hasDSP() const {
502 return getSTI().getFeatureBits()[Mips::FeatureDSP];
503 }
504 bool hasDSPR2() const {
505 return getSTI().getFeatureBits()[Mips::FeatureDSPR2];
506 }
507 bool hasDSPR3() const {
508 return getSTI().getFeatureBits()[Mips::FeatureDSPR3];
509 }
510 bool hasMSA() const {
511 return getSTI().getFeatureBits()[Mips::FeatureMSA];
512 }
490513 bool hasCnMips() const {
491 return (STI.getFeatureBits()[Mips::FeatureCnMips]);
514 return (getSTI().getFeatureBits()[Mips::FeatureCnMips]);
492515 }
493516
494517 bool inPicMode() {
496519 }
497520
498521 bool inMips16Mode() const {
499 return STI.getFeatureBits()[Mips::FeatureMips16];
522 return getSTI().getFeatureBits()[Mips::FeatureMips16];
500523 }
501524
502525 bool useTraps() const {
503 return STI.getFeatureBits()[Mips::FeatureUseTCCInDIV];
526 return getSTI().getFeatureBits()[Mips::FeatureUseTCCInDIV];
504527 }
505528
506529 bool useSoftFloat() const {
507 return STI.getFeatureBits()[Mips::FeatureSoftFloat];
530 return getSTI().getFeatureBits()[Mips::FeatureSoftFloat];
508531 }
509532
510533 /// Warn if RegIndex is the same as the current AT.
32883311 if (processInstruction(Inst, IDLoc, Instructions))
32893312 return true;
32903313 for (unsigned i = 0; i < Instructions.size(); i++)
3291 Out.EmitInstruction(Instructions[i], STI);
3314 Out.EmitInstruction(Instructions[i], getSTI());
32923315 return false;
32933316 }
32943317 case Match_MissingFeature:
242242 struct PPCOperand;
243243
244244 class PPCAsmParser : public MCTargetAsmParser {
245 MCSubtargetInfo &STI;
246245 const MCInstrInfo &MII;
247246 bool IsPPC64;
248247 bool IsDarwin;
290289
291290
292291 public:
293 PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
294 const MCTargetOptions &Options)
295 : MCTargetAsmParser(Options), STI(STI), MII(MII) {
292 PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &,
293 const MCInstrInfo &MII, const MCTargetOptions &Options)
294 : MCTargetAsmParser(Options, STI), MII(MII) {
296295 // Check for 64-bit vs. 32-bit pointer mode.
297296 Triple TheTriple(STI.getTargetTriple());
298297 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
11841183 break;
11851184 }
11861185 case PPC::MFTB: {
1187 if (STI.getFeatureBits()[PPC::FeatureMFTB]) {
1186 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
11881187 assert(Inst.getNumOperands() == 2 && "Expecting two operands");
11891188 Inst.setOpcode(PPC::MFSPR);
11901189 }
12041203 // Post-process instructions (typically extended mnemonics)
12051204 ProcessInstruction(Inst, Operands);
12061205 Inst.setLoc(IDLoc);
1207 Out.EmitInstruction(Inst, STI);
1206 Out.EmitInstruction(Inst, getSTI());
12081207 return false;
12091208 case Match_MissingFeature:
12101209 return Error(IDLoc, "instruction use requires an option to be enabled");
16891688 // where th can be omitted when it is 0. dcbtst is the same. We take the
16901689 // server form to be the default, so swap the operands if we're parsing for
16911690 // an embedded core (they'll be swapped again upon printing).
1692 if (STI.getFeatureBits()[PPC::FeatureBookE] &&
1691 if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
16931692 Operands.size() == 4 &&
16941693 (Name == "dcbt" || Name == "dcbtst")) {
16951694 std::swap(Operands[1], Operands[3]);
3434 class SparcOperand;
3535 class SparcAsmParser : public MCTargetAsmParser {
3636
37 MCSubtargetInfo &STI;
3837 MCAsmParser &Parser;
3938
4039 /// @name Auto-generated Match Functions
8180 bool parseDirectiveWord(unsigned Size, SMLoc L);
8281
8382 bool is64Bit() const {
84 return STI.getTargetTriple().getArch() == Triple::sparcv9;
83 return getSTI().getTargetTriple().getArch() == Triple::sparcv9;
8584 }
8685
8786 void expandSET(MCInst &Inst, SMLoc IDLoc,
9190 SparcAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
9291 const MCInstrInfo &MII,
9392 const MCTargetOptions &Options)
94 : MCTargetAsmParser(Options), STI(sti), Parser(parser) {
93 : MCTargetAsmParser(Options, sti), Parser(parser) {
9594 // Initialize the set of available features.
96 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
95 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
9796 }
9897
9998 };
527526 }
528527
529528 for (const MCInst &I : Instructions) {
530 Out.EmitInstruction(I, STI);
529 Out.EmitInstruction(I, getSTI());
531530 }
532531 return false;
533532 }
348348 #include "SystemZGenAsmMatcher.inc"
349349
350350 private:
351 MCSubtargetInfo &STI;
352351 MCAsmParser &Parser;
353352 enum RegisterGroup {
354353 RegGR,
388387 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
389388 const MCInstrInfo &MII,
390389 const MCTargetOptions &Options)
391 : MCTargetAsmParser(Options), STI(sti), Parser(parser) {
390 : MCTargetAsmParser(Options, sti), Parser(parser) {
392391 MCAsmParserExtension::Initialize(Parser);
393392
394393 // Initialize the set of available features.
395 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
394 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
396395 }
397396
398397 // Override MCTargetAsmParser.
792791 switch (MatchResult) {
793792 case Match_Success:
794793 Inst.setLoc(IDLoc);
795 Out.EmitInstruction(Inst, STI);
794 Out.EmitInstruction(Inst, getSTI());
796795 return false;
797796
798797 case Match_MissingFeature: {
5656 };
5757
5858 class X86AsmParser : public MCTargetAsmParser {
59 MCSubtargetInfo &STI;
6059 const MCInstrInfo &MII;
6160 ParseInstructionInfo *InstInfo;
6261 std::unique_ptr Instrumentation;
759758
760759 bool is64BitMode() const {
761760 // FIXME: Can tablegen auto-generate this?
762 return STI.getFeatureBits()[X86::Mode64Bit];
761 return getSTI().getFeatureBits()[X86::Mode64Bit];
763762 }
764763 bool is32BitMode() const {
765764 // FIXME: Can tablegen auto-generate this?
766 return STI.getFeatureBits()[X86::Mode32Bit];
765 return getSTI().getFeatureBits()[X86::Mode32Bit];
767766 }
768767 bool is16BitMode() const {
769768 // FIXME: Can tablegen auto-generate this?
770 return STI.getFeatureBits()[X86::Mode16Bit];
769 return getSTI().getFeatureBits()[X86::Mode16Bit];
771770 }
772771 void SwitchMode(unsigned mode) {
773772 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
801800 public:
802801 X86AsmParser(MCSubtargetInfo &sti, MCAsmParser &Parser,
803802 const MCInstrInfo &mii, const MCTargetOptions &Options)
804 : MCTargetAsmParser(Options), STI(sti), MII(mii), InstInfo(nullptr) {
803 : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr) {
805804
806805 // Initialize the set of available features.
807 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
806 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
808807 Instrumentation.reset(
809808 CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
810809 }
17441743 }
17451744
17461745 // rounding mode token
1747 if (STI.getFeatureBits()[X86::FeatureAVX512] &&
1746 if (getSTI().getFeatureBits()[X86::FeatureAVX512] &&
17481747 getLexer().is(AsmToken::LCurly))
17491748 return ParseRoundingModeOp(Start, End);
17501749
18021801 }
18031802 case AsmToken::LCurly:{
18041803 SMLoc Start = Parser.getTok().getLoc(), End;
1805 if (STI.getFeatureBits()[X86::FeatureAVX512])
1804 if (getSTI().getFeatureBits()[X86::FeatureAVX512])
18061805 return ParseRoundingModeOp(Start, End);
18071806 return ErrorOperand(Start, "unknown token in expression");
18081807 }
18121811 bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
18131812 const MCParsedAsmOperand &Op) {
18141813 MCAsmParser &Parser = getParser();
1815 if(STI.getFeatureBits()[X86::FeatureAVX512]) {
1814 if(getSTI().getFeatureBits()[X86::FeatureAVX512]) {
18161815 if (getLexer().is(AsmToken::LCurly)) {
18171816 // Eat "{" and mark the current place.
18181817 const SMLoc consumedToken = consumeToken();
30513051
30523052 if (HasDeprecation) {
30533053 OS << " std::string Info;\n";
3054 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, STI, Info)) {\n";
3054 OS << " if (MII.get(Inst.getOpcode()).getDeprecatedInfo(Inst, getSTI(), Info)) {\n";
30553055 OS << " SMLoc Loc = ((" << Target.getName()
30563056 << "Operand&)*Operands[0]).getStartLoc();\n";
30573057 OS << " getParser().Warning(Loc, Info, None);\n";