llvm.org GIT mirror llvm / ff16685
Fix pr18515. My understanding (from reading just the llvm code) is that * most ppc cpus have a "sync n" instruction and an msync alias that is "sync 0". * "book e" cpus instead have a msync instruction and not the more general "sync n" This patch reflects that in the .td files, allowing a single codepath for asm ond obj streamer and incidentelly fixes a crash when EmitRawText was called on a obj streamer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@199832 91177308-0d34-0410-b5e6-96231b3b80d8 Rafael Espindola 6 years ago
2 changed file(s) with 18 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
696696 return;
697697 }
698698 break;
699 case PPC::SYNC:
700 // In Book E sync is called msync, handle this special case here...
701 if (Subtarget.isBookE()) {
702 OutStreamer.EmitRawText(StringRef("\tmsync"));
703 return;
704 }
705 break;
706699 case PPC::LD:
707700 case PPC::STD:
708701 case PPC::LWA_32:
598598 def In32BitMode : Predicate<"!PPCSubTarget.isPPC64()">;
599599 def In64BitMode : Predicate<"PPCSubTarget.isPPC64()">;
600600 def IsBookE : Predicate<"PPCSubTarget.isBookE()">;
601 def IsNotBookE : Predicate<"!PPCSubTarget.isBookE()">;
601602
602603 //===----------------------------------------------------------------------===//
603604 // PowerPC Multiclass Definitions.
15491550 "stmw $rS, $dst", IIC_LdStLMW, []>;
15501551
15511552 def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
1552 "sync $L", IIC_LdStSync, []>;
1553 def : Pat<(int_ppc_sync), (SYNC 0)>;
1553 "sync $L", IIC_LdStSync, []>, Requires<[IsNotBookE]>;
1554
1555 let isCodeGenOnly = 1 in {
1556 def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
1557 "msync", IIC_LdStSync, []>, Requires<[IsBookE]> {
1558 let L = 0;
1559 }
1560 }
1561
1562 def : Pat<(int_ppc_sync), (SYNC 0)>, Requires<[IsNotBookE]>;
1563 def : Pat<(int_ppc_sync), (MSYNC)>, Requires<[IsBookE]>;
15541564
15551565 //===----------------------------------------------------------------------===//
15561566 // PPC32 Arithmetic Instructions.
23172327 def : Pat<(f64 (fextend f32:$src)),
23182328 (COPY_TO_REGCLASS $src, F8RC)>;
23192329
2320 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>;
2330 def : Pat<(atomic_fence (imm), (imm)), (SYNC 0)>, Requires<[IsNotBookE]>;
2331 def : Pat<(atomic_fence (imm), (imm)), (MSYNC)>, Requires<[IsBookE]>;
23212332
23222333 // Additional FNMSUB patterns: -a*c + b == -(a*c - b)
23232334 def : Pat<(fma (fneg f64:$A), f64:$C, f64:$B),
24062417
24072418 def : InstAlias<"sc", (SC 0)>;
24082419
2409 def : InstAlias<"sync", (SYNC 0)>;
2410 def : InstAlias<"msync", (SYNC 0)>;
2411 def : InstAlias<"lwsync", (SYNC 1)>;
2412 def : InstAlias<"ptesync", (SYNC 2)>;
2420 def : InstAlias<"sync", (SYNC 0)>, Requires<[IsNotBookE]>;
2421 def : InstAlias<"msync", (SYNC 0)>, Requires<[IsNotBookE]>;
2422 def : InstAlias<"lwsync", (SYNC 1)>, Requires<[IsNotBookE]>;
2423 def : InstAlias<"ptesync", (SYNC 2)>, Requires<[IsNotBookE]>;
24132424
24142425 def : InstAlias<"wait", (WAIT 0)>;
24152426 def : InstAlias<"waitrsv", (WAIT 1)>;