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[DAGCombiner] Use getAPIntValue() instead of getZExtValue() where possible. Better handling of out-of-i64-range values due to large integer types or from fuzz tests. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363955 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 28 days ago
1 changed file(s) with 20 addition(s) and 21 deletion(s). Raw diff Collapse all Expand all
31893189 if (!LegalOperations && N1.getOpcode() == ISD::SRL && N1.hasOneUse()) {
31903190 SDValue ShAmt = N1.getOperand(1);
31913191 ConstantSDNode *ShAmtC = isConstOrConstSplat(ShAmt);
3192 if (ShAmtC && ShAmtC->getZExtValue() == N1.getScalarValueSizeInBits() - 1) {
3192 if (ShAmtC &&
3193 ShAmtC->getAPIntValue() == (N1.getScalarValueSizeInBits() - 1)) {
31933194 SDValue SRA = DAG.getNode(ISD::SRA, DL, VT, N1.getOperand(0), ShAmt);
31943195 return DAG.getNode(ISD::ADD, DL, VT, N0, SRA);
31953196 }
74917492 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0, NewOp1);
74927493 }
74937494
7495 // fold (sra (trunc (sra x, c1)), c2) -> (trunc (sra x, c1 + c2))
74947496 // fold (sra (trunc (srl x, c1)), c2) -> (trunc (sra x, c1 + c2))
74957497 // if c1 is equal to the number of bits the trunc removes
74967498 // TODO - support non-uniform vector shift amounts.
74987500 (N0.getOperand(0).getOpcode() == ISD::SRL ||
74997501 N0.getOperand(0).getOpcode() == ISD::SRA) &&
75007502 N0.getOperand(0).hasOneUse() &&
7501 N0.getOperand(0).getOperand(1).hasOneUse() &&
7502 N1C) {
7503 N0.getOperand(0).getOperand(1).hasOneUse() && N1C) {
75037504 SDValue N0Op0 = N0.getOperand(0);
75047505 if (ConstantSDNode *LargeShift = isConstOrConstSplat(N0Op0.getOperand(1))) {
7505 unsigned LargeShiftVal = LargeShift->getZExtValue();
75067506 EVT LargeVT = N0Op0.getValueType();
7507
7508 if (LargeVT.getScalarSizeInBits() - OpSizeInBits == LargeShiftVal) {
7507 unsigned TruncBits = LargeVT.getScalarSizeInBits() - OpSizeInBits;
7508 if (LargeShift->getAPIntValue() == TruncBits) {
75097509 SDLoc DL(N);
7510 SDValue Amt =
7511 DAG.getConstant(LargeShiftVal + N1C->getZExtValue(), DL,
7512 getShiftAmountTy(N0Op0.getOperand(0).getValueType()));
7513 SDValue SRA = DAG.getNode(ISD::SRA, DL, LargeVT,
7514 N0Op0.getOperand(0), Amt);
7510 SDValue Amt = DAG.getConstant(N1C->getZExtValue() + TruncBits, DL,
7511 getShiftAmountTy(LargeVT));
7512 SDValue SRA =
7513 DAG.getNode(ISD::SRA, DL, LargeVT, N0Op0.getOperand(0), Amt);
75157514 return DAG.getNode(ISD::TRUNCATE, DL, VT, SRA);
75167515 }
75177516 }
76317630 // Shifting in all undef bits?
76327631 EVT SmallVT = N0.getOperand(0).getValueType();
76337632 unsigned BitSize = SmallVT.getScalarSizeInBits();
7634 if (N1C->getZExtValue() >= BitSize)
7633 if (N1C->getAPIntValue().uge(BitSize))
76357634 return DAG.getUNDEF(VT);
76367635
76377636 if (!LegalTypes || TLI.isTypeDesirableForOp(ISD::SRL, SmallVT)) {
76527651
76537652 // fold (srl (sra X, Y), 31) -> (srl X, 31). This srl only looks at the sign
76547653 // bit, which is unmodified by sra.
7655 if (N1C && N1C->getZExtValue() + 1 == OpSizeInBits) {
7654 if (N1C && N1C->getAPIntValue() == (OpSizeInBits - 1)) {
76567655 if (N0.getOpcode() == ISD::SRA)
76577656 return DAG.getNode(ISD::SRL, SDLoc(N), VT, N0.getOperand(0), N1);
76587657 }
1036910368 // fold (sext_in_reg (srl X, 23), i8) -> (sra X, 23) iff possible.
1037010369 // We already fold "(sext_in_reg (srl X, 25), i8) -> srl X, 25" above.
1037110370 if (N0.getOpcode() == ISD::SRL) {
10372 if (ConstantSDNode *ShAmt = dyn_cast(N0.getOperand(1)))
10373 if (ShAmt->getZExtValue()+EVTBits <= VTBits) {
10371 if (auto *ShAmt = dyn_cast(N0.getOperand(1)))
10372 if (ShAmt->getAPIntValue().ule(VTBits - EVTBits)) {
1037410373 // We can turn this into an SRA iff the input to the SRL is already sign
1037510374 // extended enough.
1037610375 unsigned InSignBits = DAG.ComputeNumSignBits(N0.getOperand(0));
10377 if (VTBits-(ShAmt->getZExtValue()+EVTBits) < InSignBits)
10378 return DAG.getNode(ISD::SRA, SDLoc(N), VT,
10379 N0.getOperand(0), N0.getOperand(1));
10376 if (((VTBits - EVTBits) - ShAmt->getZExtValue()) < InSignBits)
10377 return DAG.getNode(ISD::SRA, SDLoc(N), VT, N0.getOperand(0),
10378 N0.getOperand(1));
1038010379 }
1038110380 }
1038210381
1786817867 return SDValue();
1786917868 }
1787017869
17871 unsigned IdentityIndex = i * PartNumElem;
17872 ConstantSDNode *CS = dyn_cast(Op.getOperand(1));
17870 auto *CS = dyn_cast(Op.getOperand(1));
1787317871 // The extract index must be constant.
1787417872 if (!CS)
1787517873 return SDValue();
1787617874
1787717875 // Check that we are reading from the identity index.
17878 if (CS->getZExtValue() != IdentityIndex)
17876 unsigned IdentityIndex = i * PartNumElem;
17877 if (CS->getAPIntValue() != IdentityIndex)
1787917878 return SDValue();
1788017879 }
1788117880