llvm.org GIT mirror llvm / fe80951
Merging r340927: ------------------------------------------------------------------------ r340927 | vstefanovic | 2018-08-29 07:07:14 -0700 (Wed, 29 Aug 2018) | 14 lines [mips] Prevent shrink-wrap for BuildPairF64, ExtractElementF64 when they use $sp For a certain combination of options, BuildPairF64_{64}, ExtractElementF64{_64} may be expanded into instructions using stack. Add implicit operand $sp for such cases so that ShrinkWrapping doesn't move prologue setup below them. Fixes MultiSource/Benchmarks/MallocBench/cfrac for '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfpxx -mnan=2008' and '--target=mips-img-linux-gnu -mcpu=mips32r6 -mfp64 -mnan=2008 -mno-odd-spreg'. Differential Revision: https://reviews.llvm.org/D50986 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@346734 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 11 months ago
4 changed file(s) with 206 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
298298 // register). Unfortunately, we have to make this decision before register
299299 // allocation so for now we use a spill/reload sequence for all
300300 // double-precision values in regardless of being an odd/even register.
301 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
302 (FP64 && !Subtarget.useOddSPReg())) {
301 //
302 // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as
303 // implicit operand, so other passes (like ShrinkWrapping) are aware that
304 // stack is used.
305 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
306 && I->getOperand(3).getReg() == Mips::SP) {
303307 unsigned DstReg = I->getOperand(0).getReg();
304308 unsigned LoReg = I->getOperand(1).getReg();
305309 unsigned HiReg = I->getOperand(2).getReg();
359363 // register). Unfortunately, we have to make this decision before register
360364 // allocation so for now we use a spill/reload sequence for all
361365 // double-precision values in regardless of being an odd/even register.
362
363 if ((Subtarget.isABI_FPXX() && !Subtarget.hasMTHC1()) ||
364 (FP64 && !Subtarget.useOddSPReg())) {
366 //
367 // For the cases that should be covered here MipsSEISelDAGToDAG adds $sp as
368 // implicit operand, so other passes (like ShrinkWrapping) are aware that
369 // stack is used.
370 if (I->getNumOperands() == 4 && I->getOperand(3).isReg()
371 && I->getOperand(3).getReg() == Mips::SP) {
365372 unsigned DstReg = I->getOperand(0).getReg();
366373 unsigned SrcReg = Op1.getReg();
367374 unsigned N = Op2.getImm();
236236 break;
237237 case Mips::WRDSP:
238238 addDSPCtrlRegOperands(true, MI, MF);
239 break;
240 case Mips::BuildPairF64_64:
241 case Mips::ExtractElementF64_64:
242 if (!Subtarget->useOddSPReg()) {
243 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
244 break;
245 }
246 // fallthrough
247 case Mips::BuildPairF64:
248 case Mips::ExtractElementF64:
249 if (Subtarget->isABI_FPXX() && !Subtarget->hasMTHC1())
250 MI.addOperand(MachineOperand::CreateReg(Mips::SP, false, true));
239251 break;
240252 default:
241253 replaceUsesWithZeroReg(MRI, MI);
0 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
1 ; RUN: -mcpu=mips32 -mattr=+fpxx \
2 ; RUN: -stop-after=expand-isel-pseudos | \
3 ; RUN: FileCheck %s -check-prefix=FPXX-IMPLICIT-SP
4
5 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
6 ; RUN: -mcpu=mips32r6 -mattr=+fp64,+nooddspreg \
7 ; RUN: -stop-after=expand-isel-pseudos | \
8 ; RUN: FileCheck %s -check-prefix=FP64-IMPLICIT-SP
9
10 ; RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu \
11 ; RUN: -mcpu=mips32r2 -mattr=+fpxx \
12 ; RUN: -stop-after=expand-isel-pseudos | \
13 ; RUN: FileCheck %s -check-prefix=NO-IMPLICIT-SP
14
15 define double @foo2(i32 signext %v1, double %d1) {
16 entry:
17 ; FPXX-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
18 ; FPXX-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp
19 ; FP64-IMPLICIT-SP: BuildPairF64_64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
20 ; FP64-IMPLICIT-SP: ExtractElementF64_64 killed %{{[0-9]+}}, 1, implicit $sp
21 ; NO-IMPLICIT-SP: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}
22 ; NO-IMPLICIT-SP-NOT: BuildPairF64 %{{[0-9]+}}, %{{[0-9]+}}, implicit $sp
23 ; NO-IMPLICIT-SP: ExtractElementF64 killed %{{[0-9]+}}, 1
24 ; NO-IMPLICIT-SP-NOT: ExtractElementF64 killed %{{[0-9]+}}, 1, implicit $sp
25 %conv = fptrunc double %d1 to float
26 %0 = tail call float @llvm.copysign.f32(float 1.000000e+00, float %conv)
27 %conv1 = fpext float %0 to double
28 ret double %conv1
29 }
30
31 declare float @llvm.copysign.f32(float, float)
0 # RUN: llc -o - %s -mtriple=mips-unknown-linux-gnu -enable-shrink-wrap=true \
1 # RUN: -start-before=shrink-wrap -stop-after=prologepilog | FileCheck %s
2
3 --- |
4 declare void @foo()
5 define void @testBuildPairF64() {
6 ret void
7 }
8 define void @testBuildPairF64_64() {
9 ret void
10 }
11 define void @testBuildPairF64implicitSp() {
12 ret void
13 }
14 define void @testBuildPairF64_64implicitSp() {
15 ret void
16 }
17 define void @testExtractElementF64() {
18 ret void
19 }
20 define void @testExtractElementF64_64() {
21 ret void
22 }
23 define void @testExtractElementF64implicitSp() {
24 ret void
25 }
26 define void @testExtractElementF64_64implicitSp() {
27 ret void
28 }
29 ...
30 ---
31 name: testBuildPairF64
32 # CHECK-LABEL: name: testBuildPairF64
33 # CHECK: bb.0
34 # CHECK-NEXT: successors
35 # CHECK-NEXT: {{[[:space:]]$}}
36 # CHECK-NEXT: BuildPairF64
37 body: |
38 bb.0:
39 $d0 = BuildPairF64 $zero, $zero
40 bb.1:
41 JAL @foo, implicit-def $ra
42 bb.2:
43 RetRA
44 ...
45 ---
46 name: testBuildPairF64_64
47 # CHECK-LABEL: name: testBuildPairF64_64
48 # CHECK: bb.0
49 # CHECK-NEXT: successors
50 # CHECK-NEXT: {{[[:space:]]$}}
51 # CHECK-NEXT: BuildPairF64_64
52 body: |
53 bb.0:
54 $d0_64 = BuildPairF64_64 $zero, $zero
55 bb.1:
56 JAL @foo, implicit-def $ra
57 bb.2:
58 RetRA
59 ...
60 ---
61 name: testBuildPairF64implicitSp
62 # CHECK-LABEL: name: testBuildPairF64implicitSp
63 # CHECK: bb.0
64 # CHECK-NEXT: successors
65 # CHECK-NEXT: {{[[:space:]]$}}
66 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
67 body: |
68 bb.0:
69 $d0 = BuildPairF64 $zero, $zero, implicit $sp
70 bb.1:
71 JAL @foo, implicit-def $ra
72 bb.2:
73 RetRA
74 ...
75 ---
76 name: testBuildPairF64_64implicitSp
77 # CHECK-LABEL: name: testBuildPairF64_64implicitSp
78 # CHECK: bb.0
79 # CHECK-NEXT: successors
80 # CHECK-NEXT: {{[[:space:]]$}}
81 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
82 body: |
83 bb.0:
84 $d0_64 = BuildPairF64_64 $zero, $zero, implicit $sp
85 bb.1:
86 JAL @foo, implicit-def $ra
87 bb.2:
88 RetRA
89 ...
90 ---
91 name: testExtractElementF64
92 # CHECK-LABEL: name: testExtractElementF64
93 # CHECK: bb.0
94 # CHECK-NEXT: successors
95 # CHECK-NEXT: {{[[:space:]]$}}
96 # CHECK-NEXT: ExtractElementF64
97 body: |
98 bb.0:
99 $at = ExtractElementF64 $d6, 1
100 bb.1:
101 JAL @foo, implicit-def $ra
102 bb.2:
103 RetRA
104 ...
105 ---
106 name: testExtractElementF64_64
107 # CHECK-LABEL: name: testExtractElementF64_64
108 # CHECK: bb.0
109 # CHECK-NEXT: successors
110 # CHECK-NEXT: {{[[:space:]]$}}
111 # CHECK-NEXT: ExtractElementF64_64
112 body: |
113 bb.0:
114 $at = ExtractElementF64_64 $d12_64, 1
115 bb.1:
116 JAL @foo, implicit-def $ra
117 bb.2:
118 RetRA
119 ...
120 ---
121 name: testExtractElementF64implicitSp
122 # CHECK-LABEL: name: testExtractElementF64implicitSp
123 # CHECK: bb.0
124 # CHECK-NEXT: successors
125 # CHECK-NEXT: {{[[:space:]]$}}
126 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
127 body: |
128 bb.0:
129 $at = ExtractElementF64 $d6, 1, implicit $sp
130 bb.1:
131 JAL @foo, implicit-def $ra
132 bb.2:
133 RetRA
134 ...
135 ---
136 name: testExtractElementF64_64implicitSp
137 # CHECK-LABEL: name: testExtractElementF64_64implicitSp
138 # CHECK: bb.0
139 # CHECK-NEXT: successors
140 # CHECK-NEXT: {{[[:space:]]$}}
141 # CHECK-NEXT: $sp = ADDiu $sp, -{{[0-9]+}}
142 body: |
143 bb.0:
144 $at = ExtractElementF64_64 $d12_64, 1, implicit $sp
145 bb.1:
146 JAL @foo, implicit-def $ra
147 bb.2:
148 RetRA
149 ...