llvm.org GIT mirror llvm / fe2a6c5
Fix VINSERTF128/VEXTRACTF128 to be marked as FP instructions. Allow execution dependency fix pass to convert them to their integer equivalents when AVX2 is enabled. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@145376 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 8 years ago
6 changed file(s) with 23 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
35673567 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
35683568 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
35693569 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
3570 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
3571 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
35723570 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
3573 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr }
3571 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
3572 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
3573 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
3574 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
3575 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
3576 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
3577 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr }
35743578 };
35753579
35763580 // FIXME: Some shuffle and unpack instructions have equivalents in different
71467146 //===----------------------------------------------------------------------===//
71477147 // VINSERTF128 - Insert packed floating-point values
71487148 //
7149 let neverHasSideEffects = 1 in {
7149 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
71507150 def VINSERTF128rr : AVXAIi8<0x18, MRMSrcReg, (outs VR256:$dst),
71517151 (ins VR256:$src1, VR128:$src2, i8imm:$src3),
71527152 "vinsertf128\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
71937193 //===----------------------------------------------------------------------===//
71947194 // VEXTRACTF128 - Extract packed floating-point values
71957195 //
7196 let neverHasSideEffects = 1 in {
7196 let neverHasSideEffects = 1, ExeDomain = SSEPackedSingle in {
71977197 def VEXTRACTF128rr : AVXAIi8<0x19, MRMDestReg, (outs VR128:$dst),
71987198 (ins VR256:$src1, i8imm:$src2),
71997199 "vextractf128\t{$src2, $src1, $dst|$dst, $src1, $src2}",
1515 ret <4 x double> %shuffle.i
1616 }
1717
18 ; CHECK: vpxor
18 ; CHECK: vxorps
1919 ; CHECK-NEXT: vinsertf128 $0
2020 define <4 x i64> @castC(<2 x i64> %m) nounwind uwtable readnone ssp {
2121 entry:
21392139
21402140
21412141 define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
2142 ; CHECK: vmovdqu
2142 ; FIXME: unfortunately the execution domain fix pass changes this to vmovups and its hard to force with no 256-bit integer instructions
2143 ; CHECK: vmovups
21432144 ; add operation forces the execution domain.
21442145 %a2 = add <32 x i8> %a1,
21452146 call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
4646 ; shuffle (scalar_to_vector (load (ptr + 4))), undef, <0, 0, 0, 0>
4747 ; To:
4848 ; shuffle (vload ptr)), undef, <1, 1, 1, 1>
49 ; CHECK: vmovdqa
49 ; CHECK: vmovaps
5050 ; CHECK-NEXT: vinsertf128 $1
5151 ; CHECK-NEXT: vpermilps $-1
5252 define <8 x float> @funcE() nounwind {
10451045 ret <8 x i32> %res
10461046 }
10471047 declare <8 x i32> @llvm.x86.avx2.psrav.d.256(<8 x i32>, <8 x i32>) nounwind readnone
1048
1049 ; This is checked here because the execution dependency fix pass makes it hard to test in AVX mode since we don't have 256-bit integer instructions
1050 define void @test_x86_avx_storeu_dq_256(i8* %a0, <32 x i8> %a1) {
1051 ; CHECK: vmovdqu
1052 ; add operation forces the execution domain.
1053 %a2 = add <32 x i8> %a1,
1054 call void @llvm.x86.avx.storeu.dq.256(i8* %a0, <32 x i8> %a2)
1055 ret void
1056 }
1057 declare void @llvm.x86.avx.storeu.dq.256(i8*, <32 x i8>) nounwind