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Fix an assertion in DwarfExpression when emitting fragments in vector registers When DwarfExpression is emitting a fragment that is located in a register and that fragment is smaller than the register, and the register must be composed from sub-registers (are you still with me?) the last DW_OP_piece operation must not be larger than the size of the fragment itself, since the last piece of the fragment could be smaller than the last subregister that is being emitted. rdar://problem/29779065 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290324 91177308-0d34-0410-b5e6-96231b3b80d8 Adrian Prantl 3 years ago
3 changed file(s) with 86 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
8585 }
8686
8787 bool DwarfExpression::AddMachineReg(const TargetRegisterInfo &TRI,
88 unsigned MachineReg) {
88 unsigned MachineReg, unsigned MaxSize) {
8989 if (!TRI.isPhysicalRegister(MachineReg))
9090 return false;
9191
136136 // its range, emit a DWARF piece for it.
137137 if (Reg >= 0 && Intersection.any()) {
138138 AddReg(Reg, "sub-register");
139 if (Offset >= MaxSize)
140 break;
139141 // Emit a piece for the any gap in the coverage.
140142 if (Offset > CurPos)
141143 AddOpPiece(Offset - CurPos);
142 AddOpPiece(Size);
144 AddOpPiece(std::min(Size, MaxSize - Offset));
143145 CurPos = Offset + Size;
144146
145147 // Mark it as emitted.
195197 bool ValidReg = false;
196198 auto Op = ExprCursor.peek();
197199 switch (Op->getOp()) {
198 default:
199 ValidReg = AddMachineReg(TRI, MachineReg);
200 default: {
201 auto Fragment = ExprCursor.getFragmentInfo();
202 ValidReg = AddMachineReg(TRI, MachineReg,
203 Fragment ? Fragment->SizeInBits : ~1U);
200204 break;
205 }
201206 case dwarf::DW_OP_plus:
202207 case dwarf::DW_OP_minus: {
203208 // [DW_OP_reg,Offset,DW_OP_plus, DW_OP_deref] --> [DW_OP_breg, Offset].
7171 }
7272 /// Determine whether there are any operations left in this expression.
7373 operator bool() const { return Start != End; }
74
75 /// Retrieve the fragment information, if any.
76 Optional getFragmentInfo() const {
77 return DIExpression::getFragmentInfo(Start, End);
78 }
7479 };
7580
7681 /// Base class containing the logic for constructing DWARF expressions
144149 /// Emit a partial DWARF register operation.
145150 ///
146151 /// \param MachineReg The register number.
152 /// \param MaxSize If the register must be composed from
153 /// sub-registers this is an upper bound
154 /// for how many bits the emitted DW_OP_piece
155 /// may cover.
147156 ///
148157 /// If size and offset is zero an operation for the entire register is
149158 /// emitted: Some targets do not provide a DWARF register number for every
152161 /// multiple subregisters that alias the register.
153162 ///
154163 /// \return false if no DWARF register exists for MachineReg.
155 bool AddMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg);
164 bool AddMachineReg(const TargetRegisterInfo &TRI, unsigned MachineReg,
165 unsigned MaxSize = ~1U);
156166
157167 /// Emit a signed constant.
158168 void AddSignedConstant(int64_t Value);
0 ; RUN: llc %s -filetype=obj -o - | llvm-dwarfdump - | FileCheck %s
1 ; This tests a fragment that partially covers subregister compositions.
2 ;
3 ; Our fragment is 96 bits long and lies in a 128-bit register, which
4 ; in turn has to be composed out of its two 64-bit subregisters.
5
6 ; CHECK: .debug_info
7 ; CHECK: DW_TAG_subprogram
8 ; CHECK: DW_AT_name {{.*}}"subscript.get"
9 ; CHECK: DW_TAG_formal_parameter
10 ; CHECK-NEXT: DW_AT_location [DW_FORM_sec_offset] (0x00000000)
11 ; CHECK: .debug_loc
12 ; CHECK: 0x00000000: Beginning address offset
13 ; CHECK-NEXT: Ending address offset
14 ; CHECK-NEXT: Location description: 90 90 02 93 08 90 91 02 93 04
15 ; d16, piece 0x00000008, d17, piece 0x00000004
16 source_filename = "simd.ll"
17 target datalayout = "e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32"
18 target triple = "armv7-apple-ios7.0"
19
20 ; Function Attrs: nounwind readnone
21 declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #0
22
23 define <3 x float> @_TFV4simd8float2x3g9subscriptFSiVS_6float3(i32, <3 x float>, <3 x float>) !dbg !5 {
24 entry:
25 tail call void @llvm.dbg.value(metadata <3 x float> %1, i64 0, metadata !8, metadata !9), !dbg !10
26 tail call void @llvm.dbg.value(metadata <3 x float> %2, i64 0, metadata !8, metadata !11), !dbg !10
27 %3 = icmp eq i32 %0, 0, !dbg !12
28 br i1 %3, label %7, label %4, !dbg !12
29
30 ;
31 %5 = icmp eq i32 %0, 1, !dbg !15
32 br i1 %5, label %7, label %6, !dbg !15
33
34 ;
35 unreachable, !dbg !17
36
37 ;
38 %8 = phi <3 x float> [ %1, %entry ], [ %2, %4 ], !dbg !18
39 ret <3 x float> %8, !dbg !18
40 }
41
42 attributes #0 = { nounwind readnone }
43
44 !llvm.dbg.cu = !{!0}
45 !llvm.module.flags = !{!3, !4}
46
47 !0 = distinct !DICompileUnit(language: DW_LANG_Swift, file: !1, producer: "Swift", isOptimized: false, runtimeVersion: 3, emissionKind: FullDebug, enums: !2, imports: !2)
48 !1 = !DIFile(filename: "simd.swift", directory: "/")
49 !2 = !{}
50 !3 = !{i32 2, !"Dwarf Version", i32 4}
51 !4 = !{i32 2, !"Debug Info Version", i32 3}
52 !5 = distinct !DISubprogram(name: "subscript.get", linkageName: "_TFV4simd8float2x3g9subscriptFSiVS_6float3", scope: !6, file: !1, type: !7, isLocal: false, isDefinition: true, isOptimized: true, unit: !0, variables: !2)
53 !6 = !DICompositeType(tag: DW_TAG_structure_type, name: "float2x3", scope: !0, file: !1, line: 5824, size: 256, align: 128, elements: !2, runtimeLang: DW_LANG_Swift, identifier: "_TtV4simd8float2x3")
54 !7 = !DISubroutineType(types: !2)
55 !8 = !DILocalVariable(name: "self", arg: 2, scope: !5, file: !1, line: 5897, type: !6, flags: DIFlagArtificial)
56 !9 = !DIExpression(DW_OP_LLVM_fragment, 0, 96)
57 !10 = !DILocation(line: 5897, column: 5, scope: !5)
58 !11 = !DIExpression(DW_OP_LLVM_fragment, 96, 96)
59 !12 = !DILocation(line: 5900, column: 12, scope: !13)
60 !13 = distinct !DILexicalBlock(scope: !14, file: !1, line: 5898, column: 7)
61 !14 = distinct !DILexicalBlock(scope: !5, file: !1, line: 5897, column: 9)
62 !15 = !DILocation(line: 5902, column: 12, scope: !16)
63 !16 = distinct !DILexicalBlock(scope: !14, file: !1, line: 5898, column: 7)
64 !17 = !DILocation(line: 0, scope: !5)
65 !18 = !DILocation(line: 5906, column: 5, scope: !14)