llvm.org GIT mirror llvm / fd652df
Fix #13035, a bug around Thumb instruction LDRD/STRD with negative #0 offset index issue. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161162 91177308-0d34-0410-b5e6-96231b3b80d8 Jiangning Liu 8 years ago
5 changed file(s) with 52 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
10391039 // Immediate offset a multiple of 4 in range [-1020, 1020].
10401040 if (!Memory.OffsetImm) return true;
10411041 int64_t Val = Memory.OffsetImm->getValue();
1042 return Val >= -1020 && Val <= 1020 && (Val & 3) == 0;
1042 // Special case, #-0 is INT32_MIN.
1043 return (Val >= -1020 && Val <= 1020 && (Val & 3) == 0) || Val == INT32_MIN;
10431044 }
10441045 bool isMemImm0_1020s4Offset() const {
10451046 if (!isMemory() || Memory.OffsetRegNum != 0 || Memory.Alignment != 0)
31503150
31513151 static DecodeStatus DecodeT2Imm8S4(MCInst &Inst, unsigned Val,
31523152 uint64_t Address, const void *Decoder) {
3153 int imm = Val & 0xFF;
3154 if (!(Val & 0x100)) imm *= -1;
3155 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3153 if (Val == 0)
3154 Inst.addOperand(MCOperand::CreateImm(INT32_MIN));
3155 else {
3156 int imm = Val & 0xFF;
3157
3158 if (!(Val & 0x100)) imm *= -1;
3159 Inst.addOperand(MCOperand::CreateImm(imm << 2));
3160 }
31563161
31573162 return MCDisassembler::Success;
31583163 }
971971
972972 O << "[" << getRegisterName(MO1.getReg());
973973
974 int32_t OffImm = (int32_t)MO2.getImm() / 4;
974 int32_t OffImm = (int32_t)MO2.getImm();
975
976 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
977
975978 // Don't print +0.
976 if (OffImm < 0)
977 O << ", #-" << -OffImm * 4;
979 if (OffImm == INT32_MIN)
980 O << ", #-0";
981 else if (OffImm < 0)
982 O << ", #-" << -OffImm;
978983 else if (OffImm > 0)
979 O << ", #" << OffImm * 4;
984 O << ", #" << OffImm;
980985 O << "]";
981986 }
982987
10081013 unsigned OpNum,
10091014 raw_ostream &O) {
10101015 const MCOperand &MO1 = MI->getOperand(OpNum);
1011 int32_t OffImm = (int32_t)MO1.getImm() / 4;
1016 int32_t OffImm = (int32_t)MO1.getImm();
1017
1018 assert(((OffImm & 0x3) == 0) && "Not a valid immediate!");
1019
10121020 // Don't print +0.
1013 if (OffImm != 0) {
1014 O << ", ";
1015 if (OffImm < 0)
1016 O << "#-" << -OffImm * 4;
1017 else if (OffImm > 0)
1018 O << "#" << OffImm * 4;
1019 }
1021 if (OffImm == INT32_MIN)
1022 O << ", #-0";
1023 else if (OffImm < 0)
1024 O << ", #-" << -OffImm;
1025 else if (OffImm > 0)
1026 O << ", #" << OffImm;
10201027 }
10211028
10221029 void ARMInstPrinter::printT2AddrModeSoRegOperand(const MCInst *MI,
851851 ldrd r3, r5, [r6], #-8
852852 ldrd r3, r5, [r6]
853853 ldrd r8, r1, [r3, #0]
854 ldrd r0, r1, [r2, #-0]
855 ldrd r0, r1, [r2, #-0]!
856 ldrd r0, r1, [r2], #-0
854857
855858 @ CHECK: ldrd r3, r5, [r6, #24] @ encoding: [0xd6,0xe9,0x06,0x35]
856859 @ CHECK: ldrd r3, r5, [r6, #24]! @ encoding: [0xf6,0xe9,0x06,0x35]
858861 @ CHECK: ldrd r3, r5, [r6], #-8 @ encoding: [0x76,0xe8,0x02,0x35]
859862 @ CHECK: ldrd r3, r5, [r6] @ encoding: [0xd6,0xe9,0x00,0x35]
860863 @ CHECK: ldrd r8, r1, [r3] @ encoding: [0xd3,0xe9,0x00,0x81]
864 @ CHECK: ldrd r0, r1, [r2, #-0] @ encoding: [0x52,0xe9,0x00,0x01]
865 @ CHECK: ldrd r0, r1, [r2, #-0]! @ encoding: [0x72,0xe9,0x00,0x01]
866 @ CHECK: ldrd r0, r1, [r2], #-0 @ encoding: [0x72,0xe8,0x00,0x01]
861867
862868
863869 @------------------------------------------------------------------------------
26352641 strd r3, r5, [r6], #-8
26362642 strd r3, r5, [r6]
26372643 strd r8, r1, [r3, #0]
2644 strd r0, r1, [r2, #-0]
2645 strd r0, r1, [r2, #-0]!
2646 strd r0, r1, [r2], #-0
26382647
26392648 @ CHECK: strd r3, r5, [r6, #24] @ encoding: [0xc6,0xe9,0x06,0x35]
26402649 @ CHECK: strd r3, r5, [r6, #24]! @ encoding: [0xe6,0xe9,0x06,0x35]
26422651 @ CHECK: strd r3, r5, [r6], #-8 @ encoding: [0x66,0xe8,0x02,0x35]
26432652 @ CHECK: strd r3, r5, [r6] @ encoding: [0xc6,0xe9,0x00,0x35]
26442653 @ CHECK: strd r8, r1, [r3] @ encoding: [0xc3,0xe9,0x00,0x81]
2654 @ CHECK: strd r0, r1, [r2, #-0] @ encoding: [0x42,0xe9,0x00,0x01]
2655 @ CHECK: strd r0, r1, [r2, #-0]! @ encoding: [0x62,0xe9,0x00,0x01]
2656 @ CHECK: strd r0, r1, [r2], #-0 @ encoding: [0x62,0xe8,0x00,0x01]
26452657
26462658
26472659 @------------------------------------------------------------------------------
640640 # CHECK: ldrd r3, r5, [r6], #-8
641641 # CHECK: ldrd r3, r5, [r6]
642642 # CHECK: ldrd r8, r1, [r3]
643 # CHECK: ldrd r0, r1, [r2], #-0
644 # CHECK: ldrd r0, r1, [r2, #-0]!
645 # CHECK: ldrd r0, r1, [r2, #-0]
643646
644647 0xd6 0xe9 0x06 0x35
645648 0xf6 0xe9 0x06 0x35
647650 0x76 0xe8 0x02 0x35
648651 0xd6 0xe9 0x00 0x35
649652 0xd3 0xe9 0x00 0x81
653 0x72 0xe8 0x00 0x01
654 0x72 0xe9 0x00 0x01
655 0x52 0xe9 0x00 0x01
650656
651657
652658 #------------------------------------------------------------------------------
18211827 # STRD (immediate)
18221828 #------------------------------------------------------------------------------
18231829 # CHECK: strd r6, r3, [r5], #-8
1824 # CHECK: strd r8, r5, [r5]{{$}}
1830 # CHECK: strd r8, r5, [r5], #-0
18251831 # CHECK: strd r7, r4, [r5], #-4
1832 # CHECK: strd r0, r1, [r2, #-0]!
1833 # CHECK: strd r0, r1, [r2, #-0]
18261834
18271835 0x65 0xe8 0x02 0x63
18281836 0x65 0xe8 0x00 0x85
18291837 0x65 0xe8 0x01 0x74
1838 0x62 0xe9 0x00 0x01
1839 0x42 0xe9 0x00 0x01
18301840
18311841 #------------------------------------------------------------------------------
18321842 # STREX/STREXB/STREXH/STREXD