llvm.org GIT mirror llvm / fcc03ff
Recommit: ARM: sort register lists by encoding in push/pop instructions. For example we were producing push {r8, r10, r11, r4, r5, r7, lr} This is misleading (r4, r5 and r7 are actually pushed before the rest), and other components (stack folding recently) often forget to deal with the extra complexity coming from the different order, leading to miscompiles. Finally, we warn about our own code in -no-integrated-as mode without this, which is really not a good idea. Fixed usage of std::sort so that we (hopefully) use instantiations that actually exist in GCC 4.8. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@286881 91177308-0d34-0410-b5e6-96231b3b80d8 Tim Northover 3 years ago
4 changed file(s) with 32 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
892892 unsigned MIFlags) const {
893893 MachineFunction &MF = *MBB.getParent();
894894 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
895 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
895896
896897 DebugLoc DL;
897898
898 SmallVector, 4> Regs;
899 typedef std::pair RegAndKill;
900 SmallVector Regs;
899901 unsigned i = CSI.size();
900902 while (i != 0) {
901903 unsigned LastReg = 0;
926928
927929 if (Regs.empty())
928930 continue;
931
932 std::sort(Regs.begin(), Regs.end(), [&](RegAndKill &LHS, RegAndKill &RHS) {
933 return TRI.getEncodingValue(LHS.first) < TRI.getEncodingValue(RHS.first);
934 });
935
929936 if (Regs.size() > 1 || StrOpc== 0) {
930937 MachineInstrBuilder MIB =
931938 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(StmOpc), ARM::SP)
959966 unsigned NumAlignedDPRCS2Regs) const {
960967 MachineFunction &MF = *MBB.getParent();
961968 const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
969 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
962970 ARMFunctionInfo *AFI = MF.getInfo();
963971 DebugLoc DL;
964972 bool isTailCall = false;
10111019
10121020 if (Regs.empty())
10131021 continue;
1022
1023 std::sort(Regs.begin(), Regs.end(), [&](unsigned LHS, unsigned RHS) {
1024 return TRI.getEncodingValue(LHS) < TRI.getEncodingValue(RHS);
1025 });
1026
10141027 if (Regs.size() > 1 || LdrOpc == 0) {
10151028 MachineInstrBuilder MIB =
10161029 AddDefaultPred(BuildMI(MBB, MI, DL, TII.get(LdmOpc), ARM::SP)
725725 void ARMInstPrinter::printRegisterList(const MCInst *MI, unsigned OpNum,
726726 const MCSubtargetInfo &STI,
727727 raw_ostream &O) {
728 assert(std::is_sorted(MI->begin() + OpNum, MI->end(),
729 [&](const MCOperand &LHS, const MCOperand &RHS) {
730 return MRI.getEncodingValue(LHS.getReg()) <
731 MRI.getEncodingValue(RHS.getReg());
732 }));
733
728734 O << "{";
729735 for (unsigned i = OpNum, e = MI->getNumOperands(); i != e; ++i) {
730736 if (i != OpNum)
15441544 else
15451545 Binary |= NumRegs * 2;
15461546 } else {
1547 const MCRegisterInfo &MRI = *CTX.getRegisterInfo();
1548 assert(std::is_sorted(MI.begin() + Op, MI.end(),
1549 [&](const MCOperand &LHS, const MCOperand &RHS) {
1550 return MRI.getEncodingValue(LHS.getReg()) <
1551 MRI.getEncodingValue(RHS.getReg());
1552 }));
1553
15471554 for (unsigned I = Op, E = MI.getNumOperands(); I < E; ++I) {
1548 unsigned RegNo = CTX.getRegisterInfo()->getEncodingValue(MI.getOperand(I).getReg());
1555 unsigned RegNo = MRI.getEncodingValue(MI.getOperand(I).getReg());
15491556 Binary |= 1 << RegNo;
15501557 }
15511558 }
414414
415415 ; CHECK-ARMV7-LABEL: _params_in_reg
416416 ; Store callee saved registers excluding swifterror.
417 ; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
417 ; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
418418 ; Store swiftself (r10) and swifterror (r6).
419419 ; CHECK-ARMV7-DAG: str r6, [s[[STK1:.*]]]
420420 ; CHECK-ARMV7-DAG: str r10, [s[[STK2:.*]]]
439439 ; CHECK-ARMV7: mov r2, r5
440440 ; CHECK-ARMV7: mov r3, r4
441441 ; CHECK-ARMV7: bl _params_in_reg2
442 ; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
442 ; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
443443 define swiftcc void @params_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
444444 %error_ptr_ref = alloca swifterror %swift_error*, align 8
445445 store %swift_error* null, %swift_error** %error_ptr_ref
450450 declare swiftcc void @params_in_reg2(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err)
451451
452452 ; CHECK-ARMV7-LABEL: params_and_return_in_reg
453 ; CHECK-ARMV7: push {r8, r10, r11, r4, r5, r7, lr}
453 ; CHECK-ARMV7: push {r4, r5, r7, r8, r10, r11, lr}
454454 ; Store swifterror and swiftself
455455 ; CHECK-ARMV7: mov r4, r6
456456 ; CHECK-ARMV7: str r10, [s[[STK1:.*]]]
501501 ; CHECK-ARMV7: mov r1, r4
502502 ; CHECK-ARMV7: mov r2, r8
503503 ; CHECK-ARMV7: mov r3, r11
504 ; CHECK-ARMV7: pop {r8, r10, r11, r4, r5, r7, pc}
504 ; CHECK-ARMV7: pop {r4, r5, r7, r8, r10, r11, pc}
505505 define swiftcc { i32, i32, i32, i32} @params_and_return_in_reg(i32, i32, i32, i32, i8* swiftself, %swift_error** nocapture swifterror %err) {
506506 %error_ptr_ref = alloca swifterror %swift_error*, align 8
507507 store %swift_error* null, %swift_error** %error_ptr_ref