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Simplify eliminateFrameIndex() interface back down now that PEI doesn't need to try to re-use scavenged frame index reference registers. rdar://8277890 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112241 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 9 years ago
32 changed file(s) with 77 addition(s) and 156 deletion(s). Raw diff Collapse all Expand all
742742 /// specified instruction, as long as it keeps the iterator pointing at the
743743 /// finished product. SPAdj is the SP adjustment due to call frame setup
744744 /// instruction.
745 ///
746 /// When -enable-frame-index-scavenging is enabled, the virtual register
747 /// allocated for this frame index is returned and its value is stored in
748 /// *Value.
749 typedef std::pair FrameIndexValue;
750 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
751 int SPAdj, FrameIndexValue *Value = NULL,
752 RegScavenger *RS=NULL) const = 0;
745 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
746 int SPAdj, RegScavenger *RS=NULL) const = 0;
753747
754748 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
755749 /// the function.
6262 const TargetRegisterInfo *TRI = Fn.getTarget().getRegisterInfo();
6363 RS = TRI->requiresRegisterScavenging(Fn) ? new RegScavenger() : NULL;
6464 FrameIndexVirtualScavenging = TRI->requiresFrameIndexScavenging(Fn);
65 FrameConstantRegMap.clear();
6665
6766 // Calculate the MaxCallFrameSize and AdjustsStack variables for the
6867 // function's frame information. Also eliminates call frame pseudo
755754 // If this instruction has a FrameIndex operand, we need to
756755 // use that target machine register info object to eliminate
757756 // it.
758 TargetRegisterInfo::FrameIndexValue Value;
759 unsigned VReg =
760 TRI.eliminateFrameIndex(MI, SPAdj, &Value,
757 TRI.eliminateFrameIndex(MI, SPAdj,
761758 FrameIndexVirtualScavenging ? NULL : RS);
762 if (VReg) {
763 assert (FrameIndexVirtualScavenging &&
764 "Not scavenging, but virtual returned from "
765 "eliminateFrameIndex()!");
766 FrameConstantRegMap[VReg] = FrameConstantEntry(Value, SPAdj);
767 }
768759
769760 // Reset the iterator if we were at the beginning of the BB.
770761 if (AtBeginning) {
9898 // TRI->requiresFrameIndexScavenging() for the curren function.
9999 bool FrameIndexVirtualScavenging;
100100
101 // When using the scavenger post-pass to resolve frame reference
102 // materialization registers, maintain a map of the registers to
103 // the constant value and SP adjustment associated with it.
104 typedef std::pair
105 FrameConstantEntry;
106 DenseMap FrameConstantRegMap;
107
108101 #ifndef NDEBUG
109102 // Machine function handle.
110103 MachineFunction* MF;
365365 "Cannot scavenge register without an emergency spill slot!");
366366 TII->storeRegToStackSlot(*MBB, I, SReg, true, ScavengingFrameIndex, RC,TRI);
367367 MachineBasicBlock::iterator II = prior(I);
368 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
368 TRI->eliminateFrameIndex(II, SPAdj, this);
369369
370370 // Restore the scavenged register before its use (or first terminator).
371371 TII->loadRegFromStackSlot(*MBB, UseMI, SReg, ScavengingFrameIndex, RC, TRI);
372372 II = prior(UseMI);
373 TRI->eliminateFrameIndex(II, SPAdj, NULL, this);
373 TRI->eliminateFrameIndex(II, SPAdj, this);
374374 }
375375
376376 ScavengeRestore = prior(UseMI);
3939 #include "llvm/Support/CommandLine.h"
4040
4141 namespace llvm {
42 cl::opt
43 ReuseFrameIndexVals("arm-reuse-frame-index-vals", cl::Hidden, cl::init(false),
44 cl::desc("Reuse repeated frame index values"));
4542 static cl::opt
4643 ForceAllBaseRegAlloc("arm-force-base-reg-alloc", cl::Hidden, cl::init(false),
4744 cl::desc("Force use of virtual base registers for stack load/store"));
16191616 return false;
16201617 }
16211618
1622 unsigned
1619 void
16231620 ARMBaseRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
1624 int SPAdj, FrameIndexValue *Value,
1625 RegScavenger *RS) const {
1621 int SPAdj, RegScavenger *RS) const {
16261622 unsigned i = 0;
16271623 MachineInstr &MI = *II;
16281624 MachineBasicBlock &MBB = *MI.getParent();
16451641 if (MI.isDebugValue()) {
16461642 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
16471643 MI.getOperand(i+1).ChangeToImmediate(Offset);
1648 return 0;
1644 return;
16491645 }
16501646
16511647 // Modify MI as necessary to handle as much of 'Offset' as possible
16571653 Done = rewriteT2FrameIndex(MI, i, FrameReg, Offset, TII);
16581654 }
16591655 if (Done)
1660 return 0;
1656 return;
16611657
16621658 // If we get here, the immediate doesn't fit into the instruction. We folded
16631659 // as much as possible above, handle the rest, providing a register that is
16771673 MI.getOperand(i).ChangeToRegister(FrameReg, false, false, false);
16781674 else {
16791675 ScratchReg = MF.getRegInfo().createVirtualRegister(ARM::GPRRegisterClass);
1680 if (Value) {
1681 Value->first = FrameReg; // use the frame register as a kind indicator
1682 Value->second = Offset;
1683 }
16841676 if (!AFI->isThumbFunction())
16851677 emitARMRegPlusImmediate(MBB, II, MI.getDebugLoc(), ScratchReg, FrameReg,
16861678 Offset, Pred, PredReg, TII);
16901682 Offset, Pred, PredReg, TII);
16911683 }
16921684 MI.getOperand(i).ChangeToRegister(ScratchReg, false, false, true);
1693 if (!ReuseFrameIndexVals)
1694 ScratchReg = 0;
1695 }
1696 return ScratchReg;
1685 }
16971686 }
16981687
16991688 /// Move iterator past the next bunch of callee save load / store ops for
162162 MachineBasicBlock &MBB,
163163 MachineBasicBlock::iterator I) const;
164164
165 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
166 int SPAdj, FrameIndexValue *Value = NULL,
167 RegScavenger *RS = NULL) const;
165 virtual void eliminateFrameIndex(MachineBasicBlock::iterator II,
166 int SPAdj, RegScavenger *RS = NULL) const;
168167
169168 virtual void emitPrologue(MachineFunction &MF) const;
170169 virtual void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
575575 return true;
576576 }
577577
578 unsigned
578 void
579579 Thumb1RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
580 int SPAdj, FrameIndexValue *Value,
581 RegScavenger *RS) const{
580 int SPAdj, RegScavenger *RS) const {
582581 unsigned VReg = 0;
583582 unsigned i = 0;
584583 MachineInstr &MI = *II;
613612 if (MI.isDebugValue()) {
614613 MI.getOperand(i). ChangeToRegister(FrameReg, false /*isDef*/);
615614 MI.getOperand(i+1).ChangeToImmediate(Offset);
616 return 0;
615 return;
617616 }
618617
619618 // Modify MI as necessary to handle as much of 'Offset' as possible
620619 assert(AFI->isThumbFunction() &&
621620 "This eliminateFrameIndex only supports Thumb1!");
622621 if (rewriteFrameIndex(MI, i, FrameReg, Offset, TII))
623 return 0;
622 return;
624623
625624 // If we get here, the immediate doesn't fit into the instruction. We folded
626625 // as much as possible above, handle the rest, providing a register that is
661660 MI.addOperand(MachineOperand::CreateReg(0, false));
662661 } else if (Desc.mayStore()) {
663662 VReg = MF.getRegInfo().createVirtualRegister(ARM::tGPRRegisterClass);
664 assert (Value && "Frame index virtual allocated, but Value arg is NULL!");
665663 bool UseRR = false;
666 bool TrackVReg = true;
667 Value->first = FrameReg; // use the frame register as a kind indicator
668 Value->second = Offset;
669664
670665 if (Opcode == ARM::tSpill) {
671666 if (FrameReg == ARM::SP)
674669 else {
675670 emitLoadConstPool(MBB, II, dl, VReg, 0, Offset);
676671 UseRR = true;
677 TrackVReg = false;
678672 }
679673 } else
680674 emitThumbRegPlusImmediate(MBB, II, VReg, FrameReg, Offset, TII,
685679 MI.addOperand(MachineOperand::CreateReg(FrameReg, false));
686680 else // tSTR has an extra register operand.
687681 MI.addOperand(MachineOperand::CreateReg(0, false));
688 if (!ReuseFrameIndexVals || !TrackVReg)
689 VReg = 0;
690682 } else
691683 assert(false && "Unexpected opcode!");
692684
695687 MachineInstrBuilder MIB(&MI);
696688 AddDefaultPred(MIB);
697689 }
698 return VReg;
699690 }
700691
701692 void Thumb1RegisterInfo::emitPrologue(MachineFunction &MF) const {
5656 MachineBasicBlock::iterator &UseMI,
5757 const TargetRegisterClass *RC,
5858 unsigned Reg) const;
59 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
60 int SPAdj, FrameIndexValue *Value = NULL,
61 RegScavenger *RS = NULL) const;
59 void eliminateFrameIndex(MachineBasicBlock::iterator II,
60 int SPAdj, RegScavenger *RS = NULL) const;
6261
6362 void emitPrologue(MachineFunction &MF) const;
6463 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
136136 //variable locals
137137 //<- SP
138138
139 unsigned
139 void
140140 AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
141 int SPAdj, FrameIndexValue *Value,
142 RegScavenger *RS) const {
141 int SPAdj, RegScavenger *RS) const {
143142 assert(SPAdj == 0 && "Unexpected");
144143
145144 unsigned i = 0;
184183 } else {
185184 MI.getOperand(i).ChangeToImmediate(Offset);
186185 }
187 return 0;
188186 }
189187
190188
3737 MachineBasicBlock &MBB,
3838 MachineBasicBlock::iterator I) const;
3939
40 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
41 int SPAdj, FrameIndexValue *Value = NULL,
42 RegScavenger *RS = NULL) const;
40 void eliminateFrameIndex(MachineBasicBlock::iterator II,
41 int SPAdj, RegScavenger *RS = NULL) const;
4342
4443 //void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
4544
189189 return Reg;
190190 }
191191
192 unsigned
192 void
193193 BlackfinRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
194 int SPAdj, FrameIndexValue *Value,
195 RegScavenger *RS) const {
194 int SPAdj, RegScavenger *RS) const {
196195 MachineInstr &MI = *II;
197196 MachineBasicBlock &MBB = *MI.getParent();
198197 MachineFunction &MF = *MBB.getParent();
229228 MI.setDesc(TII.get(isStore
230229 ? BF::STORE32p_uimm6m4
231230 : BF::LOAD32p_uimm6m4));
232 return 0;
231 return;
233232 }
234233 if (BaseReg == BF::FP && isUInt<7>(-Offset)) {
235234 MI.setDesc(TII.get(isStore
236235 ? BF::STORE32fp_nimm7m4
237236 : BF::LOAD32fp_nimm7m4));
238237 MI.getOperand(FIPos+1).setImm(-Offset);
239 return 0;
238 return;
240239 }
241240 if (isInt<18>(Offset)) {
242241 MI.setDesc(TII.get(isStore
243242 ? BF::STORE32p_imm18m4
244243 : BF::LOAD32p_imm18m4));
245 return 0;
244 return;
246245 }
247246 // Use RegScavenger to calculate proper offset...
248247 MI.dump();
327326 llvm_unreachable("Cannot eliminate frame index");
328327 break;
329328 }
330 return 0;
331329 }
332330
333331 void BlackfinRegisterInfo::
5050 MachineBasicBlock &MBB,
5151 MachineBasicBlock::iterator I) const;
5252
53 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
54 int SPAdj, FrameIndexValue *Value = NULL,
55 RegScavenger *RS = NULL) const;
53 void eliminateFrameIndex(MachineBasicBlock::iterator II,
54 int SPAdj, RegScavenger *RS = NULL) const;
5655
5756 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
5857 RegScavenger *RS) const;
269269 MBB.erase(I);
270270 }
271271
272 unsigned
272 void
273273 SPURegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
274 FrameIndexValue *Value,
275274 RegScavenger *RS) const
276275 {
277276 unsigned i = 0;
327326 } else {
328327 MO.ChangeToImmediate(Offset);
329328 }
330 return 0;
331329 }
332330
333331 /// determineFrameLayout - Determine the size of the frame and maximum call
6262 MachineBasicBlock &MBB,
6363 MachineBasicBlock::iterator I) const;
6464 //! Convert frame indicies into machine operands
65 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
66 FrameIndexValue *Value = NULL,
67 RegScavenger *RS = NULL) const;
65 void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
66 RegScavenger *RS = NULL) const;
6867 //! Determine the frame's layour
6968 void determineFrameLayout(MachineFunction &MF) const;
7069
241241 // FrameIndex represent objects inside a abstract stack.
242242 // We must replace FrameIndex with an stack/frame pointer
243243 // direct reference.
244 unsigned MBlazeRegisterInfo::
244 void MBlazeRegisterInfo::
245245 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
246 FrameIndexValue *Value, RegScavenger *RS) const {
246 RegScavenger *RS) const {
247247 MachineInstr &MI = *II;
248248 MachineFunction &MF = *MI.getParent()->getParent();
249249
276276
277277 MI.getOperand(oi).ChangeToImmediate(Offset);
278278 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
279 return 0;
280279 }
281280
282281 void MBlazeRegisterInfo::
6262 MachineBasicBlock::iterator I) const;
6363
6464 /// Stack Frame Processing Methods
65 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
66 int SPAdj, FrameIndexValue *Value = NULL,
67 RegScavenger *RS = NULL) const;
65 void eliminateFrameIndex(MachineBasicBlock::iterator II,
66 int SPAdj, RegScavenger *RS = NULL) const;
6867
6968 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
7069
162162 MBB.erase(I);
163163 }
164164
165 unsigned
165 void
166166 MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
167 int SPAdj, FrameIndexValue *Value,
168 RegScavenger *RS) const {
167 int SPAdj, RegScavenger *RS) const {
169168 assert(SPAdj == 0 && "Unexpected");
170169
171170 unsigned i = 0;
203202 MI.getOperand(i).ChangeToRegister(BasePtr, false);
204203
205204 if (Offset == 0)
206 return 0;
205 return;
207206
208207 // We need to materialize the offset via add instruction.
209208 unsigned DstReg = MI.getOperand(0).getReg();
214213 BuildMI(MBB, llvm::next(II), dl, TII.get(MSP430::ADD16ri), DstReg)
215214 .addReg(DstReg).addImm(Offset);
216215
217 return 0;
216 return;
218217 }
219218
220219 MI.getOperand(i).ChangeToRegister(BasePtr, false);
221220 MI.getOperand(i+1).ChangeToImmediate(Offset);
222 return 0;
223221 }
224222
225223 void
4545 MachineBasicBlock &MBB,
4646 MachineBasicBlock::iterator I) const;
4747
48 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
49 int SPAdj, FrameIndexValue *Value = NULL,
50 RegScavenger *RS = NULL) const;
48 void eliminateFrameIndex(MachineBasicBlock::iterator II,
49 int SPAdj, RegScavenger *RS = NULL) const;
5150
5251 void emitPrologue(MachineFunction &MF) const;
5352 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
326326 // FrameIndex represent objects inside a abstract stack.
327327 // We must replace FrameIndex with an stack/frame pointer
328328 // direct reference.
329 unsigned MipsRegisterInfo::
329 void MipsRegisterInfo::
330330 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
331 FrameIndexValue *Value, RegScavenger *RS) const
332 {
331 RegScavenger *RS) const {
333332 MachineInstr &MI = *II;
334333 MachineFunction &MF = *MI.getParent()->getParent();
335334
360359
361360 MI.getOperand(i-1).ChangeToImmediate(Offset);
362361 MI.getOperand(i).ChangeToRegister(getFrameRegister(MF), false);
363 return 0;
364362 }
365363
366364 void MipsRegisterInfo::
5050 MachineBasicBlock::iterator I) const;
5151
5252 /// Stack Frame Processing Methods
53 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
54 int SPAdj, FrameIndexValue *Value = NULL,
55 RegScavenger *RS = NULL) const;
53 void eliminateFrameIndex(MachineBasicBlock::iterator II,
54 int SPAdj, RegScavenger *RS = NULL) const;
5655
5756 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
5857
4343 return false;
4444 }
4545
46 unsigned PIC16RegisterInfo::
46 void PIC16RegisterInfo::
4747 eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
48 FrameIndexValue *Value, RegScavenger *RS) const
49 {
50 /* NOT YET IMPLEMENTED */
51 return 0;
52 }
48 RegScavenger *RS) const
49 { /* NOT YET IMPLEMENTED */ }
5350
5451 void PIC16RegisterInfo::emitPrologue(MachineFunction &MF) const
5552 { /* NOT YET IMPLEMENTED */ }
4343 virtual BitVector getReservedRegs(const MachineFunction &MF) const;
4444 virtual bool hasFP(const MachineFunction &MF) const;
4545
46 virtual unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
47 int SPAdj, FrameIndexValue *Value = NULL,
48 RegScavenger *RS=NULL) const;
46 virtual void eliminateFrameIndex(MachineBasicBlock::iterator MI,
47 int SPAdj, RegScavenger *RS=NULL) const;
4948
5049 void eliminateCallFramePseudoInstr(MachineFunction &MF,
5150 MachineBasicBlock &MBB,
579579 MBB.erase(II);
580580 }
581581
582 unsigned
582 void
583583 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
584 int SPAdj, FrameIndexValue *Value,
585 RegScavenger *RS) const {
584 int SPAdj, RegScavenger *RS) const {
586585 assert(SPAdj == 0 && "Unexpected");
587586
588587 // Get the instruction.
621620 if (FPSI && FrameIndex == FPSI &&
622621 (OpC == PPC::DYNALLOC || OpC == PPC::DYNALLOC8)) {
623622 lowerDynamicAlloc(II, SPAdj, RS);
624 return 0;
623 return;
625624 }
626625
627626 // Special case for pseudo-op SPILL_CR.
628627 if (EnableRegisterScavenging) // FIXME (64-bit): Enable by default.
629628 if (OpC == PPC::SPILL_CR) {
630629 lowerCRSpilling(II, FrameIndex, SPAdj, RS);
631 return 0;
630 return;
632631 }
633632
634633 // Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
673672 if (isIXAddr)
674673 Offset >>= 2; // The actual encoded value has the low two bits zero.
675674 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
676 return 0;
675 return;
677676 }
678677
679678 // The offset doesn't fit into a single register, scavenge one to build the
709708 } else {
710709 OperandBase = OffsetOperandNo;
711710 }
712
711
713712 unsigned StackReg = MI.getOperand(FIOperandNo).getReg();
714713 MI.getOperand(OperandBase).ChangeToRegister(StackReg, false);
715714 MI.getOperand(OperandBase + 1).ChangeToRegister(SReg, false);
716 return 0;
717715 }
718716
719717 /// VRRegNo - Map from a numbered VR register to its enum value.
6262 int SPAdj, RegScavenger *RS) const;
6363 void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex,
6464 int SPAdj, RegScavenger *RS) const;
65 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
66 int SPAdj, FrameIndexValue *Value = NULL,
67 RegScavenger *RS = NULL) const;
65 void eliminateFrameIndex(MachineBasicBlock::iterator II,
66 int SPAdj, RegScavenger *RS = NULL) const;
6867
6968 /// determineFrameLayout - Determine the size of the frame and maximum call
7069 /// frame size.
6868 MBB.erase(I);
6969 }
7070
71 unsigned
71 void
7272 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
73 int SPAdj, FrameIndexValue *Value,
74 RegScavenger *RS) const {
73 int SPAdj, RegScavenger *RS) const {
7574 assert(SPAdj == 0 && "Unexpected");
7675
7776 unsigned i = 0;
107106 MI.getOperand(i).ChangeToRegister(SP::G1, false);
108107 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
109108 }
110 return 0;
111109 }
112110
113111 void SparcRegisterInfo::
3939 MachineBasicBlock &MBB,
4040 MachineBasicBlock::iterator I) const;
4141
42 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
43 int SPAdj, FrameIndexValue *Value = NULL,
44 RegScavenger *RS = NULL) const;
42 void eliminateFrameIndex(MachineBasicBlock::iterator II,
43 int SPAdj, RegScavenger *RS = NULL) const;
4544
4645 void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
4746
9191 return Offset;
9292 }
9393
94 unsigned
94 void
9595 SystemZRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
96 int SPAdj, FrameIndexValue *Value,
97 RegScavenger *RS) const {
96 int SPAdj, RegScavenger *RS) const {
9897 assert(SPAdj == 0 && "Unxpected");
9998
10099 unsigned i = 0;
116115
117116 // Offset is a either 12-bit unsigned or 20-bit signed integer.
118117 // FIXME: handle "too long" displacements.
119 int Offset = getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
118 int Offset =
119 getFrameIndexOffset(MF, FrameIndex) + MI.getOperand(i+1).getImm();
120120
121121 // Check whether displacement is too long to fit into 12 bit zext field.
122122 MI.setDesc(TII.getMemoryInstr(MI.getOpcode(), Offset));
123123
124124 MI.getOperand(i+1).ChangeToImmediate(Offset);
125 return 0;
126125 }
127126
128127 void
4242 MachineBasicBlock &MBB,
4343 MachineBasicBlock::iterator I) const;
4444
45 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
46 int SPAdj, FrameIndexValue *Value = NULL,
47 RegScavenger *RS = NULL) const;
45 void eliminateFrameIndex(MachineBasicBlock::iterator II,
46 int SPAdj, RegScavenger *RS = NULL) const;
4847
4948
5049 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
625625 MBB.erase(I);
626626 }
627627
628 unsigned
628 void
629629 X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
630 int SPAdj, FrameIndexValue *Value,
631 RegScavenger *RS) const{
630 int SPAdj, RegScavenger *RS) const{
632631 assert(SPAdj == 0 && "Unexpected");
633632
634633 unsigned i = 0;
675674 uint64_t Offset = FIOffset + (uint64_t)MI.getOperand(i+3).getOffset();
676675 MI.getOperand(i+3).setOffset(Offset);
677676 }
678 return 0;
679677 }
680678
681679 void
125125 MachineBasicBlock &MBB,
126126 MachineBasicBlock::iterator MI) const;
127127
128 unsigned eliminateFrameIndex(MachineBasicBlock::iterator MI,
129 int SPAdj, FrameIndexValue *Value = NULL,
130 RegScavenger *RS = NULL) const;
128 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
129 int SPAdj, RegScavenger *RS = NULL) const;
131130
132131 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
133132 RegScavenger *RS = NULL) const;
154154 MBB.erase(I);
155155 }
156156
157 unsigned
157 void
158158 XCoreRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
159 int SPAdj, FrameIndexValue *Value,
160 RegScavenger *RS) const {
159 int SPAdj, RegScavenger *RS) const {
161160 assert(SPAdj == 0 && "Unexpected");
162161 MachineInstr &MI = *II;
163162 DebugLoc dl = MI.getDebugLoc();
290289 }
291290 // Erase old instruction.
292291 MBB.erase(II);
293 return 0;
294292 }
295293
296294 void
5353 MachineBasicBlock &MBB,
5454 MachineBasicBlock::iterator I) const;
5555
56 unsigned eliminateFrameIndex(MachineBasicBlock::iterator II,
57 int SPAdj, FrameIndexValue *Value = NULL,
58 RegScavenger *RS = NULL) const;
56 void eliminateFrameIndex(MachineBasicBlock::iterator II,
57 int SPAdj, RegScavenger *RS = NULL) const;
5958
6059 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
6160 RegScavenger *RS = NULL) const;