llvm.org GIT mirror llvm / fc72762
[msan] Handle X86 *.psad.* and *.pmadd.* intrinsics. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@211156 91177308-0d34-0410-b5e6-96231b3b80d8 Evgeniy Stepanov 5 years ago
2 changed file(s) with 120 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
20552055
20562056 Value *S = IRB.CreateCall2(ShadowFn, S1_ext, S2_ext, "_msprop_vector_pack");
20572057 if (isX86_MMX) S = IRB.CreateBitCast(S, getShadowTy(&I));
2058 setShadow(&I, S);
2059 setOriginForNaryOp(I);
2060 }
2061
2062 // \brief Instrument sum-of-absolute-differencies intrinsic.
2063 void handleVectorSadIntrinsic(IntrinsicInst &I) {
2064 const unsigned SignificantBitsPerResultElement = 16;
2065 bool isX86_MMX = I.getOperand(0)->getType()->isX86_MMXTy();
2066 Type *ResTy = isX86_MMX ? IntegerType::get(*MS.C, 64) : I.getType();
2067 unsigned ZeroBitsPerResultElement =
2068 ResTy->getScalarSizeInBits() - SignificantBitsPerResultElement;
2069
2070 IRBuilder<> IRB(&I);
2071 Value *S = IRB.CreateOr(getShadow(&I, 0), getShadow(&I, 1));
2072 S = IRB.CreateBitCast(S, ResTy);
2073 S = IRB.CreateSExt(IRB.CreateICmpNE(S, Constant::getNullValue(ResTy)),
2074 ResTy);
2075 S = IRB.CreateLShr(S, ZeroBitsPerResultElement);
2076 S = IRB.CreateBitCast(S, getShadowTy(&I));
2077 setShadow(&I, S);
2078 setOriginForNaryOp(I);
2079 }
2080
2081 // \brief Instrument multiply-add intrinsic.
2082 void handleVectorPmaddIntrinsic(IntrinsicInst &I,
2083 unsigned EltSizeInBits = 0) {
2084 bool isX86_MMX = I.getOperand(0)->getType()->isX86_MMXTy();
2085 Type *ResTy = isX86_MMX ? getMMXVectorTy(EltSizeInBits * 2) : I.getType();
2086 IRBuilder<> IRB(&I);
2087 Value *S = IRB.CreateOr(getShadow(&I, 0), getShadow(&I, 1));
2088 S = IRB.CreateBitCast(S, ResTy);
2089 S = IRB.CreateSExt(IRB.CreateICmpNE(S, Constant::getNullValue(ResTy)),
2090 ResTy);
2091 S = IRB.CreateBitCast(S, getShadowTy(&I));
20582092 setShadow(&I, S);
20592093 setOriginForNaryOp(I);
20602094 }
21952229 handleVectorPackIntrinsic(I, 32);
21962230 break;
21972231
2232 case llvm::Intrinsic::x86_mmx_psad_bw:
2233 case llvm::Intrinsic::x86_sse2_psad_bw:
2234 case llvm::Intrinsic::x86_avx2_psad_bw:
2235 handleVectorSadIntrinsic(I);
2236 break;
2237
2238 case llvm::Intrinsic::x86_sse2_pmadd_wd:
2239 case llvm::Intrinsic::x86_avx2_pmadd_wd:
2240 case llvm::Intrinsic::x86_ssse3_pmadd_ub_sw_128:
2241 case llvm::Intrinsic::x86_avx2_pmadd_ub_sw:
2242 handleVectorPmaddIntrinsic(I);
2243 break;
2244
2245 case llvm::Intrinsic::x86_ssse3_pmadd_ub_sw:
2246 handleVectorPmaddIntrinsic(I, 8);
2247 break;
2248
2249 case llvm::Intrinsic::x86_mmx_pmadd_wd:
2250 handleVectorPmaddIntrinsic(I, 16);
2251 break;
2252
21982253 default:
21992254 if (!handleUnknownIntrinsic(I))
22002255 visitInstruction(I);
0 ; RUN: opt < %s -msan -msan-check-access-address=0 -S | FileCheck %s
1
2 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
3 target triple = "x86_64-unknown-linux-gnu"
4
5 declare <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16>, <8 x i16>) nounwind readnone
6 declare x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx, x86_mmx) nounwind readnone
7 declare <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8>, <16 x i8>) nounwind readnone
8 declare x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx, x86_mmx) nounwind readnone
9
10 define <4 x i32> @Test_sse2_pmadd_wd(<8 x i16> %a, <8 x i16> %b) sanitize_memory {
11 entry:
12 %c = tail call <4 x i32> @llvm.x86.sse2.pmadd.wd(<8 x i16> %a, <8 x i16> %b) nounwind
13 ret <4 x i32> %c
14 }
15
16 ; CHECK-LABEL: @Test_sse2_pmadd_wd(
17 ; CHECK: or <8 x i16>
18 ; CHECK: bitcast <8 x i16> {{.*}} to <4 x i32>
19 ; CHECK: icmp ne <4 x i32> {{.*}}, zeroinitializer
20 ; CHECK: sext <4 x i1> {{.*}} to <4 x i32>
21 ; CHECK: ret <4 x i32>
22
23
24 define x86_mmx @Test_ssse3_pmadd_ub_sw(x86_mmx %a, x86_mmx %b) sanitize_memory {
25 entry:
26 %c = tail call x86_mmx @llvm.x86.ssse3.pmadd.ub.sw(x86_mmx %a, x86_mmx %b) nounwind
27 ret x86_mmx %c
28 }
29
30 ; CHECK-LABEL: @Test_ssse3_pmadd_ub_sw(
31 ; CHECK: or i64
32 ; CHECK: bitcast i64 {{.*}} to <4 x i16>
33 ; CHECK: icmp ne <4 x i16> {{.*}}, zeroinitializer
34 ; CHECK: sext <4 x i1> {{.*}} to <4 x i16>
35 ; CHECK: bitcast <4 x i16> {{.*}} to i64
36 ; CHECK: ret x86_mmx
37
38
39 define <2 x i64> @Test_x86_sse2_psad_bw(<16 x i8> %a, <16 x i8> %b) sanitize_memory {
40 %c = tail call <2 x i64> @llvm.x86.sse2.psad.bw(<16 x i8> %a, <16 x i8> %b)
41 ret <2 x i64> %c
42 }
43
44 ; CHECK-LABEL: @Test_x86_sse2_psad_bw(
45 ; CHECK: or <16 x i8> {{.*}}, {{.*}}
46 ; CHECK: bitcast <16 x i8> {{.*}} to <2 x i64>
47 ; CHECK: icmp ne <2 x i64> {{.*}}, zeroinitializer
48 ; CHECK: sext <2 x i1> {{.*}} to <2 x i64>
49 ; CHECK: lshr <2 x i64> {{.*}},
50 ; CHECK: ret <2 x i64>
51
52
53 define x86_mmx @Test_x86_mmx_psad_bw(x86_mmx %a, x86_mmx %b) sanitize_memory {
54 entry:
55 %c = tail call x86_mmx @llvm.x86.mmx.psad.bw(x86_mmx %a, x86_mmx %b) nounwind
56 ret x86_mmx %c
57 }
58
59 ; CHECK-LABEL: @Test_x86_mmx_psad_bw(
60 ; CHECK: or i64
61 ; CHECK: icmp ne i64
62 ; CHECK: sext i1 {{.*}} to i64
63 ; CHECK: lshr i64 {{.*}}, 48
64 ; CHECK: ret x86_mmx