llvm.org GIT mirror llvm / fc1a161
Switch the fixed-length disassembler to be table-driven. Refactor the TableGen'erated fixed length disassemblmer to use a table-driven state machine rather than a massive set of nested switch() statements. As a result, the ARM Disassembler (ARMDisassembler.cpp) builds much more quickly and generates a smaller end result. For a Release+Asserts build on a 16GB 3.4GHz i7 iMac w/ SSD: Time to compile at -O2 (averaged w/ hot caches): Previous: 35.5s New: 8.9s TEXT size: Previous: 447,251 New: 297,661 Builds in 25% of the time previously required and generates code 66% of the size. Execution time of the disassembler is only slightly slower (7% disassembling 10 million ARM instructions, 19.6s vs 21.0s). The new implementation has not yet been tuned, however, so the performance should almost certainly be recoverable should it become a concern. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161888 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 7 years ago
5 changed file(s) with 1252 addition(s) and 724 deletion(s). Raw diff Collapse all Expand all
0 //===-- llvm/MC/MCFixedLenDisassembler.h - Decoder driver -------*- C++ -*-===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 // Fixed length disassembler decoder state machine driver.
9 //===----------------------------------------------------------------------===//
10 #ifndef MCFIXEDLENDISASSEMBLER_H
11 #define MCFIXEDLENDISASSEMBLER_H
12
13 namespace llvm {
14
15 namespace MCD {
16 // Disassembler state machine opcodes.
17 enum DecoderOps {
18 OPC_ExtractField = 1, // OPC_ExtractField(uint8_t Start, uint8_t Len)
19 OPC_FilterValue, // OPC_FilterValue(uleb128 Val, uint16_t NumToSkip)
20 OPC_CheckField, // OPC_CheckField(uint8_t Start, uint8_t Len,
21 // uleb128 Val, uint16_t NumToSkip)
22 OPC_CheckPredicate, // OPC_CheckPredicate(uleb128 PIdx, uint16_t NumToSkip)
23 OPC_Decode, // OPC_Decode(uleb128 Opcode, uleb128 DIdx)
24 OPC_SoftFail, // OPC_SoftFail(uleb128 PMask, uleb128 NMask)
25 OPC_Fail // OPC_Fail()
26 };
27
28 } // namespace MCDecode
29 } // namespace llvm
30
31 #endif
1818
1919 namespace llvm {
2020
21 /// Utility function to encode a SLEB128 value.
21 /// Utility function to encode a SLEB128 value to an output stream.
2222 static inline void encodeSLEB128(int64_t Value, raw_ostream &OS) {
2323 bool More;
2424 do {
3333 } while (More);
3434 }
3535
36 /// Utility function to encode a ULEB128 value.
36 /// Utility function to encode a ULEB128 value to an output stream.
3737 static inline void encodeULEB128(uint64_t Value, raw_ostream &OS,
3838 unsigned Padding = 0) {
3939 do {
5252 }
5353 }
5454
55 /// Utility function to encode a ULEB128 value to a buffer. Returns
56 /// the length in bytes of the encoded value.
57 static inline unsigned encodeULEB128(uint64_t Value, uint8_t *p,
58 unsigned Padding = 0) {
59 uint8_t *orig_p = p;
60 do {
61 uint8_t Byte = Value & 0x7f;
62 Value >>= 7;
63 if (Value != 0 || Padding != 0)
64 Byte |= 0x80; // Mark this byte that that more bytes will follow.
65 *p++ = Byte;
66 } while (Value != 0);
67
68 // Pad with 0x80 and emit a null byte at the end.
69 if (Padding != 0) {
70 for (; Padding != 1; --Padding)
71 *p++ = '\x80';
72 *p++ = '\x00';
73 }
74 return (unsigned)(p - orig_p);
75 }
76
77
78 /// Utility function to decode a ULEB128 value.
79 static inline uint64_t decodeULEB128(const uint8_t *p, unsigned *n = 0) {
80 const uint8_t *orig_p = p;
81 uint64_t Value = 0;
82 unsigned Shift = 0;
83 do {
84 Value += (*p & 0x7f) << Shift;
85 Shift += 7;
86 } while (*p++ >= 128);
87 if (n)
88 *n = (unsigned)(p - orig_p);
89 return Value;
90 }
91
5592 } // namespace llvm
5693
5794 #endif // LLVM_SYSTEM_LEB128_H
1717 #include "llvm/MC/MCExpr.h"
1818 #include "llvm/MC/MCContext.h"
1919 #include "llvm/MC/MCDisassembler.h"
20 #include "llvm/MC/MCFixedLenDisassembler.h"
2021 #include "llvm/MC/MCSubtargetInfo.h"
2122 #include "llvm/Support/Debug.h"
2223 #include "llvm/Support/MemoryObject.h"
2324 #include "llvm/Support/ErrorHandling.h"
25 #include "llvm/Support/LEB128.h"
2426 #include "llvm/Support/TargetRegistry.h"
2527 #include "llvm/Support/raw_ostream.h"
2628 #include
426428 (bytes[0] << 0);
427429
428430 // Calling the auto-generated decoder function.
429 DecodeStatus result = decodeARMInstruction32(MI, insn, Address, this, STI);
431 DecodeStatus result = decodeInstruction(DecoderTableARM32, MI, insn,
432 Address, this, STI);
430433 if (result != MCDisassembler::Fail) {
431434 Size = 4;
432435 return result;
435438 // VFP and NEON instructions, similarly, are shared between ARM
436439 // and Thumb modes.
437440 MI.clear();
438 result = decodeVFPInstruction32(MI, insn, Address, this, STI);
441 result = decodeInstruction(DecoderTableVFP32, MI, insn, Address, this, STI);
439442 if (result != MCDisassembler::Fail) {
440443 Size = 4;
441444 return result;
442445 }
443446
444447 MI.clear();
445 result = decodeNEONDataInstruction32(MI, insn, Address, this, STI);
448 result = decodeInstruction(DecoderTableNEONData32, MI, insn, Address,
449 this, STI);
446450 if (result != MCDisassembler::Fail) {
447451 Size = 4;
448452 // Add a fake predicate operand, because we share these instruction
453457 }
454458
455459 MI.clear();
456 result = decodeNEONLoadStoreInstruction32(MI, insn, Address, this, STI);
460 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, insn, Address,
461 this, STI);
457462 if (result != MCDisassembler::Fail) {
458463 Size = 4;
459464 // Add a fake predicate operand, because we share these instruction
464469 }
465470
466471 MI.clear();
467 result = decodeNEONDupInstruction32(MI, insn, Address, this, STI);
472 result = decodeInstruction(DecoderTableNEONDup32, MI, insn, Address,
473 this, STI);
468474 if (result != MCDisassembler::Fail) {
469475 Size = 4;
470476 // Add a fake predicate operand, because we share these instruction
764770 }
765771
766772 uint16_t insn16 = (bytes[1] << 8) | bytes[0];
767 DecodeStatus result = decodeThumbInstruction16(MI, insn16, Address, this, STI);
773 DecodeStatus result = decodeInstruction(DecoderTableThumb16, MI, insn16,
774 Address, this, STI);
768775 if (result != MCDisassembler::Fail) {
769776 Size = 2;
770777 Check(result, AddThumbPredicate(MI));
772779 }
773780
774781 MI.clear();
775 result = decodeThumbSBitInstruction16(MI, insn16, Address, this, STI);
782 result = decodeInstruction(DecoderTableThumbSBit16, MI, insn16,
783 Address, this, STI);
776784 if (result) {
777785 Size = 2;
778786 bool InITBlock = ITBlock.instrInITBlock();
782790 }
783791
784792 MI.clear();
785 result = decodeThumb2Instruction16(MI, insn16, Address, this, STI);
793 result = decodeInstruction(DecoderTableThumb216, MI, insn16,
794 Address, this, STI);
786795 if (result != MCDisassembler::Fail) {
787796 Size = 2;
788797
817826 (bytes[1] << 24) |
818827 (bytes[0] << 16);
819828 MI.clear();
820 result = decodeThumbInstruction32(MI, insn32, Address, this, STI);
829 result = decodeInstruction(DecoderTableThumb32, MI, insn32, Address,
830 this, STI);
821831 if (result != MCDisassembler::Fail) {
822832 Size = 4;
823833 bool InITBlock = ITBlock.instrInITBlock();
827837 }
828838
829839 MI.clear();
830 result = decodeThumb2Instruction32(MI, insn32, Address, this, STI);
840 result = decodeInstruction(DecoderTableThumb232, MI, insn32, Address,
841 this, STI);
831842 if (result != MCDisassembler::Fail) {
832843 Size = 4;
833844 Check(result, AddThumbPredicate(MI));
835846 }
836847
837848 MI.clear();
838 result = decodeVFPInstruction32(MI, insn32, Address, this, STI);
849 result = decodeInstruction(DecoderTableVFP32, MI, insn32, Address, this, STI);
839850 if (result != MCDisassembler::Fail) {
840851 Size = 4;
841852 UpdateThumbVFPPredicate(MI);
843854 }
844855
845856 MI.clear();
846 result = decodeNEONDupInstruction32(MI, insn32, Address, this, STI);
857 result = decodeInstruction(DecoderTableNEONDup32, MI, insn32, Address,
858 this, STI);
847859 if (result != MCDisassembler::Fail) {
848860 Size = 4;
849861 Check(result, AddThumbPredicate(MI));
850862 return result;
851863 }
852864
853 if (fieldFromInstruction32(insn32, 24, 8) == 0xF9) {
865 if (fieldFromInstruction(insn32, 24, 8) == 0xF9) {
854866 MI.clear();
855867 uint32_t NEONLdStInsn = insn32;
856868 NEONLdStInsn &= 0xF0FFFFFF;
857869 NEONLdStInsn |= 0x04000000;
858 result = decodeNEONLoadStoreInstruction32(MI, NEONLdStInsn, Address, this, STI);
870 result = decodeInstruction(DecoderTableNEONLoadStore32, MI, NEONLdStInsn,
871 Address, this, STI);
859872 if (result != MCDisassembler::Fail) {
860873 Size = 4;
861874 Check(result, AddThumbPredicate(MI));
863876 }
864877 }
865878
866 if (fieldFromInstruction32(insn32, 24, 4) == 0xF) {
879 if (fieldFromInstruction(insn32, 24, 4) == 0xF) {
867880 MI.clear();
868881 uint32_t NEONDataInsn = insn32;
869882 NEONDataInsn &= 0xF0FFFFFF; // Clear bits 27-24
870883 NEONDataInsn |= (NEONDataInsn & 0x10000000) >> 4; // Move bit 28 to bit 24
871884 NEONDataInsn |= 0x12000000; // Set bits 28 and 25
872 result = decodeNEONDataInstruction32(MI, NEONDataInsn, Address, this, STI);
885 result = decodeInstruction(DecoderTableNEONData32, MI, NEONDataInsn,
886 Address, this, STI);
873887 if (result != MCDisassembler::Fail) {
874888 Size = 4;
875889 Check(result, AddThumbPredicate(MI));
11161130 uint64_t Address, const void *Decoder) {
11171131 DecodeStatus S = MCDisassembler::Success;
11181132
1119 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1120 unsigned type = fieldFromInstruction32(Val, 5, 2);
1121 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1133 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1134 unsigned type = fieldFromInstruction(Val, 5, 2);
1135 unsigned imm = fieldFromInstruction(Val, 7, 5);
11221136
11231137 // Register-immediate
11241138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
11531167 uint64_t Address, const void *Decoder) {
11541168 DecodeStatus S = MCDisassembler::Success;
11551169
1156 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1157 unsigned type = fieldFromInstruction32(Val, 5, 2);
1158 unsigned Rs = fieldFromInstruction32(Val, 8, 4);
1170 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1171 unsigned type = fieldFromInstruction(Val, 5, 2);
1172 unsigned Rs = fieldFromInstruction(Val, 8, 4);
11591173
11601174 // Register-register
11611175 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
12231237 uint64_t Address, const void *Decoder) {
12241238 DecodeStatus S = MCDisassembler::Success;
12251239
1226 unsigned Vd = fieldFromInstruction32(Val, 8, 5);
1227 unsigned regs = fieldFromInstruction32(Val, 0, 8);
1240 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1241 unsigned regs = fieldFromInstruction(Val, 0, 8);
12281242
12291243 if (!Check(S, DecodeSPRRegisterClass(Inst, Vd, Address, Decoder)))
12301244 return MCDisassembler::Fail;
12401254 uint64_t Address, const void *Decoder) {
12411255 DecodeStatus S = MCDisassembler::Success;
12421256
1243 unsigned Vd = fieldFromInstruction32(Val, 8, 5);
1244 unsigned regs = fieldFromInstruction32(Val, 0, 8);
1257 unsigned Vd = fieldFromInstruction(Val, 8, 5);
1258 unsigned regs = fieldFromInstruction(Val, 0, 8);
12451259
12461260 regs = regs >> 1;
12471261
12621276 // the mask of all bits LSB-and-lower, and then xor them to create
12631277 // the mask of that's all ones on [msb, lsb]. Finally we not it to
12641278 // create the final mask.
1265 unsigned msb = fieldFromInstruction32(Val, 5, 5);
1266 unsigned lsb = fieldFromInstruction32(Val, 0, 5);
1279 unsigned msb = fieldFromInstruction(Val, 5, 5);
1280 unsigned lsb = fieldFromInstruction(Val, 0, 5);
12671281
12681282 DecodeStatus S = MCDisassembler::Success;
12691283 if (lsb > msb) Check(S, MCDisassembler::SoftFail);
12801294 uint64_t Address, const void *Decoder) {
12811295 DecodeStatus S = MCDisassembler::Success;
12821296
1283 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1284 unsigned CRd = fieldFromInstruction32(Insn, 12, 4);
1285 unsigned coproc = fieldFromInstruction32(Insn, 8, 4);
1286 unsigned imm = fieldFromInstruction32(Insn, 0, 8);
1287 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1288 unsigned U = fieldFromInstruction32(Insn, 23, 1);
1297 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1298 unsigned CRd = fieldFromInstruction(Insn, 12, 4);
1299 unsigned coproc = fieldFromInstruction(Insn, 8, 4);
1300 unsigned imm = fieldFromInstruction(Insn, 0, 8);
1301 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1302 unsigned U = fieldFromInstruction(Insn, 23, 1);
12891303
12901304 switch (Inst.getOpcode()) {
12911305 case ARM::LDC_OFFSET:
14251439 uint64_t Address, const void *Decoder) {
14261440 DecodeStatus S = MCDisassembler::Success;
14271441
1428 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1429 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1430 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1431 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
1432 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1433 unsigned reg = fieldFromInstruction32(Insn, 25, 1);
1434 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1435 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1442 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1443 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1444 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1445 unsigned imm = fieldFromInstruction(Insn, 0, 12);
1446 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1447 unsigned reg = fieldFromInstruction(Insn, 25, 1);
1448 unsigned P = fieldFromInstruction(Insn, 24, 1);
1449 unsigned W = fieldFromInstruction(Insn, 21, 1);
14361450
14371451 // On stores, the writeback operand precedes Rt.
14381452 switch (Inst.getOpcode()) {
14751489 return MCDisassembler::Fail;
14761490
14771491 ARM_AM::AddrOpc Op = ARM_AM::add;
1478 if (!fieldFromInstruction32(Insn, 23, 1))
1492 if (!fieldFromInstruction(Insn, 23, 1))
14791493 Op = ARM_AM::sub;
14801494
14811495 bool writeback = (P == 0) || (W == 1);
14921506 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
14931507 return MCDisassembler::Fail;
14941508 ARM_AM::ShiftOpc Opc = ARM_AM::lsl;
1495 switch( fieldFromInstruction32(Insn, 5, 2)) {
1509 switch( fieldFromInstruction(Insn, 5, 2)) {
14961510 case 0:
14971511 Opc = ARM_AM::lsl;
14981512 break;
15081522 default:
15091523 return MCDisassembler::Fail;
15101524 }
1511 unsigned amt = fieldFromInstruction32(Insn, 7, 5);
1525 unsigned amt = fieldFromInstruction(Insn, 7, 5);
15121526 unsigned imm = ARM_AM::getAM2Opc(Op, amt, Opc, idx_mode);
15131527
15141528 Inst.addOperand(MCOperand::CreateImm(imm));
15281542 uint64_t Address, const void *Decoder) {
15291543 DecodeStatus S = MCDisassembler::Success;
15301544
1531 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
1532 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
1533 unsigned type = fieldFromInstruction32(Val, 5, 2);
1534 unsigned imm = fieldFromInstruction32(Val, 7, 5);
1535 unsigned U = fieldFromInstruction32(Val, 12, 1);
1545 unsigned Rn = fieldFromInstruction(Val, 13, 4);
1546 unsigned Rm = fieldFromInstruction(Val, 0, 4);
1547 unsigned type = fieldFromInstruction(Val, 5, 2);
1548 unsigned imm = fieldFromInstruction(Val, 7, 5);
1549 unsigned U = fieldFromInstruction(Val, 12, 1);
15361550
15371551 ARM_AM::ShiftOpc ShOp = ARM_AM::lsl;
15381552 switch (type) {
15691583 uint64_t Address, const void *Decoder) {
15701584 DecodeStatus S = MCDisassembler::Success;
15711585
1572 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
1573 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1574 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
1575 unsigned type = fieldFromInstruction32(Insn, 22, 1);
1576 unsigned imm = fieldFromInstruction32(Insn, 8, 4);
1577 unsigned U = ((~fieldFromInstruction32(Insn, 23, 1)) & 1) << 8;
1578 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1579 unsigned W = fieldFromInstruction32(Insn, 21, 1);
1580 unsigned P = fieldFromInstruction32(Insn, 24, 1);
1586 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
1587 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1588 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
1589 unsigned type = fieldFromInstruction(Insn, 22, 1);
1590 unsigned imm = fieldFromInstruction(Insn, 8, 4);
1591 unsigned U = ((~fieldFromInstruction(Insn, 23, 1)) & 1) << 8;
1592 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1593 unsigned W = fieldFromInstruction(Insn, 21, 1);
1594 unsigned P = fieldFromInstruction(Insn, 24, 1);
15811595 unsigned Rt2 = Rt + 1;
15821596
15831597 bool writeback = (W == 1) | (P == 0);
16081622 S = MCDisassembler::SoftFail;
16091623 if (Rt2 == 15)
16101624 S = MCDisassembler::SoftFail;
1611 if (!type && fieldFromInstruction32(Insn, 8, 4))
1625 if (!type && fieldFromInstruction(Insn, 8, 4))
16121626 S = MCDisassembler::SoftFail;
16131627 break;
16141628 case ARM::STRH:
17601774 uint64_t Address, const void *Decoder) {
17611775 DecodeStatus S = MCDisassembler::Success;
17621776
1763 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1764 unsigned mode = fieldFromInstruction32(Insn, 23, 2);
1777 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1778 unsigned mode = fieldFromInstruction(Insn, 23, 2);
17651779
17661780 switch (mode) {
17671781 case 0:
17901804 uint64_t Address, const void *Decoder) {
17911805 DecodeStatus S = MCDisassembler::Success;
17921806
1793 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
1794 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1795 unsigned reglist = fieldFromInstruction32(Insn, 0, 16);
1807 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
1808 unsigned pred = fieldFromInstruction(Insn, 28, 4);
1809 unsigned reglist = fieldFromInstruction(Insn, 0, 16);
17961810
17971811 if (pred == 0xF) {
17981812 switch (Inst.getOpcode()) {
18491863 }
18501864
18511865 // For stores (which become SRS's, the only operand is the mode.
1852 if (fieldFromInstruction32(Insn, 20, 1) == 0) {
1866 if (fieldFromInstruction(Insn, 20, 1) == 0) {
18531867 Inst.addOperand(
1854 MCOperand::CreateImm(fieldFromInstruction32(Insn, 0, 4)));
1868 MCOperand::CreateImm(fieldFromInstruction(Insn, 0, 4)));
18551869 return S;
18561870 }
18571871
18721886
18731887 static DecodeStatus DecodeCPSInstruction(MCInst &Inst, unsigned Insn,
18741888 uint64_t Address, const void *Decoder) {
1875 unsigned imod = fieldFromInstruction32(Insn, 18, 2);
1876 unsigned M = fieldFromInstruction32(Insn, 17, 1);
1877 unsigned iflags = fieldFromInstruction32(Insn, 6, 3);
1878 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1889 unsigned imod = fieldFromInstruction(Insn, 18, 2);
1890 unsigned M = fieldFromInstruction(Insn, 17, 1);
1891 unsigned iflags = fieldFromInstruction(Insn, 6, 3);
1892 unsigned mode = fieldFromInstruction(Insn, 0, 5);
18791893
18801894 DecodeStatus S = MCDisassembler::Success;
18811895
19121926
19131927 static DecodeStatus DecodeT2CPSInstruction(MCInst &Inst, unsigned Insn,
19141928 uint64_t Address, const void *Decoder) {
1915 unsigned imod = fieldFromInstruction32(Insn, 9, 2);
1916 unsigned M = fieldFromInstruction32(Insn, 8, 1);
1917 unsigned iflags = fieldFromInstruction32(Insn, 5, 3);
1918 unsigned mode = fieldFromInstruction32(Insn, 0, 5);
1929 unsigned imod = fieldFromInstruction(Insn, 9, 2);
1930 unsigned M = fieldFromInstruction(Insn, 8, 1);
1931 unsigned iflags = fieldFromInstruction(Insn, 5, 3);
1932 unsigned mode = fieldFromInstruction(Insn, 0, 5);
19191933
19201934 DecodeStatus S = MCDisassembler::Success;
19211935
19541968 uint64_t Address, const void *Decoder) {
19551969 DecodeStatus S = MCDisassembler::Success;
19561970
1957 unsigned Rd = fieldFromInstruction32(Insn, 8, 4);
1971 unsigned Rd = fieldFromInstruction(Insn, 8, 4);
19581972 unsigned imm = 0;
19591973
1960 imm |= (fieldFromInstruction32(Insn, 0, 8) << 0);
1961 imm |= (fieldFromInstruction32(Insn, 12, 3) << 8);
1962 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1963 imm |= (fieldFromInstruction32(Insn, 26, 1) << 11);
1974 imm |= (fieldFromInstruction(Insn, 0, 8) << 0);
1975 imm |= (fieldFromInstruction(Insn, 12, 3) << 8);
1976 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
1977 imm |= (fieldFromInstruction(Insn, 26, 1) << 11);
19641978
19651979 if (Inst.getOpcode() == ARM::t2MOVTi16)
19661980 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
19781992 uint64_t Address, const void *Decoder) {
19791993 DecodeStatus S = MCDisassembler::Success;
19801994
1981 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
1982 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
1995 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
1996 unsigned pred = fieldFromInstruction(Insn, 28, 4);
19831997 unsigned imm = 0;
19841998
1985 imm |= (fieldFromInstruction32(Insn, 0, 12) << 0);
1986 imm |= (fieldFromInstruction32(Insn, 16, 4) << 12);
1999 imm |= (fieldFromInstruction(Insn, 0, 12) << 0);
2000 imm |= (fieldFromInstruction(Insn, 16, 4) << 12);
19872001
19882002 if (Inst.getOpcode() == ARM::MOVTi16)
19892003 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
20042018 uint64_t Address, const void *Decoder) {
20052019 DecodeStatus S = MCDisassembler::Success;
20062020
2007 unsigned Rd = fieldFromInstruction32(Insn, 16, 4);
2008 unsigned Rn = fieldFromInstruction32(Insn, 0, 4);
2009 unsigned Rm = fieldFromInstruction32(Insn, 8, 4);
2010 unsigned Ra = fieldFromInstruction32(Insn, 12, 4);
2011 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2021 unsigned Rd = fieldFromInstruction(Insn, 16, 4);
2022 unsigned Rn = fieldFromInstruction(Insn, 0, 4);
2023 unsigned Rm = fieldFromInstruction(Insn, 8, 4);
2024 unsigned Ra = fieldFromInstruction(Insn, 12, 4);
2025 unsigned pred = fieldFromInstruction(Insn, 28, 4);
20122026
20132027 if (pred == 0xF)
20142028 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
20322046 uint64_t Address, const void *Decoder) {
20332047 DecodeStatus S = MCDisassembler::Success;
20342048
2035 unsigned add = fieldFromInstruction32(Val, 12, 1);
2036 unsigned imm = fieldFromInstruction32(Val, 0, 12);
2037 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
2049 unsigned add = fieldFromInstruction(Val, 12, 1);
2050 unsigned imm = fieldFromInstruction(Val, 0, 12);
2051 unsigned Rn = fieldFromInstruction(Val, 13, 4);
20382052
20392053 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
20402054 return MCDisassembler::Fail;
20522066 uint64_t Address, const void *Decoder) {
20532067 DecodeStatus S = MCDisassembler::Success;
20542068
2055 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
2056 unsigned U = fieldFromInstruction32(Val, 8, 1);
2057 unsigned imm = fieldFromInstruction32(Val, 0, 8);
2069 unsigned Rn = fieldFromInstruction(Val, 9, 4);
2070 unsigned U = fieldFromInstruction(Val, 8, 1);
2071 unsigned imm = fieldFromInstruction(Val, 0, 8);
20582072
20592073 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
20602074 return MCDisassembler::Fail;
20762090 DecodeT2BInstruction(MCInst &Inst, unsigned Insn,
20772091 uint64_t Address, const void *Decoder) {
20782092 DecodeStatus S = MCDisassembler::Success;
2079 unsigned imm = (fieldFromInstruction32(Insn, 0, 11) << 0) |
2080 (fieldFromInstruction32(Insn, 11, 1) << 18) |
2081 (fieldFromInstruction32(Insn, 13, 1) << 17) |
2082 (fieldFromInstruction32(Insn, 16, 6) << 11) |
2083 (fieldFromInstruction32(Insn, 26, 1) << 19);
2093 unsigned imm = (fieldFromInstruction(Insn, 0, 11) << 0) |
2094 (fieldFromInstruction(Insn, 11, 1) << 18) |
2095 (fieldFromInstruction(Insn, 13, 1) << 17) |
2096 (fieldFromInstruction(Insn, 16, 6) << 11) |
2097 (fieldFromInstruction(Insn, 26, 1) << 19);
20842098 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<20>(imm<<1) + 4,
20852099 true, 4, Inst, Decoder))
20862100 Inst.addOperand(MCOperand::CreateImm(SignExtend32<20>(imm << 1)));
20922106 uint64_t Address, const void *Decoder) {
20932107 DecodeStatus S = MCDisassembler::Success;
20942108
2095 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
2096 unsigned imm = fieldFromInstruction32(Insn, 0, 24) << 2;
2109 unsigned pred = fieldFromInstruction(Insn, 28, 4);
2110 unsigned imm = fieldFromInstruction(Insn, 0, 24) << 2;
20972111
20982112 if (pred == 0xF) {
20992113 Inst.setOpcode(ARM::BLXi);
2100 imm |= fieldFromInstruction32(Insn, 24, 1) << 1;
2114 imm |= fieldFromInstruction(Insn, 24, 1) << 1;
21012115 if (!tryAddingSymbolicOperand(Address, Address + SignExtend32<26>(imm) + 8,
21022116 true, 4, Inst, Decoder))
21032117 Inst.addOperand(MCOperand::CreateImm(SignExtend32<26>(imm)));
21182132 uint64_t Address, const void *Decoder) {
21192133 DecodeStatus S = MCDisassembler::Success;
21202134
2121 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
2122 unsigned align = fieldFromInstruction32(Val, 4, 2);
2135 unsigned Rm = fieldFromInstruction(Val, 0, 4);
2136 unsigned align = fieldFromInstruction(Val, 4, 2);
21232137
21242138 if (!Check(S, DecodeGPRRegisterClass(Inst, Rm, Address, Decoder)))
21252139 return MCDisassembler::Fail;
21352149 uint64_t Address, const void *Decoder) {
21362150 DecodeStatus S = MCDisassembler::Success;
21372151
2138 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2139 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2140 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2141 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2142 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2143 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2152 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2153 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2154 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2155 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2156 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2157 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
21442158
21452159 // First output register
21462160 switch (Inst.getOpcode()) {
24092423 uint64_t Address, const void *Decoder) {
24102424 DecodeStatus S = MCDisassembler::Success;
24112425
2412 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2413 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2414 unsigned wb = fieldFromInstruction32(Insn, 16, 4);
2415 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2416 Rn |= fieldFromInstruction32(Insn, 4, 2) << 4;
2417 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2426 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2427 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2428 unsigned wb = fieldFromInstruction(Insn, 16, 4);
2429 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2430 Rn |= fieldFromInstruction(Insn, 4, 2) << 4;
2431 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
24182432
24192433 // Writeback Operand
24202434 switch (Inst.getOpcode()) {
26802694 uint64_t Address, const void *Decoder) {
26812695 DecodeStatus S = MCDisassembler::Success;
26822696
2683 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2684 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2685 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2686 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2687 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2688 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2697 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2698 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2699 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2700 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2701 unsigned align = fieldFromInstruction(Insn, 4, 1);
2702 unsigned size = fieldFromInstruction(Insn, 6, 2);
26892703
26902704 align *= (1 << size);
26912705
27252739 uint64_t Address, const void *Decoder) {
27262740 DecodeStatus S = MCDisassembler::Success;
27272741
2728 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2729 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2730 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2731 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2732 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2733 unsigned size = 1 << fieldFromInstruction32(Insn, 6, 2);
2742 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2743 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2744 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2745 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2746 unsigned align = fieldFromInstruction(Insn, 4, 1);
2747 unsigned size = 1 << fieldFromInstruction(Insn, 6, 2);
27342748 align *= 2*size;
27352749
27362750 switch (Inst.getOpcode()) {
27732787 uint64_t Address, const void *Decoder) {
27742788 DecodeStatus S = MCDisassembler::Success;
27752789
2776 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2777 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2778 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2779 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2780 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2790 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2791 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2792 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2793 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2794 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
27812795
27822796 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
27832797 return MCDisassembler::Fail;
28082822 uint64_t Address, const void *Decoder) {
28092823 DecodeStatus S = MCDisassembler::Success;
28102824
2811 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2812 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2813 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2814 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2815 unsigned size = fieldFromInstruction32(Insn, 6, 2);
2816 unsigned inc = fieldFromInstruction32(Insn, 5, 1) + 1;
2817 unsigned align = fieldFromInstruction32(Insn, 4, 1);
2825 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2826 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2827 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2828 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2829 unsigned size = fieldFromInstruction(Insn, 6, 2);
2830 unsigned inc = fieldFromInstruction(Insn, 5, 1) + 1;
2831 unsigned align = fieldFromInstruction(Insn, 4, 1);
28182832
28192833 if (size == 0x3) {
28202834 size = 4;
28612875 uint64_t Address, const void *Decoder) {
28622876 DecodeStatus S = MCDisassembler::Success;
28632877
2864 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2865 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2866 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
2867 imm |= fieldFromInstruction32(Insn, 16, 3) << 4;
2868 imm |= fieldFromInstruction32(Insn, 24, 1) << 7;
2869 imm |= fieldFromInstruction32(Insn, 8, 4) << 8;
2870 imm |= fieldFromInstruction32(Insn, 5, 1) << 12;
2871 unsigned Q = fieldFromInstruction32(Insn, 6, 1);
2878 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2879 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2880 unsigned imm = fieldFromInstruction(Insn, 0, 4);
2881 imm |= fieldFromInstruction(Insn, 16, 3) << 4;
2882 imm |= fieldFromInstruction(Insn, 24, 1) << 7;
2883 imm |= fieldFromInstruction(Insn, 8, 4) << 8;
2884 imm |= fieldFromInstruction(Insn, 5, 1) << 12;
2885 unsigned Q = fieldFromInstruction(Insn, 6, 1);
28722886
28732887 if (Q) {
28742888 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
29062920 uint64_t Address, const void *Decoder) {
29072921 DecodeStatus S = MCDisassembler::Success;
29082922
2909 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2910 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2911 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2912 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2913 unsigned size = fieldFromInstruction32(Insn, 18, 2);
2923 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2924 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2925 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2926 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2927 unsigned size = fieldFromInstruction(Insn, 18, 2);
29142928
29152929 if (!Check(S, DecodeQPRRegisterClass(Inst, Rd, Address, Decoder)))
29162930 return MCDisassembler::Fail;
29492963 uint64_t Address, const void *Decoder) {
29502964 DecodeStatus S = MCDisassembler::Success;
29512965
2952 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
2953 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
2954 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
2955 Rn |= fieldFromInstruction32(Insn, 7, 1) << 4;
2956 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
2957 Rm |= fieldFromInstruction32(Insn, 5, 1) << 4;
2958 unsigned op = fieldFromInstruction32(Insn, 6, 1);
2966 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
2967 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
2968 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
2969 Rn |= fieldFromInstruction(Insn, 7, 1) << 4;
2970 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
2971 Rm |= fieldFromInstruction(Insn, 5, 1) << 4;
2972 unsigned op = fieldFromInstruction(Insn, 6, 1);
29592973
29602974 if (!Check(S, DecodeDPRRegisterClass(Inst, Rd, Address, Decoder)))
29612975 return MCDisassembler::Fail;
29852999 uint64_t Address, const void *Decoder) {
29863000 DecodeStatus S = MCDisassembler::Success;
29873001
2988 unsigned dst = fieldFromInstruction16(Insn, 8, 3);
2989 unsigned imm = fieldFromInstruction16(Insn, 0, 8);
3002 unsigned dst = fieldFromInstruction(Insn, 8, 3);
3003 unsigned imm = fieldFromInstruction(Insn, 0, 8);
29903004
29913005 if (!Check(S, DecodetGPRRegisterClass(Inst, dst, Address, Decoder)))
29923006 return MCDisassembler::Fail;
30333047 uint64_t Address, const void *Decoder) {
30343048 DecodeStatus S = MCDisassembler::Success;
30353049
3036 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3037 unsigned Rm = fieldFromInstruction32(Val, 3, 3);
3050 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3051 unsigned Rm = fieldFromInstruction(Val, 3, 3);
30383052
30393053 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
30403054 return MCDisassembler::Fail;
30483062 uint64_t Address, const void *Decoder) {
30493063 DecodeStatus S = MCDisassembler::Success;
30503064
3051 unsigned Rn = fieldFromInstruction32(Val, 0, 3);
3052 unsigned imm = fieldFromInstruction32(Val, 3, 5);
3065 unsigned Rn = fieldFromInstruction(Val, 0, 3);
3066 unsigned imm = fieldFromInstruction(Val, 3, 5);
30533067
30543068 if (!Check(S, DecodetGPRRegisterClass(Inst, Rn, Address, Decoder)))
30553069 return MCDisassembler::Fail;
30803094 uint64_t Address, const void *Decoder) {
30813095 DecodeStatus S = MCDisassembler::Success;
30823096
3083 unsigned Rn = fieldFromInstruction32(Val, 6, 4);
3084 unsigned Rm = fieldFromInstruction32(Val, 2, 4);
3085 unsigned imm = fieldFromInstruction32(Val, 0, 2);
3097 unsigned Rn = fieldFromInstruction(Val, 6, 4);
3098 unsigned Rm = fieldFromInstruction(Val, 2, 4);
3099 unsigned imm = fieldFromInstruction(Val, 0, 2);
30863100
30873101 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
30883102 return MCDisassembler::Fail;
31033117 case ARM::t2PLIs:
31043118 break;
31053119 default: {
3106 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3120 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
31073121 if (!Check(S, DecoderGPRRegisterClass(Inst, Rt, Address, Decoder)))
31083122 return MCDisassembler::Fail;
31093123 }
31103124 }
31113125
3112 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3126 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
31133127 if (Rn == 0xF) {
31143128 switch (Inst.getOpcode()) {
31153129 case ARM::t2LDRBs:
31323146 return MCDisassembler::Fail;
31333147 }
31343148
3135 int imm = fieldFromInstruction32(Insn, 0, 12);
3136 if (!fieldFromInstruction32(Insn, 23, 1)) imm *= -1;
3149 int imm = fieldFromInstruction(Insn, 0, 12);
3150 if (!fieldFromInstruction(Insn, 23, 1)) imm *= -1;
31373151 Inst.addOperand(MCOperand::CreateImm(imm));
31383152
31393153 return S;
31403154 }
31413155
3142 unsigned addrmode = fieldFromInstruction32(Insn, 4, 2);
3143 addrmode |= fieldFromInstruction32(Insn, 0, 4) << 2;
3144 addrmode |= fieldFromInstruction32(Insn, 16, 4) << 6;
3156 unsigned addrmode = fieldFromInstruction(Insn, 4, 2);
3157 addrmode |= fieldFromInstruction(Insn, 0, 4) << 2;
3158 addrmode |= fieldFromInstruction(Insn, 16, 4) << 6;
31453159 if (!Check(S, DecodeT2AddrModeSOReg(Inst, addrmode, Address, Decoder)))
31463160 return MCDisassembler::Fail;
31473161
31663180 uint64_t Address, const void *Decoder) {
31673181 DecodeStatus S = MCDisassembler::Success;
31683182
3169 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3170 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3183 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3184 unsigned imm = fieldFromInstruction(Val, 0, 9);
31713185
31723186 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
31733187 return MCDisassembler::Fail;
31813195 uint64_t Address, const void *Decoder) {
31823196 DecodeStatus S = MCDisassembler::Success;
31833197
3184 unsigned Rn = fieldFromInstruction32(Val, 8, 4);
3185 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3198 unsigned Rn = fieldFromInstruction(Val, 8, 4);
3199 unsigned imm = fieldFromInstruction(Val, 0, 8);
31863200
31873201 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rn, Address, Decoder)))
31883202 return MCDisassembler::Fail;
32093223 uint64_t Address, const void *Decoder) {
32103224 DecodeStatus S = MCDisassembler::Success;
32113225
3212 unsigned Rn = fieldFromInstruction32(Val, 9, 4);
3213 unsigned imm = fieldFromInstruction32(Val, 0, 9);
3226 unsigned Rn = fieldFromInstruction(Val, 9, 4);
3227 unsigned imm = fieldFromInstruction(Val, 0, 9);
32143228
32153229 // Some instructions always use an additive offset.
32163230 switch (Inst.getOpcode()) {
32403254 uint64_t Address, const void *Decoder) {
32413255 DecodeStatus S = MCDisassembler::Success;
32423256
3243 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3244 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3245 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
3246 addr |= fieldFromInstruction32(Insn, 9, 1) << 8;
3257 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3258 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3259 unsigned addr = fieldFromInstruction(Insn, 0, 8);
3260 addr |= fieldFromInstruction(Insn, 9, 1) << 8;
32473261 addr |= Rn << 9;
3248 unsigned load = fieldFromInstruction32(Insn, 20, 1);
3262 unsigned load = fieldFromInstruction(Insn, 20, 1);
32493263
32503264 if (!load) {
32513265 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
32703284 uint64_t Address, const void *Decoder) {
32713285 DecodeStatus S = MCDisassembler::Success;
32723286
3273 unsigned Rn = fieldFromInstruction32(Val, 13, 4);
3274 unsigned imm = fieldFromInstruction32(Val, 0, 12);
3287 unsigned Rn = fieldFromInstruction(Val, 13, 4);
3288 unsigned imm = fieldFromInstruction(Val, 0, 12);
32753289
32763290 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
32773291 return MCDisassembler::Fail;
32833297
32843298 static DecodeStatus DecodeThumbAddSPImm(MCInst &Inst, uint16_t Insn,
32853299 uint64_t Address, const void *Decoder) {
3286 unsigned imm = fieldFromInstruction16(Insn, 0, 7);
3300 unsigned imm = fieldFromInstruction(Insn, 0, 7);
32873301
32883302 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
32893303 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
32973311 DecodeStatus S = MCDisassembler::Success;
32983312
32993313 if (Inst.getOpcode() == ARM::tADDrSP) {
3300 unsigned Rdm = fieldFromInstruction16(Insn, 0, 3);
3301 Rdm |= fieldFromInstruction16(Insn, 7, 1) << 3;
3314 unsigned Rdm = fieldFromInstruction(Insn, 0, 3);
3315 Rdm |= fieldFromInstruction(Insn, 7, 1) << 3;
33023316
33033317 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
33043318 return MCDisassembler::Fail;
33063320 if (!Check(S, DecodeGPRRegisterClass(Inst, Rdm, Address, Decoder)))
33073321 return MCDisassembler::Fail;
33083322 } else if (Inst.getOpcode() == ARM::tADDspr) {
3309 unsigned Rm = fieldFromInstruction16(Insn, 3, 4);
3323 unsigned Rm = fieldFromInstruction(Insn, 3, 4);
33103324
33113325 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
33123326 Inst.addOperand(MCOperand::CreateReg(ARM::SP));
33193333
33203334 static DecodeStatus DecodeThumbCPS(MCInst &Inst, uint16_t Insn,
33213335 uint64_t Address, const void *Decoder) {
3322 unsigned imod = fieldFromInstruction16(Insn, 4, 1) | 0x2;
3323 unsigned flags = fieldFromInstruction16(Insn, 0, 3);
3336 unsigned imod = fieldFromInstruction(Insn, 4, 1) | 0x2;
3337 unsigned flags = fieldFromInstruction(Insn, 0, 3);
33243338
33253339 Inst.addOperand(MCOperand::CreateImm(imod));
33263340 Inst.addOperand(MCOperand::CreateImm(flags));
33313345 static DecodeStatus DecodePostIdxReg(MCInst &Inst, unsigned Insn,
33323346 uint64_t Address, const void *Decoder) {
33333347 DecodeStatus S = MCDisassembler::Success;
3334 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3335 unsigned add = fieldFromInstruction32(Insn, 4, 1);
3348 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3349 unsigned add = fieldFromInstruction(Insn, 4, 1);
33363350
33373351 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rm, Address, Decoder)))
33383352 return MCDisassembler::Fail;
33793393 uint64_t Address, const void *Decoder) {
33803394 DecodeStatus S = MCDisassembler::Success;
33813395
3382 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3383 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3396 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3397 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
33843398
33853399 if (Rn == ARM::SP) S = MCDisassembler::SoftFail;
33863400 if (!Check(S, DecodeGPRRegisterClass(Inst, Rn, Address, Decoder)))
33953409 uint64_t Address, const void *Decoder) {
33963410 DecodeStatus S = MCDisassembler::Success;
33973411
3398 unsigned pred = fieldFromInstruction32(Insn, 22, 4);
3412 unsigned pred = fieldFromInstruction(Insn, 22, 4);
33993413 if (pred == 0xE || pred == 0xF) {
3400 unsigned opc = fieldFromInstruction32(Insn, 4, 28);
3414 unsigned opc = fieldFromInstruction(Insn, 4, 28);
34013415 switch (opc) {
34023416 default:
34033417 return MCDisassembler::Fail;
34123426 break;
34133427 }
34143428
3415 unsigned imm = fieldFromInstruction32(Insn, 0, 4);
3429 unsigned imm = fieldFromInstruction(Insn, 0, 4);
34163430 return DecodeMemBarrierOption(Inst, imm, Address, Decoder);
34173431 }
34183432
3419 unsigned brtarget = fieldFromInstruction32(Insn, 0, 11) << 1;
3420 brtarget |= fieldFromInstruction32(Insn, 11, 1) << 19;
3421 brtarget |= fieldFromInstruction32(Insn, 13, 1) << 18;
3422 brtarget |= fieldFromInstruction32(Insn, 16, 6) << 12;
3423 brtarget |= fieldFromInstruction32(Insn, 26, 1) << 20;
3433 unsigned brtarget = fieldFromInstruction(Insn, 0, 11) << 1;
3434 brtarget |= fieldFromInstruction(Insn, 11, 1) << 19;
3435 brtarget |= fieldFromInstruction(Insn, 13, 1) << 18;
3436 brtarget |= fieldFromInstruction(Insn, 16, 6) << 12;
3437 brtarget |= fieldFromInstruction(Insn, 26, 1) << 20;
34243438
34253439 if (!Check(S, DecodeT2BROperand(Inst, brtarget, Address, Decoder)))
34263440 return MCDisassembler::Fail;
34353449 // a splat operation or a rotation.
34363450 static DecodeStatus DecodeT2SOImm(MCInst &Inst, unsigned Val,
34373451 uint64_t Address, const void *Decoder) {
3438 unsigned ctrl = fieldFromInstruction32(Val, 10, 2);
3452 unsigned ctrl = fieldFromInstruction(Val, 10, 2);
34393453 if (ctrl == 0) {
3440 unsigned byte = fieldFromInstruction32(Val, 8, 2);
3441 unsigned imm = fieldFromInstruction32(Val, 0, 8);
3454 unsigned byte = fieldFromInstruction(Val, 8, 2);
3455 unsigned imm = fieldFromInstruction(Val, 0, 8);
34423456 switch (byte) {
34433457 case 0:
34443458 Inst.addOperand(MCOperand::CreateImm(imm));
34553469 break;
34563470 }
34573471 } else {
3458 unsigned unrot = fieldFromInstruction32(Val, 0, 7) | 0x80;
3459 unsigned rot = fieldFromInstruction32(Val, 7, 5);
3472 unsigned unrot = fieldFromInstruction(Val, 0, 7) | 0x80;
3473 unsigned rot = fieldFromInstruction(Val, 7, 5);
34603474 unsigned imm = (unrot >> rot) | (unrot << ((32-rot)&31));
34613475 Inst.addOperand(MCOperand::CreateImm(imm));
34623476 }
35163530 uint64_t Address, const void *Decoder) {
35173531 DecodeStatus S = MCDisassembler::Success;
35183532
3519 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3520 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3521 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3533 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3534 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3535 unsigned pred = fieldFromInstruction(Insn, 28, 4);
35223536
35233537 if ((Rt & 1) || Rt == 0xE || Rn == 0xF) return MCDisassembler::Fail;
35243538
35393553 uint64_t Address, const void *Decoder){
35403554 DecodeStatus S = MCDisassembler::Success;
35413555
3542 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3543 unsigned Rt = fieldFromInstruction32(Insn, 0, 4);
3544 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3545 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3556 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3557 unsigned Rt = fieldFromInstruction(Insn, 0, 4);
3558 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3559 unsigned pred = fieldFromInstruction(Insn, 28, 4);
35463560
35473561 if (!Check(S, DecoderGPRRegisterClass(Inst, Rd, Address, Decoder)))
35483562 return MCDisassembler::Fail;
35663580 uint64_t Address, const void *Decoder) {
35673581 DecodeStatus S = MCDisassembler::Success;
35683582
3569 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3570 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3571 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3572 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3573 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3574 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3583 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3584 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3585 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3586 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3587 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3588 unsigned pred = fieldFromInstruction(Insn, 28, 4);
35753589
35763590 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
35773591
35913605 uint64_t Address, const void *Decoder) {
35923606 DecodeStatus S = MCDisassembler::Success;
35933607
3594 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3595 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3596 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3597 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3598 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3599 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3600 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3608 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3609 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3610 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3611 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3612 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3613 unsigned pred = fieldFromInstruction(Insn, 28, 4);
3614 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
36013615
36023616 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
36033617 if (Rm == 0xF) S = MCDisassembler::SoftFail;
36193633 uint64_t Address, const void *Decoder) {
36203634 DecodeStatus S = MCDisassembler::Success;
36213635
3622 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3623 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3624 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3625 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3626 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3627 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3636 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3637 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3638 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3639 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3640 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3641 unsigned pred = fieldFromInstruction(Insn, 28, 4);
36283642
36293643 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
36303644
36443658 uint64_t Address, const void *Decoder) {
36453659 DecodeStatus S = MCDisassembler::Success;
36463660
3647 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3648 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
3649 unsigned imm = fieldFromInstruction32(Insn, 0, 12);
3650 imm |= fieldFromInstruction32(Insn, 16, 4) << 13;
3651 imm |= fieldFromInstruction32(Insn, 23, 1) << 12;
3652 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
3661 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3662 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
3663 unsigned imm = fieldFromInstruction(Insn, 0, 12);
3664 imm |= fieldFromInstruction(Insn, 16, 4) << 13;
3665 imm |= fieldFromInstruction(Insn, 23, 1) << 12;
3666 unsigned pred = fieldFromInstruction(Insn, 28, 4);
36533667
36543668 if (Rn == 0xF || Rn == Rt) S = MCDisassembler::SoftFail;
36553669
36693683 uint64_t Address, const void *Decoder) {
36703684 DecodeStatus S = MCDisassembler::Success;
36713685
3672 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3673 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3674 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3675 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3676 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3686 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3687 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3688 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3689 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3690 unsigned size = fieldFromInstruction(Insn, 10, 2);
36773691
36783692 unsigned align = 0;
36793693 unsigned index = 0;
36813695 default:
36823696 return MCDisassembler::Fail;
36833697 case 0:
3684 if (fieldFromInstruction32(Insn, 4, 1))
3698 if (fieldFromInstruction(Insn, 4, 1))
36853699 return MCDisassembler::Fail; // UNDEFINED
3686 index = fieldFromInstruction32(Insn, 5, 3);
3700 index = fieldFromInstruction(Insn, 5, 3);
36873701 break;
36883702 case 1:
3689 if (fieldFromInstruction32(Insn, 5, 1))
3703 if (fieldFromInstruction(Insn, 5, 1))
36903704 return MCDisassembler::Fail; // UNDEFINED
3691 index = fieldFromInstruction32(Insn, 6, 2);
3692 if (fieldFromInstruction32(Insn, 4, 1))
3705 index = fieldFromInstruction(Insn, 6, 2);
3706 if (fieldFromInstruction(Insn, 4, 1))
36933707 align = 2;
36943708 break;
36953709 case 2:
3696 if (fieldFromInstruction32(Insn, 6, 1))
3710 if (fieldFromInstruction(Insn, 6, 1))
36973711 return MCDisassembler::Fail; // UNDEFINED
3698 index = fieldFromInstruction32(Insn, 7, 1);
3699 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3712 index = fieldFromInstruction(Insn, 7, 1);
3713 if (fieldFromInstruction(Insn, 4, 2) != 0)
37003714 align = 4;
37013715 }
37023716
37283742 uint64_t Address, const void *Decoder) {
37293743 DecodeStatus S = MCDisassembler::Success;
37303744
3731 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3732 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3733 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3734 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3735 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3745 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3746 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3747 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3748 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3749 unsigned size = fieldFromInstruction(Insn, 10, 2);
37363750
37373751 unsigned align = 0;
37383752 unsigned index = 0;
37403754 default:
37413755 return MCDisassembler::Fail;
37423756 case 0:
3743 if (fieldFromInstruction32(Insn, 4, 1))
3757 if (fieldFromInstruction(Insn, 4, 1))
37443758 return MCDisassembler::Fail; // UNDEFINED
3745 index = fieldFromInstruction32(Insn, 5, 3);
3759 index = fieldFromInstruction(Insn, 5, 3);
37463760 break;
37473761 case 1:
3748 if (fieldFromInstruction32(Insn, 5, 1))
3762 if (fieldFromInstruction(Insn, 5, 1))
37493763 return MCDisassembler::Fail; // UNDEFINED
3750 index = fieldFromInstruction32(Insn, 6, 2);
3751 if (fieldFromInstruction32(Insn, 4, 1))
3764 index = fieldFromInstruction(Insn, 6, 2);
3765 if (fieldFromInstruction(Insn, 4, 1))
37523766 align = 2;
37533767 break;
37543768 case 2:
3755 if (fieldFromInstruction32(Insn, 6, 1))
3769 if (fieldFromInstruction(Insn, 6, 1))
37563770 return MCDisassembler::Fail; // UNDEFINED
3757 index = fieldFromInstruction32(Insn, 7, 1);
3758 if (fieldFromInstruction32(Insn, 4, 2) != 0)
3771 index = fieldFromInstruction(Insn, 7, 1);
3772 if (fieldFromInstruction(Insn, 4, 2) != 0)
37593773 align = 4;
37603774 }
37613775
37863800 uint64_t Address, const void *Decoder) {
37873801 DecodeStatus S = MCDisassembler::Success;
37883802
3789 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3790 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3791 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3792 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3793 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3803 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3804 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3805 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3806 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3807 unsigned size = fieldFromInstruction(Insn, 10, 2);
37943808
37953809 unsigned align = 0;
37963810 unsigned index = 0;
37993813 default:
38003814 return MCDisassembler::Fail;
38013815 case 0:
3802 index = fieldFromInstruction32(Insn, 5, 3);
3803 if (fieldFromInstruction32(Insn, 4, 1))
3816 index = fieldFromInstruction(Insn, 5, 3);
3817 if (fieldFromInstruction(Insn, 4, 1))
38043818 align = 2;
38053819 break;
38063820 case 1:
3807 index = fieldFromInstruction32(Insn, 6, 2);
3808 if (fieldFromInstruction32(Insn, 4, 1))
3821 index = fieldFromInstruction(Insn, 6, 2);
3822 if (fieldFromInstruction(Insn, 4, 1))
38093823 align = 4;
3810 if (fieldFromInstruction32(Insn, 5, 1))
3824 if (fieldFromInstruction(Insn, 5, 1))
38113825 inc = 2;
38123826 break;
38133827 case 2:
3814 if (fieldFromInstruction32(Insn, 5, 1))
3828 if (fieldFromInstruction(Insn, 5, 1))
38153829 return MCDisassembler::Fail; // UNDEFINED
3816 index = fieldFromInstruction32(Insn, 7, 1);
3817 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3830 index = fieldFromInstruction(Insn, 7, 1);
3831 if (fieldFromInstruction(Insn, 4, 1) != 0)
38183832 align = 8;
3819 if (fieldFromInstruction32(Insn, 6, 1))
3833 if (fieldFromInstruction(Insn, 6, 1))
38203834 inc = 2;
38213835 break;
38223836 }
38533867 uint64_t Address, const void *Decoder) {
38543868 DecodeStatus S = MCDisassembler::Success;
38553869
3856 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3857 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3858 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3859 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3860 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3870 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3871 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3872 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3873 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3874 unsigned size = fieldFromInstruction(Insn, 10, 2);
38613875
38623876 unsigned align = 0;
38633877 unsigned index = 0;
38663880 default:
38673881 return MCDisassembler::Fail;
38683882 case 0:
3869 index = fieldFromInstruction32(Insn, 5, 3);
3870 if (fieldFromInstruction32(Insn, 4, 1))
3883 index = fieldFromInstruction(Insn, 5, 3);
3884 if (fieldFromInstruction(Insn, 4, 1))
38713885 align = 2;
38723886 break;
38733887 case 1:
3874 index = fieldFromInstruction32(Insn, 6, 2);
3875 if (fieldFromInstruction32(Insn, 4, 1))
3888 index = fieldFromInstruction(Insn, 6, 2);
3889 if (fieldFromInstruction(Insn, 4, 1))
38763890 align = 4;
3877 if (fieldFromInstruction32(Insn, 5, 1))
3891 if (fieldFromInstruction(Insn, 5, 1))
38783892 inc = 2;
38793893 break;
38803894 case 2:
3881 if (fieldFromInstruction32(Insn, 5, 1))
3895 if (fieldFromInstruction(Insn, 5, 1))
38823896 return MCDisassembler::Fail; // UNDEFINED
3883 index = fieldFromInstruction32(Insn, 7, 1);
3884 if (fieldFromInstruction32(Insn, 4, 1) != 0)
3897 index = fieldFromInstruction(Insn, 7, 1);
3898 if (fieldFromInstruction(Insn, 4, 1) != 0)
38853899 align = 8;
3886 if (fieldFromInstruction32(Insn, 6, 1))
3900 if (fieldFromInstruction(Insn, 6, 1))
38873901 inc = 2;
38883902 break;
38893903 }
39173931 uint64_t Address, const void *Decoder) {
39183932 DecodeStatus S = MCDisassembler::Success;
39193933
3920 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3921 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3922 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3923 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3924 unsigned size = fieldFromInstruction32(Insn, 10, 2);
3934 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
3935 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
3936 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
3937 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
3938 unsigned size = fieldFromInstruction(Insn, 10, 2);
39253939
39263940 unsigned align = 0;
39273941 unsigned index = 0;
39303944 default:
39313945 return MCDisassembler::Fail;
39323946 case 0:
3933 if (fieldFromInstruction32(Insn, 4, 1))
3947 if (fieldFromInstruction(Insn, 4, 1))
39343948 return MCDisassembler::Fail; // UNDEFINED
3935 index = fieldFromInstruction32(Insn, 5, 3);
3949 index = fieldFromInstruction(Insn, 5, 3);
39363950 break;
39373951 case 1:
3938 if (fieldFromInstruction32(Insn, 4, 1))
3952 if (fieldFromInstruction(Insn, 4, 1))
39393953 return MCDisassembler::Fail; // UNDEFINED
3940 index = fieldFromInstruction32(Insn, 6, 2);
3941 if (fieldFromInstruction32(Insn, 5, 1))
3954 index = fieldFromInstruction(Insn, 6, 2);
3955 if (fieldFromInstruction(Insn, 5, 1))
39423956 inc = 2;
39433957 break;
39443958 case 2:
3945 if (fieldFromInstruction32(Insn, 4, 2))
3959 if (fieldFromInstruction(Insn, 4, 2))
39463960 return MCDisassembler::Fail; // UNDEFINED
3947 index = fieldFromInstruction32(Insn, 7, 1);
3948 if (fieldFromInstruction32(Insn, 6, 1))
3961 index = fieldFromInstruction(Insn, 7, 1);
3962 if (fieldFromInstruction(Insn, 6, 1))
39493963 inc = 2;
39503964 break;
39513965 }
39874001 uint64_t Address, const void *Decoder) {
39884002 DecodeStatus S = MCDisassembler::Success;
39894003
3990 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
3991 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
3992 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
3993 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
3994 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4004 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4005 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4006 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4007 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4008 unsigned size = fieldFromInstruction(Insn, 10, 2);
39954009
39964010 unsigned align = 0;
39974011 unsigned index = 0;
40004014 default:
40014015 return MCDisassembler::Fail;
40024016 case 0:
4003 if (fieldFromInstruction32(Insn, 4, 1))
4017 if (fieldFromInstruction(Insn, 4, 1))
40044018 return MCDisassembler::Fail; // UNDEFINED
4005 index = fieldFromInstruction32(Insn, 5, 3);
4019 index = fieldFromInstruction(Insn, 5, 3);
40064020 break;
40074021 case 1:
4008 if (fieldFromInstruction32(Insn, 4, 1))
4022 if (fieldFromInstruction(Insn, 4, 1))
40094023 return MCDisassembler::Fail; // UNDEFINED
4010 index = fieldFromInstruction32(Insn, 6, 2);
4011 if (fieldFromInstruction32(Insn, 5, 1))
4024 index = fieldFromInstruction(Insn, 6, 2);
4025 if (fieldFromInstruction(Insn, 5, 1))
40124026 inc = 2;
40134027 break;
40144028 case 2:
4015 if (fieldFromInstruction32(Insn, 4, 2))
4029 if (fieldFromInstruction(Insn, 4, 2))
40164030 return MCDisassembler::Fail; // UNDEFINED
4017 index = fieldFromInstruction32(Insn, 7, 1);
4018 if (fieldFromInstruction32(Insn, 6, 1))
4031 index = fieldFromInstruction(Insn, 7, 1);
4032 if (fieldFromInstruction(Insn, 6, 1))
40194033 inc = 2;
40204034 break;
40214035 }
40514065 uint64_t Address, const void *Decoder) {
40524066 DecodeStatus S = MCDisassembler::Success;
40534067
4054 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4055 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4056 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4057 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4058 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4068 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4069 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4070 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4071 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4072 unsigned size = fieldFromInstruction(Insn, 10, 2);
40594073
40604074 unsigned align = 0;
40614075 unsigned index = 0;
40644078 default:
40654079 return MCDisassembler::Fail;
40664080 case 0:
4067 if (fieldFromInstruction32(Insn, 4, 1))
4081 if (fieldFromInstruction(Insn, 4, 1))
40684082 align = 4;
4069 index = fieldFromInstruction32(Insn, 5, 3);
4083 index = fieldFromInstruction(Insn, 5, 3);
40704084 break;
40714085 case 1:
4072 if (fieldFromInstruction32(Insn, 4, 1))
4086 if (fieldFromInstruction(Insn, 4, 1))
40734087 align = 8;
4074 index = fieldFromInstruction32(Insn, 6, 2);
4075 if (fieldFromInstruction32(Insn, 5, 1))
4088 index = fieldFromInstruction(Insn, 6, 2);
4089 if (fieldFromInstruction(Insn, 5, 1))
40764090 inc = 2;
40774091 break;
40784092 case 2:
4079 if (fieldFromInstruction32(Insn, 4, 2))
4080 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4081 index = fieldFromInstruction32(Insn, 7, 1);
4082 if (fieldFromInstruction32(Insn, 6, 1))
4093 if (fieldFromInstruction(Insn, 4, 2))
4094 align = 4 << fieldFromInstruction(Insn, 4, 2);
4095 index = fieldFromInstruction(Insn, 7, 1);
4096 if (fieldFromInstruction(Insn, 6, 1))
40834097 inc = 2;
40844098 break;
40854099 }
41254139 uint64_t Address, const void *Decoder) {
41264140 DecodeStatus S = MCDisassembler::Success;
41274141
4128 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4129 unsigned Rm = fieldFromInstruction32(Insn, 0, 4);
4130 unsigned Rd = fieldFromInstruction32(Insn, 12, 4);
4131 Rd |= fieldFromInstruction32(Insn, 22, 1) << 4;
4132 unsigned size = fieldFromInstruction32(Insn, 10, 2);
4142 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4143 unsigned Rm = fieldFromInstruction(Insn, 0, 4);
4144 unsigned Rd = fieldFromInstruction(Insn, 12, 4);
4145 Rd |= fieldFromInstruction(Insn, 22, 1) << 4;
4146 unsigned size = fieldFromInstruction(Insn, 10, 2);
41334147
41344148 unsigned align = 0;
41354149 unsigned index = 0;
41384152 default:
41394153 return MCDisassembler::Fail;
41404154 case 0:
4141 if (fieldFromInstruction32(Insn, 4, 1))
4155 if (fieldFromInstruction(Insn, 4, 1))
41424156 align = 4;
4143 index = fieldFromInstruction32(Insn, 5, 3);
4157 index = fieldFromInstruction(Insn, 5, 3);
41444158 break;
41454159 case 1:
4146 if (fieldFromInstruction32(Insn, 4, 1))
4160 if (fieldFromInstruction(Insn, 4, 1))
41474161 align = 8;
4148 index = fieldFromInstruction32(Insn, 6, 2);
4149 if (fieldFromInstruction32(Insn, 5, 1))
4162 index = fieldFromInstruction(Insn, 6, 2);
4163 if (fieldFromInstruction(Insn, 5, 1))
41504164 inc = 2;
41514165 break;
41524166 case 2:
4153 if (fieldFromInstruction32(Insn, 4, 2))
4154 align = 4 << fieldFromInstruction32(Insn, 4, 2);
4155 index = fieldFromInstruction32(Insn, 7, 1);
4156 if (fieldFromInstruction32(Insn, 6, 1))
4167 if (fieldFromInstruction(Insn, 4, 2))
4168 align = 4 << fieldFromInstruction(Insn, 4, 2);
4169 index = fieldFromInstruction(Insn, 7, 1);
4170 if (fieldFromInstruction(Insn, 6, 1))
41574171 inc = 2;
41584172 break;
41594173 }
41894203 static DecodeStatus DecodeVMOVSRR(MCInst &Inst, unsigned Insn,
41904204 uint64_t Address, const void *Decoder) {
41914205 DecodeStatus S = MCDisassembler::Success;
4192 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4193 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4194 unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
4195 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4196 Rm |= fieldFromInstruction32(Insn, 0, 4) << 1;
4206 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4207 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4208 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4209 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4210 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
41974211
41984212 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
41994213 S = MCDisassembler::SoftFail;
42154229 static DecodeStatus DecodeVMOVRRS(MCInst &Inst, unsigned Insn,
42164230 uint64_t Address, const void *Decoder) {
42174231 DecodeStatus S = MCDisassembler::Success;
4218 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4219 unsigned Rt2 = fieldFromInstruction32(Insn, 16, 4);
4220 unsigned Rm = fieldFromInstruction32(Insn, 5, 1);
4221 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4222 Rm |= fieldFromInstruction32(Insn, 0, 4) << 1;
4232 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4233 unsigned Rt2 = fieldFromInstruction(Insn, 16, 4);
4234 unsigned Rm = fieldFromInstruction(Insn, 5, 1);
4235 unsigned pred = fieldFromInstruction(Insn, 28, 4);
4236 Rm |= fieldFromInstruction(Insn, 0, 4) << 1;
42234237
42244238 if (Rt == 0xF || Rt2 == 0xF || Rm == 0x1F)
42254239 S = MCDisassembler::SoftFail;
42414255 static DecodeStatus DecodeIT(MCInst &Inst, unsigned Insn,
42424256 uint64_t Address, const void *Decoder) {
42434257 DecodeStatus S = MCDisassembler::Success;
4244 unsigned pred = fieldFromInstruction16(Insn, 4, 4);
4245 unsigned mask = fieldFromInstruction16(Insn, 0, 4);
4258 unsigned pred = fieldFromInstruction(Insn, 4, 4);
4259 unsigned mask = fieldFromInstruction(Insn, 0, 4);
42464260
42474261 if (pred == 0xF) {
42484262 pred = 0xE;
42644278 uint64_t Address, const void *Decoder) {
42654279 DecodeStatus S = MCDisassembler::Success;
42664280
4267 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4268 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4269 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4270 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4271 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4272 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4273 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4281 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4282 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4283 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4284 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4285 unsigned W = fieldFromInstruction(Insn, 21, 1);
4286 unsigned U = fieldFromInstruction(Insn, 23, 1);
4287 unsigned P = fieldFromInstruction(Insn, 24, 1);
42744288 bool writeback = (W == 1) | (P == 0);
42754289
42764290 addr |= (U << 8) | (Rn << 9);
43014315 uint64_t Address, const void *Decoder) {
43024316 DecodeStatus S = MCDisassembler::Success;
43034317
4304 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4305 unsigned Rt2 = fieldFromInstruction32(Insn, 8, 4);
4306 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4307 unsigned addr = fieldFromInstruction32(Insn, 0, 8);
4308 unsigned W = fieldFromInstruction32(Insn, 21, 1);
4309 unsigned U = fieldFromInstruction32(Insn, 23, 1);
4310 unsigned P = fieldFromInstruction32(Insn, 24, 1);
4318 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4319 unsigned Rt2 = fieldFromInstruction(Insn, 8, 4);
4320 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4321 unsigned addr = fieldFromInstruction(Insn, 0, 8);
4322 unsigned W = fieldFromInstruction(Insn, 21, 1);
4323 unsigned U = fieldFromInstruction(Insn, 23, 1);
4324 unsigned P = fieldFromInstruction(Insn, 24, 1);
43114325 bool writeback = (W == 1) | (P == 0);
43124326
43134327 addr |= (U << 8) | (Rn << 9);
43334347
43344348 static DecodeStatus DecodeT2Adr(MCInst &Inst, uint32_t Insn,
43354349 uint64_t Address, const void *Decoder) {
4336 unsigned sign1 = fieldFromInstruction32(Insn, 21, 1);
4337 unsigned sign2 = fieldFromInstruction32(Insn, 23, 1);
4350 unsigned sign1 = fieldFromInstruction(Insn, 21, 1);
4351 unsigned sign2 = fieldFromInstruction(Insn, 23, 1);
43384352 if (sign1 != sign2) return MCDisassembler::Fail;
43394353
4340 unsigned Val = fieldFromInstruction32(Insn, 0, 8);
4341 Val |= fieldFromInstruction32(Insn, 12, 3) << 8;
4342 Val |= fieldFromInstruction32(Insn, 26, 1) << 11;
4354 unsigned Val = fieldFromInstruction(Insn, 0, 8);
4355 Val |= fieldFromInstruction(Insn, 12, 3) << 8;
4356 Val |= fieldFromInstruction(Insn, 26, 1) << 11;
43434357 Val |= sign1 << 12;
43444358 Inst.addOperand(MCOperand::CreateImm(SignExtend32<13>(Val)));
43454359
43594373
43604374 static DecodeStatus DecodeSwap(MCInst &Inst, unsigned Insn,
43614375 uint64_t Address, const void *Decoder) {
4362 unsigned Rt = fieldFromInstruction32(Insn, 12, 4);
4363 unsigned Rt2 = fieldFromInstruction32(Insn, 0, 4);
4364 unsigned Rn = fieldFromInstruction32(Insn, 16, 4);
4365 unsigned pred = fieldFromInstruction32(Insn, 28, 4);
4376 unsigned Rt = fieldFromInstruction(Insn, 12, 4);
4377 unsigned Rt2 = fieldFromInstruction(Insn, 0, 4);
4378 unsigned Rn = fieldFromInstruction(Insn, 16, 4);
4379 unsigned pred = fieldFromInstruction(Insn, 28, 4);
43664380
43674381 if (pred == 0xF)
43684382 return DecodeCPSInstruction(Inst, Insn, Address, Decoder);
43864400
43874401 static DecodeStatus DecodeVCVTD(MCInst &Inst, unsigned Insn,
43884402 uint64_t Address, const void *Decoder) {
4389 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4390 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4391 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4392 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4393 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4394 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4403 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4404 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4405 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4406 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4407 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4408 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
43954409
43964410 DecodeStatus S = MCDisassembler::Success;
43974411
44144428
44154429 static DecodeStatus DecodeVCVTQ(MCInst &Inst, unsigned Insn,
44164430 uint64_t Address, const void *Decoder) {
4417 unsigned Vd = (fieldFromInstruction32(Insn, 12, 4) << 0);
4418 Vd |= (fieldFromInstruction32(Insn, 22, 1) << 4);
4419 unsigned Vm = (fieldFromInstruction32(Insn, 0, 4) << 0);
4420 Vm |= (fieldFromInstruction32(Insn, 5, 1) << 4);
4421 unsigned imm = fieldFromInstruction32(Insn, 16, 6);
4422 unsigned cmode = fieldFromInstruction32(Insn, 8, 4);
4431 unsigned Vd = (fieldFromInstruction(Insn, 12, 4) << 0);
4432 Vd |= (fieldFromInstruction(Insn, 22, 1) << 4);
4433 unsigned Vm = (fieldFromInstruction(Insn, 0, 4) << 0);
4434 Vm |= (fieldFromInstruction(Insn, 5, 1) << 4);
4435 unsigned imm = fieldFromInstruction(Insn, 16, 6);
4436 unsigned cmode = fieldFromInstruction(Insn, 8, 4);
44234437
44244438 DecodeStatus S = MCDisassembler::Success;
44254439
44444458 uint64_t Address, const void *Decoder) {
44454459 DecodeStatus S = MCDisassembler::Success;
44464460
4447 unsigned Rn = fieldFromInstruction32(Val, 16, 4);
4448 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4449 unsigned Rm = fieldFromInstruction32(Val, 0, 4);
4450 Rm |= (fieldFromInstruction32(Val, 23, 1) << 4);
4451 unsigned Cond = fieldFromInstruction32(Val, 28, 4);
4461 unsigned Rn = fieldFromInstruction(Val, 16, 4);
4462 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4463 unsigned Rm = fieldFromInstruction(Val, 0, 4);
4464 Rm |= (fieldFromInstruction(Val, 23, 1) << 4);
4465 unsigned Cond = fieldFromInstruction(Val, 28, 4);
44524466
4453 if (fieldFromInstruction32(Val, 8, 4) != 0 || Rn == Rt)
4467 if (fieldFromInstruction(Val, 8, 4) != 0 || Rn == Rt)
44544468 S = MCDisassembler::SoftFail;
44554469
44564470 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
44724486
44734487 DecodeStatus S = MCDisassembler::Success;
44744488
4475 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4476 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4477 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4478 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4479 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4489 unsigned CRm = fieldFromInstruction(Val, 0, 4);
4490 unsigned opc1 = fieldFromInstruction(Val, 4, 4);
4491 unsigned cop = fieldFromInstruction(Val, 8, 4);
4492 unsigned Rt = fieldFromInstruction(Val, 12, 4);
4493 unsigned Rt2 = fieldFromInstruction(Val, 16, 4);
44804494
44814495 if ((cop & ~0x1) == 0xa)
44824496 return MCDisassembler::Fail;
1515 #include "MipsRegisterInfo.h"
1616 #include "llvm/MC/EDInstInfo.h"
1717 #include "llvm/MC/MCDisassembler.h"
18 #include "llvm/MC/MCFixedLenDisassembler.h"
1819 #include "llvm/Support/MemoryObject.h"
1920 #include "llvm/Support/TargetRegistry.h"
2021 #include "llvm/MC/MCSubtargetInfo.h"
273274 return MCDisassembler::Fail;
274275
275276 // Calling the auto-generated decoder function.
276 Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
277 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
278 this, STI);
277279 if (Result != MCDisassembler::Fail) {
278280 Size = 4;
279281 return Result;
297299 return MCDisassembler::Fail;
298300
299301 // Calling the auto-generated decoder function.
300 Result = decodeMips64Instruction32(instr, Insn, Address, this, STI);
302 Result = decodeInstruction(DecoderTableMips6432, instr, Insn, Address,
303 this, STI);
301304 if (Result != MCDisassembler::Fail) {
302305 Size = 4;
303306 return Result;
304307 }
305308 // If we fail to decode in Mips64 decoder space we can try in Mips32
306 Result = decodeMipsInstruction32(instr, Insn, Address, this, STI);
309 Result = decodeInstruction(DecoderTableMips32, instr, Insn, Address,
310 this, STI);
307311 if (Result != MCDisassembler::Fail) {
308312 Size = 4;
309313 return Result;
378382 uint64_t Address,
379383 const void *Decoder) {
380384 int Offset = SignExtend32<16>(Insn & 0xffff);
381 unsigned Reg = fieldFromInstruction32(Insn, 16, 5);
382 unsigned Base = fieldFromInstruction32(Insn, 21, 5);
385 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
386 unsigned Base = fieldFromInstruction(Insn, 21, 5);
383387
384388 Reg = getReg(Decoder, Mips::CPURegsRegClassID, Reg);
385389 Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
400404 uint64_t Address,
401405 const void *Decoder) {
402406 int Offset = SignExtend32<16>(Insn & 0xffff);
403 unsigned Reg = fieldFromInstruction32(Insn, 16, 5);
404 unsigned Base = fieldFromInstruction32(Insn, 21, 5);
407 unsigned Reg = fieldFromInstruction(Insn, 16, 5);
408 unsigned Base = fieldFromInstruction(Insn, 21, 5);
405409
406410 Reg = getReg(Decoder, Mips::FGR64RegClassID, Reg);
407411 Base = getReg(Decoder, Mips::CPURegsRegClassID, Base);
483487 uint64_t Address,
484488 const void *Decoder) {
485489
486 unsigned JumpOffset = fieldFromInstruction32(Insn, 0, 26) << 2;
490 unsigned JumpOffset = fieldFromInstruction(Insn, 0, 26) << 2;
487491 Inst.addOperand(MCOperand::CreateImm(JumpOffset));
488492 return MCDisassembler::Success;
489493 }
1616 #include "CodeGenTarget.h"
1717 #include "llvm/TableGen/Record.h"
1818 #include "llvm/ADT/APInt.h"
19 #include "llvm/ADT/SmallString.h"
1920 #include "llvm/ADT/StringExtras.h"
21 #include "llvm/ADT/StringRef.h"
22 #include "llvm/ADT/Twine.h"
23 #include "llvm/MC/MCFixedLenDisassembler.h"
2024 #include "llvm/Support/DataTypes.h"
2125 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/FormattedStream.h"
27 #include "llvm/Support/LEB128.h"
2228 #include "llvm/Support/raw_ostream.h"
2329 #include "llvm/TableGen/TableGenBackend.h"
2430
3440 EncodingField(unsigned B, unsigned W, unsigned O)
3541 : Base(B), Width(W), Offset(O) { }
3642 };
37 } // End anonymous namespace
38
39 namespace {
43
4044 struct OperandInfo {
4145 std::vector Fields;
4246 std::string Decoder;
5559 const_iterator begin() const { return Fields.begin(); }
5660 const_iterator end() const { return Fields.end(); }
5761 };
62
63 typedef std::vector DecoderTable;
64 typedef uint32_t DecoderFixup;
65 typedef std::vector FixupList;
66 typedef std::vector FixupScopeList;
67 typedef SetVector PredicateSet;
68 typedef SetVector DecoderSet;
69 struct DecoderTableInfo {
70 DecoderTable Table;
71 FixupScopeList FixupStack;
72 PredicateSet Predicates;
73 DecoderSet Decoders;
74 };
75
5876 } // End anonymous namespace
5977
6078 namespace {
6179 class FixedLenDecoderEmitter {
80 const std::vector *NumberedInstructions;
6281 public:
6382
6483 // Defaults preserved here for documentation, even though they aren't
7594 PredicateNamespace(PredicateNamespace),
7695 GuardPrefix(GPrefix), GuardPostfix(GPostfix),
7796 ReturnOK(ROK), ReturnFail(RFail), Locals(L) {}
97
98 // Emit the decoder state machine table.
99 void emitTable(formatted_raw_ostream &o, DecoderTable &Table,
100 unsigned Indentation, unsigned BitWidth,
101 StringRef Namespace) const;
102 void emitPredicateFunction(formatted_raw_ostream &OS,
103 PredicateSet &Predicates,
104 unsigned Indentation) const;
105 void emitDecoderFunction(formatted_raw_ostream &OS,
106 DecoderSet &Decoders,
107 unsigned Indentation) const;
78108
79109 // run - Output the code emitter
80110 void run(raw_ostream &o);
237267 // match the remaining undecoded encoding bits against the singleton.
238268 void recurse();
239269
240 // Emit code to decode instructions given a segment or segments of bits.
241 void emit(raw_ostream &o, unsigned &Indentation) const;
270 // Emit table entries to decode instructions given a segment or segments of
271 // bits.
272 void emitTableEntry(DecoderTableInfo &TableInfo) const;
242273
243274 // Returns the number of fanout produced by the filter. More fanout implies
244275 // the filter distinguishes more categories of instructions.
337368 doFilter();
338369 }
339370
340 // The top level filter chooser has NULL as its parent.
341 bool isTopLevel() const { return Parent == NULL; }
342
343 // Emit the top level typedef and decodeInstruction() function.
344 void emitTop(raw_ostream &o, unsigned Indentation,
345 const std::string &Namespace) const;
371 unsigned getBitWidth() const { return BitWidth; }
346372
347373 protected:
348374 // Populates the insn given the uid.
413439 bool emitPredicateMatch(raw_ostream &o, unsigned &Indentation,
414440 unsigned Opc) const;
415441
416 void emitSoftFailCheck(raw_ostream &o, unsigned Indentation,
417 unsigned Opc) const;
418
419 // Emits code to decode the singleton. Return true if we have matched all the
420 // well-known bits.
421 bool emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
422 unsigned Opc) const;
442 bool doesOpcodeNeedPredicate(unsigned Opc) const;
443 unsigned getPredicateIndex(DecoderTableInfo &TableInfo, StringRef P) const;
444 void emitPredicateTableEntry(DecoderTableInfo &TableInfo,
445 unsigned Opc) const;
446
447 void emitSoftFailTableEntry(DecoderTableInfo &TableInfo,
448 unsigned Opc) const;
449
450 // Emits table entries to decode the singleton.
451 void emitSingletonTableEntry(DecoderTableInfo &TableInfo,
452 unsigned Opc) const;
423453
424454 // Emits code to decode the singleton, and then to decode the rest.
425 void emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
426 const Filter &Best) const;
427
428 void emitBinaryParser(raw_ostream &o , unsigned &Indentation,
455 void emitSingletonTableEntry(DecoderTableInfo &TableInfo,
456 const Filter &Best) const;
457
458 void emitBinaryParser(raw_ostream &o, unsigned &Indentation,
429459 const OperandInfo &OpInfo) const;
460
461 void emitDecoder(raw_ostream &OS, unsigned Indentation, unsigned Opc) const;
462 unsigned getDecoderIndex(DecoderSet &Decoders, unsigned Opc) const;
430463
431464 // Assign a single filter and run with it.
432465 void runSingleFilter(unsigned startBit, unsigned numBit, bool mixed);
446479 // dump the conflict set to the standard error.
447480 void doFilter();
448481
449 // Emits code to decode our share of instructions. Returns true if the
450 // emitted code causes a return, which occurs if we know how to decode
451 // the instruction at this level or the instruction is not decodeable.
452 bool emit(raw_ostream &o, unsigned &Indentation) const;
482 public:
483 // emitTableEntries - Emit state machine entries to decode our share of
484 // instructions.
485 void emitTableEntries(DecoderTableInfo &TableInfo) const;
453486 };
454487 } // End anonymous namespace
455488
543576 }
544577
545578 // No need to recurse for a singleton filtered instruction.
546 // See also Filter::emit().
579 // See also Filter::emit*().
547580 if (getNumFiltered() == 1) {
548581 //Owner->SingletonExists(LastOpcFiltered);
549582 assert(FilterChooserMap.size() == 1);
576609 }
577610 }
578611
579 // Emit code to decode instructions given a segment or segments of bits.
580 void Filter::emit(raw_ostream &o, unsigned &Indentation) const {
581 o.indent(Indentation) << "// Check Inst{";
582
583 if (NumBits > 1)
584 o << (StartBit + NumBits - 1) << '-';
585
586 o << StartBit << "} ...\n";
587
588 o.indent(Indentation) << "switch (fieldFromInstruction" << Owner->BitWidth
589 << "(insn, " << StartBit << ", "
590 << NumBits << ")) {\n";
612 static void resolveTableFixups(DecoderTable &Table, const FixupList &Fixups,
613 uint32_t DestIdx) {
614 // Any NumToSkip fixups in the current scope can resolve to the
615 // current location.
616 for (FixupList::const_reverse_iterator I = Fixups.rbegin(),
617 E = Fixups.rend();
618 I != E; ++I) {
619 // Calculate the distance from the byte following the fixup entry byte
620 // to the destination. The Target is calculated from after the 16-bit
621 // NumToSkip entry itself, so subtract two from the displacement here
622 // to account for that.
623 uint32_t FixupIdx = *I;
624 uint32_t Delta = DestIdx - FixupIdx - 2;
625 // Our NumToSkip entries are 16-bits. Make sure our table isn't too
626 // big.
627 assert(Delta < 65536U && "disassembler decoding table too large!");
628 Table[FixupIdx] = (uint8_t)Delta;
629 Table[FixupIdx + 1] = (uint8_t)(Delta >> 8);
630 }
631 }
632
633 // Emit table entries to decode instructions given a segment or segments
634 // of bits.
635 void Filter::emitTableEntry(DecoderTableInfo &TableInfo) const {
636 TableInfo.Table.push_back(MCD::OPC_ExtractField);
637 TableInfo.Table.push_back(StartBit);
638 TableInfo.Table.push_back(NumBits);
639
640 // A new filter entry begins a new scope for fixup resolution.
641 TableInfo.FixupStack.push_back(FixupList());
591642
592643 std::map::const_iterator filterIterator;
593644
594 bool DefaultCase = false;
645 DecoderTable &Table = TableInfo.Table;
646
647 size_t PrevFilter = 0;
648 bool HasFallthrough = false;
595649 for (filterIterator = FilterChooserMap.begin();
596650 filterIterator != FilterChooserMap.end();
597651 filterIterator++) {
598
599652 // Field value -1 implies a non-empty set of variable instructions.
600653 // See also recurse().
601654 if (filterIterator->first == (unsigned)-1) {
602 DefaultCase = true;
603
604 o.indent(Indentation) << "default:\n";
605 o.indent(Indentation) << " break; // fallthrough\n";
606
607 // Closing curly brace for the switch statement.
608 // This is unconventional because we want the default processing to be
609 // performed for the fallthrough cases as well, i.e., when the "cases"
610 // did not prove a decoded instruction.
611 o.indent(Indentation) << "}\n";
612
613 } else
614 o.indent(Indentation) << "case " << filterIterator->first << ":\n";
655 HasFallthrough = true;
656
657 // Each scope should always have at least one filter value to check
658 // for.
659 assert(PrevFilter != 0 && "empty filter set!");
660 FixupList &CurScope = TableInfo.FixupStack.back();
661 // Resolve any NumToSkip fixups in the current scope.
662 resolveTableFixups(Table, CurScope, Table.size());
663 CurScope.clear();
664 PrevFilter = 0; // Don't re-process the filter's fallthrough.
665 } else {
666 Table.push_back(MCD::OPC_FilterValue);
667 // Encode and emit the value to filter against.
668 uint8_t Buffer[8];
669 unsigned Len = encodeULEB128(filterIterator->first, Buffer);
670 Table.insert(Table.end(), Buffer, Buffer + Len);
671 // Reserve space for the NumToSkip entry. We'll backpatch the value
672 // later.
673 PrevFilter = Table.size();
674 Table.push_back(0);
675 Table.push_back(0);
676 }
615677
616678 // We arrive at a category of instructions with the same segment value.
617679 // Now delegate to the sub filter chooser for further decodings.
618680 // The case may fallthrough, which happens if the remaining well-known
619681 // encoding bits do not match exactly.
620 if (!DefaultCase) { ++Indentation; ++Indentation; }
621
622 filterIterator->second->emit(o, Indentation);
623 // For top level default case, there's no need for a break statement.
624 if (Owner->isTopLevel() && DefaultCase)
625 break;
626
627 o.indent(Indentation) << "break;\n";
628
629 if (!DefaultCase) { --Indentation; --Indentation; }
630 }
631
632 // If there is no default case, we still need to supply a closing brace.
633 if (!DefaultCase) {
634 // Closing curly brace for the switch statement.
635 o.indent(Indentation) << "}\n";
636 }
682 filterIterator->second->emitTableEntries(TableInfo);
683
684 // Now that we've emitted the body of the handler, update the NumToSkip
685 // of the filter itself to be able to skip forward when false. Subtract
686 // two as to account for the width of the NumToSkip field itself.
687 if (PrevFilter) {
688 uint32_t NumToSkip = Table.size() - PrevFilter - 2;
689 assert(NumToSkip < 65536U && "disassembler decoding table too large!");
690 Table[PrevFilter] = (uint8_t)NumToSkip;
691 Table[PrevFilter + 1] = (uint8_t)(NumToSkip >> 8);
692 }
693 }
694
695 // Any remaining unresolved fixups bubble up to the parent fixup scope.
696 assert(TableInfo.FixupStack.size() > 1 && "fixup stack underflow!");
697 FixupScopeList::iterator Source = TableInfo.FixupStack.end() - 1;
698 FixupScopeList::iterator Dest = Source - 1;
699 Dest->insert(Dest->end(), Source->begin(), Source->end());
700 TableInfo.FixupStack.pop_back();
701
702 // If there is no fallthrough, then the final filter should get fixed
703 // up according to the enclosing scope rather than the current position.
704 if (!HasFallthrough)
705 TableInfo.FixupStack.back().push_back(PrevFilter);
637706 }
638707
639708 // Returns the number of fanout produced by the filter. More fanout implies
651720 // //
652721 //////////////////////////////////
653722
654 // Emit the top level typedef and decodeInstruction() function.
655 void FilterChooser::emitTop(raw_ostream &o, unsigned Indentation,
656 const std::string &Namespace) const {
657 o.indent(Indentation) <<
658 "static MCDisassembler::DecodeStatus decode" << Namespace << "Instruction"
659 << BitWidth << "(MCInst &MI, uint" << BitWidth
660 << "_t insn, uint64_t Address, "
661 << "const void *Decoder, const MCSubtargetInfo &STI) {\n";
662 o.indent(Indentation) << " unsigned tmp = 0;\n";
663 o.indent(Indentation) << " (void)tmp;\n";
664 o.indent(Indentation) << Emitter->Locals << "\n";
665 o.indent(Indentation) << " uint64_t Bits = STI.getFeatureBits();\n";
666 o.indent(Indentation) << " (void)Bits;\n";
667
668 ++Indentation; ++Indentation;
669 // Emits code to decode the instructions.
670 emit(o, Indentation);
671
672 o << '\n';
673 o.indent(Indentation) << "return " << Emitter->ReturnFail << ";\n";
674 --Indentation; --Indentation;
675
676 o.indent(Indentation) << "}\n";
677
678 o << '\n';
723 // Emit the decoder state machine table.
724 void FixedLenDecoderEmitter::emitTable(formatted_raw_ostream &OS,
725 DecoderTable &Table,
726 unsigned Indentation,
727 unsigned BitWidth,
728 StringRef Namespace) const {
729 OS.indent(Indentation) << "static const uint8_t DecoderTable" << Namespace
730 << BitWidth << "[] = {\n";
731
732 Indentation += 2;
733
734 // FIXME: We may be able to use the NumToSkip values to recover
735 // appropriate indentation levels.
736 DecoderTable::const_iterator I = Table.begin();
737 DecoderTable::const_iterator E = Table.end();
738 while (I != E) {
739 assert (I < E && "incomplete decode table entry!");
740
741 uint64_t Pos = I - Table.begin();
742 OS << "/* " << Pos << " */";
743 OS.PadToColumn(12);
744
745 switch (*I) {
746 default:
747 throw "invalid decode table opcode";
748 case MCD::OPC_ExtractField: {
749 ++I;
750 unsigned Start = *I++;
751 unsigned Len = *I++;
752 OS.indent(Indentation) << "MCD::OPC_ExtractField, " << Start << ", "
753 << Len << ", // Inst{";
754 if (Len > 1)
755 OS << (Start + Len - 1) << "-";
756 OS << Start << "} ...\n";
757 break;
758 }
759 case MCD::OPC_FilterValue: {
760 ++I;
761 OS.indent(Indentation) << "MCD::OPC_FilterValue, ";
762 // The filter value is ULEB128 encoded.
763 while (*I >= 128)
764 OS << utostr(*I++) << ", ";
765 OS << utostr(*I++) << ", ";
766
767 // 16-bit numtoskip value.
768 uint8_t Byte = *I++;
769 uint32_t NumToSkip = Byte;
770 OS << utostr(Byte) << ", ";
771 Byte = *I++;
772 OS << utostr(Byte) << ", ";
773 NumToSkip |= Byte << 8;
774 OS << "// Skip to: " << ((I - Table.begin()) + NumToSkip) << "\n";
775 break;
776 }
777 case MCD::OPC_CheckField: {
778 ++I;
779 unsigned Start = *I++;
780 unsigned Len = *I++;
781 OS.indent(Indentation) << "MCD::OPC_CheckField, " << Start << ", "
782 << Len << ", ";// << Val << ", " << NumToSkip << ",\n";
783 // ULEB128 encoded field value.
784 for (; *I >= 128; ++I)
785 OS << utostr(*I) << ", ";
786 OS << utostr(*I++) << ", ";
787 // 16-bit numtoskip value.
788 uint8_t Byte = *I++;
789 uint32_t NumToSkip = Byte;
790 OS << utostr(Byte) << ", ";
791 Byte = *I++;
792 OS << utostr(Byte) << ", ";
793 NumToSkip |= Byte << 8;
794 OS << "// Skip to: " << ((I - Table.begin()) + NumToSkip) << "\n";
795 break;
796 }
797 case MCD::OPC_CheckPredicate: {
798 ++I;
799 OS.indent(Indentation) << "MCD::OPC_CheckPredicate, ";
800 for (; *I >= 128; ++I)
801 OS << utostr(*I) << ", ";
802 OS << utostr(*I++) << ", ";
803
804 // 16-bit numtoskip value.
805 uint8_t Byte = *I++;
806 uint32_t NumToSkip = Byte;
807 OS << utostr(Byte) << ", ";
808 Byte = *I++;
809 OS << utostr(Byte) << ", ";
810 NumToSkip |= Byte << 8;
811 OS << "// Skip to: " << ((I - Table.begin()) + NumToSkip) << "\n";
812 break;
813 }
814 case MCD::OPC_Decode: {
815 ++I;
816 // Extract the ULEB128 encoded Opcode to a buffer.
817 uint8_t Buffer[8], *p = Buffer;
818 while ((*p++ = *I++) >= 128)
819 assert((p - Buffer) <= (ptrdiff_t)sizeof(Buffer)
820 && "ULEB128 value too large!");
821 // Decode the Opcode value.
822 unsigned Opc = decodeULEB128(Buffer);
823 OS.indent(Indentation) << "MCD::OPC_Decode, ";
824 for (p = Buffer; *p >= 128; ++p)
825 OS << utostr(*p) << ", ";
826 OS << utostr(*p) << ", ";
827
828 // Decoder index.
829 for (; *I >= 128; ++I)
830 OS << utostr(*I) << ", ";
831 OS << utostr(*I++) << ", ";
832
833 OS << "// Opcode: "
834 << NumberedInstructions->at(Opc)->TheDef->getName() << "\n";
835 break;
836 }
837 case MCD::OPC_SoftFail: {
838 ++I;
839 OS.indent(Indentation) << "MCD::OPC_SoftFail";
840 // Positive mask
841 uint64_t Value = 0;
842 unsigned Shift = 0;
843 do {
844 OS << ", " << utostr(*I);
845 Value += (*I & 0x7f) << Shift;
846 Shift += 7;
847 } while (*I++ >= 128);
848 if (Value > 127)
849 OS << " /* 0x" << utohexstr(Value) << " */";
850 // Negative mask
851 Value = 0;
852 Shift = 0;
853 do {
854 OS << ", " << utostr(*I);
855 Value += (*I & 0x7f) << Shift;
856 Shift += 7;
857 } while (*I++ >= 128);
858 if (Value > 127)
859 OS << " /* 0x" << utohexstr(Value) << " */";
860 OS << ",\n";
861 break;
862 }
863 case MCD::OPC_Fail: {
864 ++I;
865 OS.indent(Indentation) << "MCD::OPC_Fail,\n";
866 break;
867 }
868 }
869 }
870 OS.indent(Indentation) << "0\n";
871
872 Indentation -= 2;
873
874 OS.indent(Indentation) << "};\n\n";
875 }
876
877 void FixedLenDecoderEmitter::
878 emitPredicateFunction(formatted_raw_ostream &OS, PredicateSet &Predicates,
879 unsigned Indentation) const {
880 // The predicate function is just a big switch statement based on the
881 // input predicate index.
882 OS.indent(Indentation) << "static bool checkDecoderPredicate(unsigned Idx, "
883 << "uint64_t Bits) {\n";
884 Indentation += 2;
885 OS.indent(Indentation) << "switch (Idx) {\n";
886 OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n";
887 unsigned Index = 0;
888 for (PredicateSet::const_iterator I = Predicates.begin(), E = Predicates.end();
889 I != E; ++I, ++Index) {
890 OS.indent(Indentation) << "case " << Index << ":\n";
891 OS.indent(Indentation+2) << "return (" << *I << ");\n";
892 }
893 OS.indent(Indentation) << "}\n";
894 Indentation -= 2;
895 OS.indent(Indentation) << "}\n\n";
896 }
897
898 void FixedLenDecoderEmitter::
899 emitDecoderFunction(formatted_raw_ostream &OS, DecoderSet &Decoders,
900 unsigned Indentation) const {
901 // The decoder function is just a big switch statement based on the
902 // input decoder index.
903 OS.indent(Indentation) << "template\n";
904 OS.indent(Indentation) << "static DecodeStatus decodeToMCInst(DecodeStatus S,"
905 << " unsigned Idx, InsnType insn, MCInst &MI,\n";
906 OS.indent(Indentation) << " uint64_t "
907 << "Address, void *Decoder) {\n";
908 Indentation += 2;
909 OS.indent(Indentation) << "InsnType tmp;\n";
910 OS.indent(Indentation) << "switch (Idx) {\n";
911 OS.indent(Indentation) << "default: llvm_unreachable(\"Invalid index!\");\n";
912 unsigned Index = 0;
913 for (DecoderSet::const_iterator I = Decoders.begin(), E = Decoders.end();
914 I != E; ++I, ++Index) {
915 OS.indent(Indentation) << "case " << Index << ":\n";
916 OS << *I << "\n";
917 OS.indent(Indentation+2) << "return S;\n";
918 }
919 OS.indent(Indentation) << "}\n";
920 Indentation -= 2;
921 OS.indent(Indentation) << "}\n\n";
679922 }
680923
681924 // Populates the field of the insn given the start position and the number of
8261069
8271070 if (OpInfo.numFields() == 1) {
8281071 OperandInfo::const_iterator OI = OpInfo.begin();
829 o.indent(Indentation) << " tmp = fieldFromInstruction" << BitWidth
830 << "(insn, " << OI->Base << ", " << OI->Width
831 << ");\n";
1072 o.indent(Indentation) << " tmp = fieldFromInstruction"
1073 << "(insn, " << OI->Base << ", " << OI->Width
1074 << ");\n";
8321075 } else {
8331076 o.indent(Indentation) << " tmp = 0;\n";
8341077 for (OperandInfo::const_iterator OI = OpInfo.begin(), OE = OpInfo.end();
8351078 OI != OE; ++OI) {
836 o.indent(Indentation) << " tmp |= (fieldFromInstruction" << BitWidth
1079 o.indent(Indentation) << " tmp |= (fieldFromInstruction"
8371080 << "(insn, " << OI->Base << ", " << OI->Width
8381081 << ") << " << OI->Offset << ");\n";
8391082 }
8461089 else
8471090 o.indent(Indentation) << " MI.addOperand(MCOperand::CreateImm(tmp));\n";
8481091
1092 }
1093
1094 void FilterChooser::emitDecoder(raw_ostream &OS, unsigned Indentation,
1095 unsigned Opc) const {
1096 std::map >::const_iterator OpIter =
1097 Operands.find(Opc);
1098 const std::vector& InsnOperands = OpIter->second;
1099 for (std::vector::const_iterator
1100 I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
1101 // If a custom instruction decoder was specified, use that.
1102 if (I->numFields() == 0 && I->Decoder.size()) {
1103 OS.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder
1104 << "(MI, insn, Address, Decoder)"
1105 << Emitter->GuardPostfix << "\n";
1106 break;
1107 }
1108
1109 emitBinaryParser(OS, Indentation, *I);
1110 }
1111 }
1112
1113 unsigned FilterChooser::getDecoderIndex(DecoderSet &Decoders,
1114 unsigned Opc) const {
1115 // Build up the predicate string.
1116 SmallString<256> Decoder;
1117 // FIXME: emitDecoder() function can take a buffer directly rather than
1118 // a stream.
1119 raw_svector_ostream S(Decoder);
1120 unsigned I = 0;
1121 emitDecoder(S, I, Opc);
1122 S.flush();
1123
1124 // Using the full decoder string as the key value here is a bit
1125 // heavyweight, but is effective. If the string comparisons become a
1126 // performance concern, we can implement a mangling of the predicate
1127 // data easilly enough with a map back to the actual string. That's
1128 // overkill for now, though.
1129
1130 // Make sure the predicate is in the table.
1131 Decoders.insert(Decoder.str());
1132 // Now figure out the index for when we write out the table.
1133 DecoderSet::const_iterator P = std::find(Decoders.begin(),
1134 Decoders.end(),
1135 Decoder.str());
1136 return (unsigned)(P - Decoders.begin());
8491137 }
8501138
8511139 static void emitSinglePredicateMatch(raw_ostream &o, StringRef str,
8861174 return Predicates->getSize() > 0;
8871175 }
8881176
889 void FilterChooser::emitSoftFailCheck(raw_ostream &o, unsigned Indentation,
890 unsigned Opc) const {
1177 bool FilterChooser::doesOpcodeNeedPredicate(unsigned Opc) const {
1178 ListInit *Predicates =
1179 AllInstructions[Opc]->TheDef->getValueAsListInit("Predicates");
1180 for (unsigned i = 0; i < Predicates->getSize(); ++i) {
1181 Record *Pred = Predicates->getElementAsRecord(i);
1182 if (!Pred->getValue("AssemblerMatcherPredicate"))
1183 continue;
1184
1185 std::string P = Pred->getValueAsString("AssemblerCondString");
1186
1187 if (!P.length())
1188 continue;
1189
1190 return true;
1191 }
1192 return false;
1193 }
1194
1195 unsigned FilterChooser::getPredicateIndex(DecoderTableInfo &TableInfo,
1196 StringRef Predicate) const {
1197 // Using the full predicate string as the key value here is a bit
1198 // heavyweight, but is effective. If the string comparisons become a
1199 // performance concern, we can implement a mangling of the predicate
1200 // data easilly enough with a map back to the actual string. That's
1201 // overkill for now, though.
1202
1203 // Make sure the predicate is in the table.
1204 TableInfo.Predicates.insert(Predicate.str());
1205 // Now figure out the index for when we write out the table.
1206 PredicateSet::const_iterator P = std::find(TableInfo.Predicates.begin(),
1207 TableInfo.Predicates.end(),
1208 Predicate.str());
1209 return (unsigned)(P - TableInfo.Predicates.begin());
1210 }
1211
1212 void FilterChooser::emitPredicateTableEntry(DecoderTableInfo &TableInfo,
1213 unsigned Opc) const {
1214 if (!doesOpcodeNeedPredicate(Opc))
1215 return;
1216
1217 // Build up the predicate string.
1218 SmallString<256> Predicate;
1219 // FIXME: emitPredicateMatch() functions can take a buffer directly rather
1220 // than a stream.
1221 raw_svector_ostream PS(Predicate);
1222 unsigned I = 0;
1223 emitPredicateMatch(PS, I, Opc);
1224
1225 // Figure out the index into the predicate table for the predicate just
1226 // computed.
1227 unsigned PIdx = getPredicateIndex(TableInfo, PS.str());
1228 SmallString<16> PBytes;
1229 raw_svector_ostream S(PBytes);
1230 encodeULEB128(PIdx, S);
1231 S.flush();
1232
1233 TableInfo.Table.push_back(MCD::OPC_CheckPredicate);
1234 // Predicate index
1235 for (int i = 0, e = PBytes.size(); i != e; ++i)
1236 TableInfo.Table.push_back(PBytes[i]);
1237 // Push location for NumToSkip backpatching.
1238 TableInfo.FixupStack.back().push_back(TableInfo.Table.size());
1239 TableInfo.Table.push_back(0);
1240 TableInfo.Table.push_back(0);
1241 }
1242
1243 void FilterChooser::emitSoftFailTableEntry(DecoderTableInfo &TableInfo,
1244 unsigned Opc) const {
8911245 BitsInit *SFBits =
8921246 AllInstructions[Opc]->TheDef->getValueAsBitsInit("SoftFail");
8931247 if (!SFBits) return;
9131267 default:
9141268 // The bit is not set; this must be an error!
9151269 StringRef Name = AllInstructions[Opc]->TheDef->getName();
916 errs() << "SoftFail Conflict: bit SoftFail{" << i << "} in "
917 << Name
918 << " is set but Inst{" << i <<"} is unset!\n"
1270 errs() << "SoftFail Conflict: bit SoftFail{" << i << "} in " << Name
1271 << " is set but Inst{" << i << "} is unset!\n"
9191272 << " - You can only mark a bit as SoftFail if it is fully defined"
9201273 << " (1/0 - not '?') in Inst\n";
921 o << "#error SoftFail Conflict, " << Name << "::SoftFail{" << i
922 << "} set but Inst{" << i << "} undefined!\n";
1274 return;
9231275 }
9241276 }
9251277
9291281 if (!NeedPositiveMask && !NeedNegativeMask)
9301282 return;
9311283
932 std::string PositiveMaskStr = PositiveMask.toString(16, /*signed=*/false);
933 std::string NegativeMaskStr = NegativeMask.toString(16, /*signed=*/false);
934 StringRef BitExt = "";
935 if (BitWidth > 32)
936 BitExt = "ULL";
937
938 o.indent(Indentation) << "if (";
939 if (NeedPositiveMask)
940 o << "insn & 0x" << PositiveMaskStr << BitExt;
941 if (NeedPositiveMask && NeedNegativeMask)
942 o << " || ";
943 if (NeedNegativeMask)
944 o << "~insn & 0x" << NegativeMaskStr << BitExt;
945 o << ")\n";
946 o.indent(Indentation+2) << "S = MCDisassembler::SoftFail;\n";
947 }
948
949 // Emits code to decode the singleton. Return true if we have matched all the
950 // well-known bits.
951 bool FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
952 unsigned Opc) const {
1284 TableInfo.Table.push_back(MCD::OPC_SoftFail);
1285
1286 SmallString<16> MaskBytes;
1287 raw_svector_ostream S(MaskBytes);
1288 if (NeedPositiveMask) {
1289 encodeULEB128(PositiveMask.getZExtValue(), S);
1290 S.flush();
1291 for (int i = 0, e = MaskBytes.size(); i != e; ++i)
1292 TableInfo.Table.push_back(MaskBytes[i]);
1293 } else
1294 TableInfo.Table.push_back(0);
1295 if (NeedNegativeMask) {
1296 MaskBytes.clear();
1297 S.resync();
1298 encodeULEB128(NegativeMask.getZExtValue(), S);
1299 S.flush();
1300 for (int i = 0, e = MaskBytes.size(); i != e; ++i)
1301 TableInfo.Table.push_back(MaskBytes[i]);
1302 } else
1303 TableInfo.Table.push_back(0);
1304 }
1305
1306 // Emits table entries to decode the singleton.
1307 void FilterChooser::emitSingletonTableEntry(DecoderTableInfo &TableInfo,
1308 unsigned Opc) const {
9531309 std::vector StartBits;
9541310 std::vector EndBits;
9551311 std::vector FieldVals;
9621318 unsigned Size = StartBits.size();
9631319 unsigned I, NumBits;
9641320
965 // If we have matched all the well-known bits, just issue a return.
966 if (Size == 0) {
967 o.indent(Indentation) << "if (";
968 if (!emitPredicateMatch(o, Indentation, Opc))
969 o << "1";
970 o << ") {\n";
971 emitSoftFailCheck(o, Indentation+2, Opc);
972 o.indent(Indentation) << " MI.setOpcode(" << Opc << ");\n";
973 std::map >::const_iterator OpIter =
974 Operands.find(Opc);
975 const std::vector& InsnOperands = OpIter->second;
976 for (std::vector::const_iterator
977 I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
978 // If a custom instruction decoder was specified, use that.
979 if (I->numFields() == 0 && I->Decoder.size()) {
980 o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder
981 << "(MI, insn, Address, Decoder)"
982 << Emitter->GuardPostfix << "\n";
983 break;
984 }
985
986 emitBinaryParser(o, Indentation, *I);
987 }
988
989 o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // "
990 << nameWithID(Opc) << '\n';
991 o.indent(Indentation) << "}\n"; // Closing predicate block.
992 return true;
993 }
994
995 // Otherwise, there are more decodings to be done!
996
997 // Emit code to match the island(s) for the singleton.
998 o.indent(Indentation) << "// Check ";
999
1000 for (I = Size; I != 0; --I) {
1001 o << "Inst{" << EndBits[I-1] << '-' << StartBits[I-1] << "} ";
1002 if (I > 1)
1003 o << " && ";
1004 else
1005 o << "for singleton decoding...\n";
1006 }
1007
1008 o.indent(Indentation) << "if (";
1009 if (emitPredicateMatch(o, Indentation, Opc)) {
1010 o << " &&\n";
1011 o.indent(Indentation+4);
1012 }
1013
1321 // Emit the predicate table entry if one is needed.
1322 emitPredicateTableEntry(TableInfo, Opc);
1323
1324 // Check any additional encoding fields needed.
10141325 for (I = Size; I != 0; --I) {
10151326 NumBits = EndBits[I-1] - StartBits[I-1] + 1;
1016 o << "fieldFromInstruction" << BitWidth << "(insn, "
1017 << StartBits[I-1] << ", " << NumBits
1018 << ") == " << FieldVals[I-1];
1019 if (I > 1)
1020 o << " && ";
1021 else
1022 o << ") {\n";
1023 }
1024 emitSoftFailCheck(o, Indentation+2, Opc);
1025 o.indent(Indentation) << " MI.setOpcode(" << Opc << ");\n";
1026 std::map >::const_iterator OpIter =
1027 Operands.find(Opc);
1028 const std::vector& InsnOperands = OpIter->second;
1029 for (std::vector::const_iterator
1030 I = InsnOperands.begin(), E = InsnOperands.end(); I != E; ++I) {
1031 // If a custom instruction decoder was specified, use that.
1032 if (I->numFields() == 0 && I->Decoder.size()) {
1033 o.indent(Indentation) << " " << Emitter->GuardPrefix << I->Decoder
1034 << "(MI, insn, Address, Decoder)"
1035 << Emitter->GuardPostfix << "\n";
1036 break;
1037 }
1038
1039 emitBinaryParser(o, Indentation, *I);
1040 }
1041 o.indent(Indentation) << " return " << Emitter->ReturnOK << "; // "
1042 << nameWithID(Opc) << '\n';
1043 o.indent(Indentation) << "}\n";
1044
1045 return false;
1046 }
1047
1048 // Emits code to decode the singleton, and then to decode the rest.
1049 void FilterChooser::emitSingletonDecoder(raw_ostream &o, unsigned &Indentation,
1050 const Filter &Best) const {
1051
1327 TableInfo.Table.push_back(MCD::OPC_CheckField);
1328 TableInfo.Table.push_back(StartBits[I-1]);
1329 TableInfo.Table.push_back(NumBits);
1330 uint8_t Buffer[8], *p;
1331 encodeULEB128(FieldVals[I-1], Buffer);
1332 for (p = Buffer; *p >= 128 ; ++p)
1333 TableInfo.Table.push_back(*p);
1334 TableInfo.Table.push_back(*p);
1335 // Push location for NumToSkip backpatching.
1336 TableInfo.FixupStack.back().push_back(TableInfo.Table.size());
1337 // The fixup is always 16-bits, so go ahead and allocate the space
1338 // in the table so all our relative position calculations work OK even
1339 // before we fully resolve the real value here.
1340 TableInfo.Table.push_back(0);
1341 TableInfo.Table.push_back(0);
1342 }
1343
1344 // Check for soft failure of the match.
1345 emitSoftFailTableEntry(TableInfo, Opc);
1346
1347 TableInfo.Table.push_back(MCD::OPC_Decode);
1348 uint8_t Buffer[8], *p;
1349 encodeULEB128(Opc, Buffer);
1350 for (p = Buffer; *p >= 128 ; ++p)
1351 TableInfo.Table.push_back(*p);
1352 TableInfo.Table.push_back(*p);
1353
1354 unsigned DIdx = getDecoderIndex(TableInfo.Decoders, Opc);
1355 SmallString<16> Bytes;
1356 raw_svector_ostream S(Bytes);
1357 encodeULEB128(DIdx, S);
1358 S.flush();
1359
1360 // Decoder index
1361 for (int i = 0, e = Bytes.size(); i != e; ++i)
1362 TableInfo.Table.push_back(Bytes[i]);
1363 }
1364
1365 // Emits table entries to decode the singleton, and then to decode the rest.
1366 void FilterChooser::emitSingletonTableEntry(DecoderTableInfo &TableInfo,
1367 const Filter &Best) const {
10521368 unsigned Opc = Best.getSingletonOpc();
10531369
1054 emitSingletonDecoder(o, Indentation, Opc);
1055
1056 // Emit code for the rest.
1057 o.indent(Indentation) << "else\n";
1058
1059 Indentation += 2;
1060 Best.getVariableFC().emit(o, Indentation);
1061 Indentation -= 2;
1062 }
1370 // complex singletons need predicate checks from the first singleton
1371 // to refer forward to the variable filterchooser that follows.
1372 TableInfo.FixupStack.push_back(FixupList());
1373
1374 emitSingletonTableEntry(TableInfo, Opc);
1375
1376 resolveTableFixups(TableInfo.Table, TableInfo.FixupStack.back(),
1377 TableInfo.Table.size());
1378 TableInfo.FixupStack.pop_back();
1379
1380 Best.getVariableFC().emitTableEntries(TableInfo);
1381 }
1382
10631383
10641384 // Assign a single filter and run with it. Top level API client can initialize
10651385 // with a single filter to start the filtering process.
13401660 BestIndex = -1;
13411661 }
13421662
1343 // Emits code to decode our share of instructions. Returns true if the
1344 // emitted code causes a return, which occurs if we know how to decode
1345 // the instruction at this level or the instruction is not decodeable.
1346 bool FilterChooser::emit(raw_ostream &o, unsigned &Indentation) const {
1347 if (Opcodes.size() == 1)
1663 // emitTableEntries - Emit state machine entries to decode our share of
1664 // instructions.
1665 void FilterChooser::emitTableEntries(DecoderTableInfo &TableInfo) const {
1666 if (Opcodes.size() == 1) {
13481667 // There is only one instruction in the set, which is great!
13491668 // Call emitSingletonDecoder() to see whether there are any remaining
13501669 // encodings bits.
1351 return emitSingletonDecoder(o, Indentation, Opcodes[0]);
1670 emitSingletonTableEntry(TableInfo, Opcodes[0]);
1671 return;
1672 }
13521673
13531674 // Choose the best filter to do the decodings!
13541675 if (BestIndex != -1) {
13551676 const Filter &Best = Filters[BestIndex];
13561677 if (Best.getNumFiltered() == 1)
1357 emitSingletonDecoder(o, Indentation, Best);
1678 emitSingletonTableEntry(TableInfo, Best);
13581679 else
1359 Best.emit(o, Indentation);
1360 return false;
1361 }
1362
1363 // We don't know how to decode these instructions! Return 0 and dump the
1364 // conflict set!
1365 o.indent(Indentation) << "return 0;" << " // Conflict set: ";
1366 for (int i = 0, N = Opcodes.size(); i < N; ++i) {
1367 o << nameWithID(Opcodes[i]);
1368 if (i < (N - 1))
1369 o << ", ";
1370 else
1371 o << '\n';
1372 }
1680 Best.emitTableEntry(TableInfo);
1681 return;
1682 }
1683
1684 // We don't know how to decode these instructions! Dump the
1685 // conflict set and bail.
13731686
13741687 // Print out useful conflict information for postmortem analysis.
13751688 errs() << "Decoding Conflict:\n";
13841697 getBitsField(*AllInstructions[Opcodes[i]]->TheDef, "Inst"));
13851698 errs() << '\n';
13861699 }
1387
1388 return true;
13891700 }
13901701
13911702 static bool populateInstruction(const CodeGenInstruction &CGI, unsigned Opc,
15481859 return true;
15491860 }
15501861
1551 static void emitHelper(llvm::raw_ostream &o, unsigned BitWidth) {
1552 unsigned Indentation = 0;
1553 std::string WidthStr = "uint" + utostr(BitWidth) + "_t";
1554
1555 o << '\n';
1556
1557 o.indent(Indentation) << "static " << WidthStr <<
1558 " fieldFromInstruction" << BitWidth <<
1559 "(" << WidthStr <<" insn, unsigned startBit, unsigned numBits)\n";
1560
1561 o.indent(Indentation) << "{\n";
1562
1563 ++Indentation; ++Indentation;
1564 o.indent(Indentation) << "assert(startBit + numBits <= " << BitWidth
1565 << " && \"Instruction field out of bounds!\");\n";
1566 o << '\n';
1567 o.indent(Indentation) << WidthStr << " fieldMask;\n";
1568 o << '\n';
1569 o.indent(Indentation) << "if (numBits == " << BitWidth << ")\n";
1570
1571 ++Indentation; ++Indentation;
1572 o.indent(Indentation) << "fieldMask = (" << WidthStr << ")-1;\n";
1573 --Indentation; --Indentation;
1574
1575 o.indent(Indentation) << "else\n";
1576
1577 ++Indentation; ++Indentation;
1578 o.indent(Indentation) << "fieldMask = ((1 << numBits) - 1) << startBit;\n";
1579 --Indentation; --Indentation;
1580
1581 o << '\n';
1582 o.indent(Indentation) << "return (insn & fieldMask) >> startBit;\n";
1583 --Indentation; --Indentation;
1584
1585 o.indent(Indentation) << "}\n";
1586
1587 o << '\n';
1862 // emitFieldFromInstruction - Emit the templated helper function
1863 // fieldFromInstruction().
1864 static void emitFieldFromInstruction(formatted_raw_ostream &OS) {
1865 OS << "// Helper function for extracting fields from encoded instructions.\n"
1866 << "template\n"
1867 << "static InsnType fieldFromInstruction(InsnType insn, unsigned startBit,\n"
1868 << " unsigned numBits) {\n"
1869 << " assert(startBit + numBits <= (sizeof(InsnType)*8) &&\n"
1870 << " \"Instruction field out of bounds!\");\n"
1871 << " InsnType fieldMask;\n"
1872 << " if (numBits == sizeof(InsnType)*8)\n"
1873 << " fieldMask = (InsnType)(-1LL);\n"
1874 << " else\n"
1875 << " fieldMask = ((1 << numBits) - 1) << startBit;\n"
1876 << " return (insn & fieldMask) >> startBit;\n"
1877 << "}\n\n";
1878 }
1879
1880 // emitDecodeInstruction - Emit the templated helper function
1881 // decodeInstruction().
1882 static void emitDecodeInstruction(formatted_raw_ostream &OS) {
1883 OS << "template\n"
1884 << "static DecodeStatus decodeInstruction(const uint8_t DecodeTable[], MCInst &MI,\n"
1885 << " InsnType insn, uint64_t Address,\n"
1886 << " const void *DisAsm,\n"
1887 << " const MCSubtargetInfo &STI) {\n"
1888 << " uint64_t Bits = STI.getFeatureBits();\n"
1889 << "\n"
1890 << " const uint8_t *Ptr = DecodeTable;\n"
1891 << " uint32_t CurFieldValue;\n"
1892 << " DecodeStatus S = MCDisassembler::Success;\n"
1893 << " for (;;) {\n"
1894 << " ptrdiff_t Loc = Ptr - DecodeTable;\n"
1895 << " switch (*Ptr) {\n"
1896 << " default:\n"
1897 << " errs() << Loc << \": Unexpected decode table opcode!\\n\";\n"
1898 << " return MCDisassembler::Fail;\n"
1899 << " case MCD::OPC_ExtractField: {\n"
1900 << " unsigned Start = *++Ptr;\n"
1901 << " unsigned Len = *++Ptr;\n"
1902 << " ++Ptr;\n"
1903 << " CurFieldValue = fieldFromInstruction(insn, Start, Len);\n"
1904 << " DEBUG(dbgs() << Loc << \": OPC_ExtractField(\" << Start << \", \"\n"
1905 << " << Len << \"): \" << CurFieldValue << \"\\n\");\n"
1906 << " break;\n"
1907 << " }\n"
1908 << " case MCD::OPC_FilterValue: {\n"
1909 << " // Decode the field value.\n"
1910 << " unsigned Len;\n"
1911 << " InsnType Val = decodeULEB128(++Ptr, &Len);\n"
1912 << " Ptr += Len;\n"
1913 << " // NumToSkip is a plain 16-bit integer.\n"
1914 << " unsigned NumToSkip = *Ptr++;\n"
1915 << " NumToSkip |= (*Ptr++) << 8;\n"
1916 << "\n"
1917 << " // Perform the filter operation.\n"
1918 << " if (Val != CurFieldValue)\n"
1919 << " Ptr += NumToSkip;\n"
1920 << " DEBUG(dbgs() << Loc << \": OPC_FilterValue(\" << Val << \", \" << NumToSkip\n"
1921 << " << \"): \" << ((Val != CurFieldValue) ? \"FAIL:\" : \"PASS:\")\n"
1922 << " << \" continuing at \" << (Ptr - DecodeTable) << \"\\n\");\n"
1923 << "\n"
1924 << " break;\n"
1925 << " }\n"
1926 << " case MCD::OPC_CheckField: {\n"
1927 << " unsigned Start = *++Ptr;\n"
1928 << " unsigned Len = *++Ptr;\n"
1929 << " InsnType FieldValue = fieldFromInstruction(insn, Start, Len);\n"
1930 << " // Decode the field value.\n"
1931 << " uint32_t ExpectedValue = decodeULEB128(++Ptr, &Len);\n"
1932 << " Ptr += Len;\n"
1933 << " // NumToSkip is a plain 16-bit integer.\n"
1934 << " unsigned NumToSkip = *Ptr++;\n"
1935 << " NumToSkip |= (*Ptr++) << 8;\n"
1936 << "\n"
1937 << " // If the actual and expected values don't match, skip.\n"
1938 << " if (ExpectedValue != FieldValue)\n"
1939 << " Ptr += NumToSkip;\n"
1940 << " DEBUG(dbgs() << Loc << \": OPC_CheckField(\" << Start << \", \"\n"
1941 << " << Len << \", \" << ExpectedValue << \", \" << NumToSkip\n"
1942 << " << \"): FieldValue = \" << FieldValue << \", ExpectedValue = \"\n"
1943 << " << ExpectedValue << \": \"\n"
1944 << " << ((ExpectedValue == FieldValue) ? \"PASS\\n\" : \"FAIL\\n\"));\n"
1945 << " break;\n"
1946 << " }\n"
1947 << " case MCD::OPC_CheckPredicate: {\n"
1948 << " unsigned Len;\n"
1949 << " // Decode the Predicate Index value.\n"
1950 << " unsigned PIdx = decodeULEB128(++Ptr, &Len);\n"
1951 << " Ptr += Len;\n"
1952 << " // NumToSkip is a plain 16-bit integer.\n"
1953 << " unsigned NumToSkip = *Ptr++;\n"
1954 << " NumToSkip |= (*Ptr++) << 8;\n"
1955 << " // Check the predicate.\n"
1956 << " bool Pred;\n"
1957 << " if (!(Pred = checkDecoderPredicate(PIdx, Bits)))\n"
1958 << " Ptr += NumToSkip;\n"
1959 << " (void)Pred;\n"
1960 << " DEBUG(dbgs() << Loc << \": OPC_CheckPredicate(\" << PIdx << \"): \"\n"
1961 << " << (Pred ? \"PASS\\n\" : \"FAIL\\n\"));\n"
1962 << "\n"
1963 << " break;\n"
1964 << " }\n"
1965 << " case MCD::OPC_Decode: {\n"
1966 << " unsigned Len;\n"
1967 << " // Decode the Opcode value.\n"
1968 << " unsigned Opc = decodeULEB128(++Ptr, &Len);\n"
1969 << " Ptr += Len;\n"
1970 << " unsigned DecodeIdx = decodeULEB128(Ptr, &Len);\n"
1971 << " Ptr += Len;\n"
1972 << " DEBUG(dbgs() << Loc << \": OPC_Decode: opcode \" << Opc\n"
1973 << " << \", using decoder \" << DecodeIdx << \"\\n\" );\n"
1974 << " DEBUG(dbgs() << \"----- DECODE SUCCESSFUL -----\\n\");\n"
1975 << "\n"
1976 << " MI.setOpcode(Opc);\n"
1977 << " return decodeToMCInst(S, DecodeIdx, insn, MI, Address, (void*)DisAsm);\n"
1978 << " }\n"
1979 << " case MCD::OPC_SoftFail: {\n"
1980 << " // Decode the mask values.\n"
1981 << " unsigned Len;\n"
1982 << " InsnType PositiveMask = decodeULEB128(++Ptr, &Len);\n"
1983 << " Ptr += Len;\n"
1984 << " InsnType NegativeMask = decodeULEB128(Ptr, &Len);\n"
1985 << " Ptr += Len;\n"
1986 << " bool Fail = (insn & PositiveMask) || (~insn & NegativeMask);\n"
1987 << " if (Fail)\n"
1988 << " S = MCDisassembler::SoftFail;\n"
1989 << " DEBUG(dbgs() << Loc << \": OPC_SoftFail: \" << (Fail ? \"FAIL\\n\":\"PASS\\n\"));\n"
1990 << " break;\n"
1991 << " }\n"
1992 << " case MCD::OPC_Fail: {\n"
1993 << " DEBUG(dbgs() << Loc << \": OPC_Fail\\n\");\n"
1994 << " return MCDisassembler::Fail;\n"
1995 << " }\n"
1996 << " }\n"
1997 << " }\n"
1998 << " llvm_unreachable(\"bogosity detected in disassembler state machine!\");\n"
1999 << "}\n\n";
15882000 }
15892001
15902002 // Emits disassembler code for instruction decoding.
15912003 void FixedLenDecoderEmitter::run(raw_ostream &o) {
1592 o << "#include \"llvm/MC/MCInst.h\"\n";
1593 o << "#include \"llvm/Support/DataTypes.h\"\n";
1594 o << "#include \n";
1595 o << '\n';
1596 o << "namespace llvm {\n\n";
2004 formatted_raw_ostream OS(o);
2005 OS << "#include \"llvm/MC/MCInst.h\"\n";
2006 OS << "#include \"llvm/Support/Debug.h\"\n";
2007 OS << "#include \"llvm/Support/DataTypes.h\"\n";
2008 OS << "#include \"llvm/Support/LEB128.h\"\n";
2009 OS << "#include \"llvm/Support/raw_ostream.h\"\n";
2010 OS << "#include \n";
2011 OS << '\n';
2012 OS << "namespace llvm {\n\n";
2013
2014 emitFieldFromInstruction(OS);
15972015
15982016 // Parameterize the decoders based on namespace and instruction width.
1599 const std::vector &NumberedInstructions =
1600 Target.getInstructionsByEnumValue();
2017 NumberedInstructions = &Target.getInstructionsByEnumValue();
16012018 std::map,
16022019 std::vector > OpcMap;
16032020 std::map > Operands;
16042021
1605 for (unsigned i = 0; i < NumberedInstructions.size(); ++i) {
1606 const CodeGenInstruction *Inst = NumberedInstructions[i];
2022 for (unsigned i = 0; i < NumberedInstructions->size(); ++i) {
2023 const CodeGenInstruction *Inst = NumberedInstructions->at(i);
16072024 const Record *Def = Inst->TheDef;
16082025 unsigned Size = Def->getValueAsInt("Size");
16092026 if (Def->getValueAsString("Namespace") == "TargetOpcode" ||
16212038 }
16222039 }
16232040
2041 DecoderTableInfo TableInfo;
16242042 std::set Sizes;
16252043 for (std::map,
16262044 std::vector >::const_iterator
16272045 I = OpcMap.begin(), E = OpcMap.end(); I != E; ++I) {
1628 // If we haven't visited this instruction width before, emit the
1629 // helper method to extract fields.
1630 if (!Sizes.count(I->first.second)) {
1631 emitHelper(o, 8*I->first.second);
1632 Sizes.insert(I->first.second);
1633 }
1634
16352046 // Emit the decoder for this namespace+width combination.
1636 FilterChooser FC(NumberedInstructions, I->second, Operands,
2047 FilterChooser FC(*NumberedInstructions, I->second, Operands,
16372048 8*I->first.second, this);
1638 FC.emitTop(o, 0, I->first.first);
1639 }
1640
1641 o << "\n} // End llvm namespace \n";
2049
2050 // The decode table is cleared for each top level decoder function. The
2051 // predicates and decoders themselves, however, are shared across all
2052 // decoders to give more opportunities for uniqueing.
2053 TableInfo.Table.clear();
2054 TableInfo.FixupStack.clear();
2055 TableInfo.Table.reserve(16384);
2056 TableInfo.FixupStack.push_back(FixupList());
2057 FC.emitTableEntries(TableInfo);
2058 // Any NumToSkip fixups in the top level scope can resolve to the
2059 // OPC_Fail at the end of the table.
2060 assert(TableInfo.FixupStack.size() == 1 && "fixup stack phasing error!");
2061 // Resolve any NumToSkip fixups in the current scope.
2062 resolveTableFixups(TableInfo.Table, TableInfo.FixupStack.back(),
2063 TableInfo.Table.size());
2064 TableInfo.FixupStack.clear();
2065
2066 TableInfo.Table.push_back(MCD::OPC_Fail);
2067
2068 // Print the table to the output stream.
2069 emitTable(OS, TableInfo.Table, 0, FC.getBitWidth(), I->first.first);
2070 OS.flush();
2071 }
2072
2073 // Emit the predicate function.
2074 emitPredicateFunction(OS, TableInfo.Predicates, 0);
2075
2076 // Emit the decoder function.
2077 emitDecoderFunction(OS, TableInfo.Decoders, 0);
2078
2079 // Emit the main entry point for the decoder, decodeInstruction().
2080 emitDecodeInstruction(OS);
2081
2082 OS << "\n} // End llvm namespace\n";
16422083 }
16432084
16442085 namespace llvm {