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MC: Add MCInstrDesc::mayAffectControlFlow() method. MC disassembler clients (LLDB) are interested in querying if an instruction may affect control flow other than by virtue of being an explicit branch instruction. For example, instructions which write directly to the PC on some architectures. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@170610 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 7 years ago
7 changed file(s) with 50 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
1515 #define LLVM_MC_MCINSTRDESC_H
1616
1717 #include "llvm/Support/DataTypes.h"
18 #include "llvm/MC/MCRegisterInfo.h"
19 #include "llvm/MC/MCInst.h"
1820
1921 namespace llvm {
2022
257259 return isBranch() & isBarrier() & !isIndirectBranch();
258260 }
259261
262 /// Return true if this is a branch or an instruction which directly
263 /// writes to the program counter. Considered 'may' affect rather than
264 /// 'does' affect as things like predication are not taken into account.
265 bool mayAffectControlFlow(const MCInst &MI, const MCRegisterInfo &RI) const {
266 if (isBranch() || isCall() || isReturn() || isIndirectBranch())
267 return true;
268 unsigned PC = RI.getProgramCounter();
269 if (PC == 0) return false;
270 return hasDefOfPhysReg(MI, PC, RI);
271 }
272
260273 /// isPredicable - Return true if this instruction has a predicate operand
261274 /// that controls execution. It may be set to 'always', or may be set to other
262275 /// values. There are various methods in TargetInstrInfo that can be used to
501514
502515 /// hasImplicitDefOfPhysReg - Return true if this instruction implicitly
503516 /// defines the specified physical register.
504 bool hasImplicitDefOfPhysReg(unsigned Reg) const {
517 bool hasImplicitDefOfPhysReg(unsigned Reg,
518 const MCRegisterInfo *MRI = 0) const {
505519 if (const uint16_t *ImpDefs = ImplicitDefs)
506520 for (; *ImpDefs; ++ImpDefs)
507 if (*ImpDefs == Reg) return true;
521 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs)))
522 return true;
508523 return false;
524 }
525
526 /// Return true if this instruction defines the specified physical
527 /// register, either explicitly or implicitly.
528 bool hasDefOfPhysReg(const MCInst &MI, unsigned Reg,
529 const MCRegisterInfo &RI) const {
530 for (int i = 0, e = NumDefs; i != e; ++i)
531 if (MI.getOperand(i).isReg() &&
532 RI.isSubRegisterEq(Reg, MI.getOperand(i).getReg()))
533 return true;
534 return hasImplicitDefOfPhysReg(Reg, &RI);
509535 }
510536
511537 /// getSchedClass - Return the scheduling class for this instruction. The
151151 const MCRegisterDesc *Desc; // Pointer to the descriptor array
152152 unsigned NumRegs; // Number of entries in the array
153153 unsigned RAReg; // Return address register
154 unsigned PCReg; // Program counter register
154155 const MCRegisterClass *Classes; // Pointer to the regclass array
155156 unsigned NumClasses; // Number of entries in the array
156157 unsigned NumRegUnits; // Number of regunits.
231232 /// InitMCRegisterInfo - Initialize MCRegisterInfo, called by TableGen
232233 /// auto-generated routines. *DO NOT USE*.
233234 void InitMCRegisterInfo(const MCRegisterDesc *D, unsigned NR, unsigned RA,
235 unsigned PC,
234236 const MCRegisterClass *C, unsigned NC,
235237 const uint16_t (*RURoots)[2],
236238 unsigned NRU,
242244 Desc = D;
243245 NumRegs = NR;
244246 RAReg = RA;
247 PCReg = PC;
245248 Classes = C;
246249 DiffLists = DL;
247250 RegStrings = Strings;
296299 return RAReg;
297300 }
298301
302 /// Return the register which is the program counter.
303 unsigned getProgramCounter() const {
304 return PCReg;
305 }
306
299307 const MCRegisterDesc &operator[](unsigned RegNo) const {
300308 assert(RegNo < NumRegs &&
301309 "Attempting to access record for invalid register number!");
4444
4545 ARMBaseRegisterInfo::ARMBaseRegisterInfo(const ARMBaseInstrInfo &tii,
4646 const ARMSubtarget &sti)
47 : ARMGenRegisterInfo(ARM::LR), TII(tii), STI(sti),
47 : ARMGenRegisterInfo(ARM::LR, 0, 0, ARM::PC), TII(tii), STI(sti),
4848 FramePtr((STI.isTargetDarwin() || STI.isThumb()) ? ARM::R7 : ARM::R11),
4949 BasePtr(ARM::R6) {
5050 }
145145
146146 static MCRegisterInfo *createARMMCRegisterInfo(StringRef Triple) {
147147 MCRegisterInfo *X = new MCRegisterInfo();
148 InitARMMCRegisterInfo(X, ARM::LR);
148 InitARMMCRegisterInfo(X, ARM::LR, 0, 0, ARM::PC);
149149 return X;
150150 }
151151
256256 MCRegisterInfo *X = new MCRegisterInfo();
257257 InitX86MCRegisterInfo(X, RA,
258258 X86_MC::getDwarfRegFlavour(TT, false),
259 X86_MC::getDwarfRegFlavour(TT, true));
259 X86_MC::getDwarfRegFlavour(TT, true),
260 RA);
260261 X86_MC::InitLLVM2SEHRegisterMapping(X);
261262 return X;
262263 }
5555
5656 X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm,
5757 const TargetInstrInfo &tii)
58 : X86GenRegisterInfo(tm.getSubtarget().is64Bit()
59 ? X86::RIP : X86::EIP,
58 : X86GenRegisterInfo((tm.getSubtarget().is64Bit()
59 ? X86::RIP : X86::EIP),
6060 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), false),
61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true)),
61 X86_MC::getDwarfRegFlavour(tm.getTargetTriple(), true),
62 (tm.getSubtarget().is64Bit()
63 ? X86::RIP : X86::EIP)),
6264 TM(tm), TII(tii) {
6365 X86_MC::InitLLVM2SEHRegisterMapping(this);
6466
920920 // MCRegisterInfo initialization routine.
921921 OS << "static inline void Init" << TargetName
922922 << "MCRegisterInfo(MCRegisterInfo *RI, unsigned RA, "
923 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0) {\n"
923 << "unsigned DwarfFlavour = 0, unsigned EHFlavour = 0, unsigned PC = 0) {\n"
924924 << " RI->InitMCRegisterInfo(" << TargetName << "RegDesc, "
925 << Regs.size()+1 << ", RA, " << TargetName << "MCRegisterClasses, "
925 << Regs.size()+1 << ", RA, PC, " << TargetName << "MCRegisterClasses, "
926926 << RegisterClasses.size() << ", "
927927 << TargetName << "RegUnitRoots, "
928928 << RegBank.getNumNativeRegUnits() << ", "
957957
958958 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
959959 << " explicit " << ClassName
960 << "(unsigned RA, unsigned D = 0, unsigned E = 0);\n"
960 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
961961 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
962962 << " { return false; }\n";
963963 if (!RegBank.getSubRegIndices().empty()) {
12661266 EmitRegMappingTables(OS, Regs, true);
12671267
12681268 OS << ClassName << "::\n" << ClassName
1269 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour)\n"
1269 << "(unsigned RA, unsigned DwarfFlavour, unsigned EHFlavour, unsigned PC)\n"
12701270 << " : TargetRegisterInfo(" << TargetName << "RegInfoDesc"
12711271 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n"
12721272 << " SubRegIndexNameTable, SubRegIndexLaneMaskTable) {\n"
12731273 << " InitMCRegisterInfo(" << TargetName << "RegDesc, "
1274 << Regs.size()+1 << ", RA,\n " << TargetName
1274 << Regs.size()+1 << ", RA, PC,\n " << TargetName
12751275 << "MCRegisterClasses, " << RegisterClasses.size() << ",\n"
12761276 << " " << TargetName << "RegUnitRoots,\n"
12771277 << " " << RegBank.getNumNativeRegUnits() << ",\n"