llvm.org GIT mirror llvm / fbcb9d6
[ARM][NFC] Make tests immune to better div optimizations Summary: Related to D52504 Reviewers: spatel Reviewed By: spatel Subscribers: javed.absar, kristof.beyls, chrib, llvm-commits Differential Revision: https://reviews.llvm.org/D53901 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@345665 91177308-0d34-0410-b5e6-96231b3b80d8 David Bolvansky 1 year, 3 months ago
3 changed file(s) with 16 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s
11
2 define <4 x i8> @i(<4 x i8>*) !dbg !8 {
3 %2 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
2 define <4 x i8> @i(<4 x i8>*, <4 x i8>) !dbg !8 {
3 %3 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
44 ; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load 4 from %ir.0)
5 ; CHECK-NEXT: VMOVLsv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
6 ; CHECK-NEXT: VMOVLsv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
7
8 %3 = sdiv <4 x i8> zeroinitializer, %2, !dbg !15
9 call void @llvm.dbg.value(metadata <4 x i8> %2, metadata !11, metadata !DIExpression()), !dbg !14
10 call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !13, metadata !DIExpression()), !dbg !15
11 ret <4 x i8> %3, !dbg !16
5 ; CHECK: VMOVLsv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
6 ; CHECK: VMOVLsv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
7 %4 = sdiv <4 x i8> %1, %3, !dbg !15
8 call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !11, metadata !DIExpression()), !dbg !14
9 call void @llvm.dbg.value(metadata <4 x i8> %4, metadata !13, metadata !DIExpression()), !dbg !15
10 ret <4 x i8> %4, !dbg !16
1211 }
1312
1413 declare void @llvm.dbg.value(metadata, metadata, metadata)
0 ; RUN: llc -mtriple armv7 %s -stop-before=livedebugvalues -o - | FileCheck %s
11
2 define <4 x i8> @i(<4 x i8>*) !dbg !8 {
3 %2 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
2 define <4 x i8> @i(<4 x i8>*, <4 x i8>) !dbg !8 {
3 %3 = load <4 x i8>, <4 x i8>* %0, align 4, !dbg !14
44 ; CHECK: $[[reg:.*]] = VLD1LNd32 {{.*}} debug-location !14 :: (load 4 from %ir.0)
55 ; CHECK-NEXT: VMOVLuv8i16 {{.*}} $[[reg]], {{.*}} debug-location !14
66 ; CHECK-NEXT: VMOVLuv4i32 {{.*}} $[[reg]], {{.*}} debug-location !14
7
8 %3 = udiv <4 x i8> zeroinitializer, %2, !dbg !15
9 call void @llvm.dbg.value(metadata <4 x i8> %2, metadata !11, metadata !DIExpression()), !dbg !14
10 call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !13, metadata !DIExpression()), !dbg !15
11 ret <4 x i8> %3, !dbg !16
7 %4 = udiv <4 x i8> %1, %3, !dbg !15
8 call void @llvm.dbg.value(metadata <4 x i8> %3, metadata !11, metadata !DIExpression()), !dbg !14
9 call void @llvm.dbg.value(metadata <4 x i8> %4, metadata !13, metadata !DIExpression()), !dbg !15
10 ret <4 x i8> %4, !dbg !16
1211 }
1312
1413 declare void @llvm.dbg.value(metadata, metadata, metadata)
4747 }
4848
4949 ; CHECK-LABEL: i:
50 define <4 x i8> @i(<4 x i8>* %x) {
50 define <4 x i8> @i(<4 x i8>* %x, <4 x i8> %y) {
5151 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
5252 ; instructions is bad on some cores
5353 ; CHECK: vld1
5858 ; CHECK: vmul
5959 ; CHECK: vmovn
6060 %1 = load <4 x i8>, <4 x i8>* %x, align 4
61 %2 = sdiv <4 x i8> zeroinitializer, %1
61 %2 = sdiv <4 x i8> %y, %1
6262 ret <4 x i8> %2
6363 }
6464 ; CHECK-LABEL: j: