llvm.org GIT mirror llvm / fbc21fa
ARM: 'add Rd, pc, #imm' is an alias for 'adr Rd, #imm'. rdar://9795790 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164577 91177308-0d34-0410-b5e6-96231b3b80d8 Jim Grosbach 7 years ago
2 changed file(s) with 18 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
56655665 processInstruction(MCInst &Inst,
56665666 const SmallVectorImpl &Operands) {
56675667 switch (Inst.getOpcode()) {
5668 // Alias for alternate form of 'ADR Rd, #imm' instruction.
5669 case ARM::ADDri: {
5670 if (Inst.getOperand(1).getReg() != ARM::PC ||
5671 Inst.getOperand(5).getReg() != 0)
5672 return false;
5673 MCInst TmpInst;
5674 TmpInst.setOpcode(ARM::ADR);
5675 TmpInst.addOperand(Inst.getOperand(0));
5676 TmpInst.addOperand(Inst.getOperand(2));
5677 TmpInst.addOperand(Inst.getOperand(3));
5678 TmpInst.addOperand(Inst.getOperand(4));
5679 Inst = TmpInst;
5680 return true;
5681 }
56685682 // Aliases for alternate PC+imm syntax of LDR instructions.
56695683 case ARM::t2LDRpcrel:
56705684 Inst.setOpcode(ARM::t2LDRpci);
123123 @ CHECK: bicseq r2, r2, #6 @ encoding: [0x06,0x20,0xd2,0x03]
124124 @ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01]
125125 @ CHECK: bicseq r2, r2, r3 @ encoding: [0x03,0x20,0xd2,0x01]
126
127 add r0, pc, #123
128
129 @ CHECK: adr r0, #123 @ encoding: [0x7b,0x00,0x8f,0xe2]