llvm.org GIT mirror llvm / fbad25e
CR fixes per Bruno's request. Undo the changes from r139285 which added custom lowering to vselect. Add tablegen lowering for vselect. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139479 91177308-0d34-0410-b5e6-96231b3b80d8 Nadav Rotem 9 years ago
4 changed file(s) with 53 addition(s) and 95 deletion(s). Raw diff Collapse all Expand all
145145 ]>;
146146
147147 def SDTSelect : SDTypeProfile<1, 3, [ // select
148 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
149 ]>;
150
151 def SDTVSelect : SDTypeProfile<1, 3, [ // vselect
148152 SDTCisInt<1>, SDTCisSameAs<0, 2>, SDTCisSameAs<2, 3>
149153 ]>;
150154
389393
390394 def setcc : SDNode<"ISD::SETCC" , SDTSetCC>;
391395 def select : SDNode<"ISD::SELECT" , SDTSelect>;
396 def vselect : SDNode<"ISD::VSELECT" , SDTVSelect>;
392397 def selectcc : SDNode<"ISD::SELECT_CC" , SDTSelectCC>;
393 def vsetcc : SDNode<"ISD::VSETCC" , SDTSetCC>;
394398
395399 def brcond : SDNode<"ISD::BRCOND" , SDTBrcond, [SDNPHasChain]>;
396400 def brind : SDNode<"ISD::BRIND" , SDTBrind, [SDNPHasChain]>;
916916 setOperationAction(ISD::SHL, MVT::v4i32, Custom);
917917 setOperationAction(ISD::SHL, MVT::v16i8, Custom);
918918
919 setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
920 setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
921 setOperationAction(ISD::VSELECT, MVT::v16i8, Custom);
922 setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
923 setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
919 setOperationAction(ISD::VSELECT, MVT::v2f64, Legal);
920 setOperationAction(ISD::VSELECT, MVT::v2i64, Legal);
921 setOperationAction(ISD::VSELECT, MVT::v16i8, Legal);
922 setOperationAction(ISD::VSELECT, MVT::v4i32, Legal);
923 setOperationAction(ISD::VSELECT, MVT::v4f32, Legal);
924924
925925 // i8 and i16 vectors are custom , because the source register and source
926926 // source memory operand types are not the same width. f32 vectors are
10181018 setOperationAction(ISD::SELECT, MVT::v4i64, Custom);
10191019 setOperationAction(ISD::SELECT, MVT::v8f32, Custom);
10201020
1021 setOperationAction(ISD::VSELECT, MVT::v4f64, Custom);
1022 setOperationAction(ISD::VSELECT, MVT::v4i64, Custom);
1023 setOperationAction(ISD::VSELECT, MVT::v8i32, Custom);
1024 setOperationAction(ISD::VSELECT, MVT::v8f32, Custom);
1021 setOperationAction(ISD::VSELECT, MVT::v4f64, Legal);
1022 setOperationAction(ISD::VSELECT, MVT::v4i64, Legal);
1023 setOperationAction(ISD::VSELECT, MVT::v8i32, Legal);
1024 setOperationAction(ISD::VSELECT, MVT::v8f32, Legal);
10251025
10261026 setOperationAction(ISD::ADD, MVT::v4i64, Custom);
10271027 setOperationAction(ISD::ADD, MVT::v8i32, Custom);
87018701 SDValue Ops[] = { Op2, Op1, CC, Cond };
87028702 return DAG.getNode(X86ISD::CMOV, DL, VTs, Ops, array_lengthof(Ops));
87038703 }
8704
8705 SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
8706 SDValue Cond = Op.getOperand(0);
8707 SDValue Op1 = Op.getOperand(1);
8708 SDValue Op2 = Op.getOperand(2);
8709 DebugLoc DL = Op.getDebugLoc();
8710
8711 SDValue Ops[] = {Op1, Op2, Cond};
8712
8713 assert(Op1.getValueType().isVector() && "Op1 must be a vector");
8714 assert(Op2.getValueType().isVector() && "Op2 must be a vector");
8715 assert(Cond.getValueType().isVector() && "Cond must be a vector");
8716 assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
8717
8718 EVT VT = Op1.getValueType();
8719 switch (VT.getSimpleVT().SimpleTy) {
8720 default: break;
8721 // SSE4:
8722 case MVT::v2i64:
8723 case MVT::v2f64:
8724 case MVT::v4i32:
8725 case MVT::v4f32:
8726 case MVT::v16i8:
8727 case MVT::v8i16:
8728 // AVX:
8729 case MVT::v4i64:
8730 case MVT::v4f64:
8731 case MVT::v8i32:
8732 case MVT::v8f32:
8733 case MVT::v32i8:
8734 case MVT::v16i16:
8735 return DAG.getNode(X86ISD::BLENDV, DL, VT, Ops, array_lengthof(Ops));
8736 }
8737
8738 return SDValue();
8739 }
8740
87418704
87428705 // isAndOrOfSingleUseSetCCs - Return true if node is an ISD::AND or
87438706 // ISD::OR of two X86ISD::SETCC nodes each of which has no other use apart
99929955 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
99939956 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
99949957 DAG.getConstant(4, MVT::i32));
9995 R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
9958 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
99969959 // a += a
99979960 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
99989961
100079970 M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
100089971 DAG.getConstant(Intrinsic::x86_sse2_pslli_w, MVT::i32), M,
100099972 DAG.getConstant(2, MVT::i32));
10010 R = DAG.getNode(X86ISD::BLENDV, dl, VT, R, M, Op);
9973 R = DAG.getNode(ISD::VSELECT, dl, VT, Op, R, M);
100119974 // a += a
100129975 Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
100139976
100149977 // return pblendv(r, r+r, a);
10015 R = DAG.getNode(X86ISD::BLENDV, dl, VT,
10016 R, DAG.getNode(ISD::ADD, dl, VT, R, R), Op);
9978 R = DAG.getNode(ISD::VSELECT, dl, VT, Op,
9979 R, DAG.getNode(ISD::ADD, dl, VT, R, R));
100179980 return R;
100189981 }
100199982 return SDValue();
1040510368 case ISD::FGETSIGN: return LowerFGETSIGN(Op, DAG);
1040610369 case ISD::SETCC: return LowerSETCC(Op, DAG);
1040710370 case ISD::SELECT: return LowerSELECT(Op, DAG);
10408 case ISD::VSELECT: return LowerVSELECT(Op, DAG);
1040910371 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
1041010372 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
1041110373 case ISD::VASTART: return LowerVASTART(Op, DAG);
1065010612 case X86ISD::PSIGNB: return "X86ISD::PSIGNB";
1065110613 case X86ISD::PSIGNW: return "X86ISD::PSIGNW";
1065210614 case X86ISD::PSIGND: return "X86ISD::PSIGND";
10653 case X86ISD::BLENDV: return "X86ISD::BLENDV";
1065410615 case X86ISD::FMAX: return "X86ISD::FMAX";
1065510616 case X86ISD::FMIN: return "X86ISD::FMIN";
1065610617 case X86ISD::FRSQRT: return "X86ISD::FRSQRT";
1338013341 X = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, X);
1338113342 Y = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Y);
1338213343 Mask = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Mask);
13383 Mask = DAG.getNode(X86ISD::BLENDV, DL, MVT::v16i8, X, Y, Mask);
13344 Mask = DAG.getNode(ISD::VSELECT, DL, MVT::v16i8, Mask, X, Y);
1338413345 return DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Mask);
1338513346 }
1338613347 }
808808 SDValue LowerSETCC(SDValue Op, SelectionDAG &DAG) const;
809809 SDValue LowerVSETCC(SDValue Op, SelectionDAG &DAG) const;
810810 SDValue LowerSELECT(SDValue Op, SelectionDAG &DAG) const;
811 SDValue LowerVSELECT(SDValue Op, SelectionDAG &DAG) const;
812811 SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
813812 SDValue LowerMEMSET(SDValue Op, SelectionDAG &DAG) const;
814813 SDValue LowerJumpTable(SDValue Op, SelectionDAG &DAG) const;
58685868
58695869 let Predicates = [HasAVX] in {
58705870 def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
5871 VR128:$mask)),
5872 (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5873 def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2),
5874 VR128:$mask)),
5875 (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5876 def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2),
5877 VR128:$mask)),
5878 (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5879 def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2),
5880 VR128:$mask)),
5881 (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5882 def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2),
5883 VR128:$mask)),
5884 (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5885
5886
5887 def : Pat<(v8i32 (X86blendv (v8i32 VR256:$src1), (v8i32 VR256:$src2),
5888 VR256:$mask)),
5889 (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5890 def : Pat<(v8f32 (X86blendv (v8f32 VR256:$src1), (v8f32 VR256:$src2),
5891 VR256:$mask)),
5892 (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5893
5894
5895 def : Pat<(v4i64 (X86blendv (v4i64 VR256:$src1), (v4i64 VR256:$src2),
5896 VR256:$mask)),
5897 (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5898 def : Pat<(v4f64 (X86blendv (v4f64 VR256:$src1), (v4f64 VR256:$src2),
5899 VR256:$mask)),
5900 (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5871 VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5872
5873 def : Pat<(v16i8 (vselect (v16i8 VR128:$mask), (v16i8 VR128:$src1),
5874 (v16i8 VR128:$src2))), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5875 def : Pat<(v4i32 (vselect (v4i32 VR128:$mask), (v4i32 VR128:$src1),
5876 (v4i32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5877 def : Pat<(v4f32 (vselect (v4i32 VR128:$mask), (v4f32 VR128:$src1),
5878 (v4f32 VR128:$src2))), (VBLENDVPSrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5879 def : Pat<(v2i64 (vselect (v2i64 VR128:$mask), (v2i64 VR128:$src1),
5880 (v2i64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5881 def : Pat<(v2f64 (vselect (v2i64 VR128:$mask), (v2f64 VR128:$src1),
5882 (v2f64 VR128:$src2))), (VBLENDVPDrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5883 def : Pat<(v8i32 (vselect (v8i32 VR256:$mask), (v8i32 VR256:$src1),
5884 (v8i32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5885 def : Pat<(v8f32 (vselect (v8i32 VR256:$mask), (v8f32 VR256:$src1),
5886 (v8f32 VR256:$src2))), (VBLENDVPSYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5887 def : Pat<(v4i64 (vselect (v4i64 VR256:$mask), (v4i64 VR256:$src1),
5888 (v4i64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5889 def : Pat<(v4f64 (vselect (v4i64 VR256:$mask), (v4f64 VR256:$src1),
5890 (v4f64 VR256:$src2))), (VBLENDVPDYrr VR256:$src1, VR256:$src2, VR256:$mask)>;
5891
59015892 }
59025893
59035894 /// SS41I_ternary_int - SSE 4.1 ternary operator
59255916 defm PBLENDVB : SS41I_ternary_int<0x10, "pblendvb", int_x86_sse41_pblendvb>;
59265917
59275918 let Predicates = [HasSSE41] in {
5928 def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2), XMM0)),
5929 (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5930 def : Pat<(v4i32 (X86blendv (v4i32 VR128:$src1), (v4i32 VR128:$src2), XMM0)),
5931 (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
5932 def : Pat<(v4f32 (X86blendv (v4f32 VR128:$src1), (v4f32 VR128:$src2), XMM0)),
5933 (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
5934 def : Pat<(v2i64 (X86blendv (v2i64 VR128:$src1), (v2i64 VR128:$src2), XMM0)),
5935 (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
5936 def : Pat<(v2f64 (X86blendv (v2f64 VR128:$src1), (v2f64 VR128:$src2), XMM0)),
5937 (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
5919 def : Pat<(v16i8 (X86blendv (v16i8 VR128:$src1), (v16i8 VR128:$src2),
5920 VR128:$mask)), (VPBLENDVBrr VR128:$src1, VR128:$src2, VR128:$mask)>;
5921
5922 def : Pat<(v16i8 (vselect (v16i8 XMM0), (v16i8 VR128:$src1),
5923 (v16i8 VR128:$src2))), (PBLENDVBrr0 VR128:$src1, VR128:$src2)>;
5924 def : Pat<(v4i32 (vselect (v4i32 XMM0), (v4i32 VR128:$src1),
5925 (v4i32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
5926 def : Pat<(v4f32 (vselect (v4i32 XMM0), (v4f32 VR128:$src1),
5927 (v4f32 VR128:$src2))), (BLENDVPSrr0 VR128:$src1, VR128:$src2)>;
5928 def : Pat<(v2i64 (vselect (v2i64 XMM0), (v2i64 VR128:$src1),
5929 (v2i64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
5930 def : Pat<(v2f64 (vselect (v2i64 XMM0), (v2f64 VR128:$src1),
5931 (v2f64 VR128:$src2))), (BLENDVPDrr0 VR128:$src1, VR128:$src2)>;
59385932 }
59395933
59405934 let Predicates = [HasAVX] in