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Switch most getReservedRegs() clients to the MRI equivalent. Using the cached bit vector in MRI avoids comstantly allocating and recomputing the reserved register bit vector. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@165983 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
12 changed file(s) with 28 addition(s) and 52 deletion(s). Raw diff Collapse all Expand all
125125 /// building live intervals.
126126 SparseBitVector<> PHIJoins;
127127
128 /// ReservedRegisters - This vector keeps track of which registers
129 /// are reserved register which are not allocatable by the target machine.
130 /// We can not track liveness for values that are in this set.
131 ///
132 BitVector ReservedRegisters;
133
134128 private: // Intermediate data structures
135129 MachineFunction *MF;
136130
1717 #define LLVM_CODEGEN_REGISTER_SCAVENGING_H
1818
1919 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
2021 #include "llvm/ADT/BitVector.h"
2122
2223 namespace llvm {
5758 /// CalleeSavedrRegs - A bitvector of callee saved registers for the target.
5859 ///
5960 BitVector CalleeSavedRegs;
60
61 /// ReservedRegs - A bitvector of reserved registers.
62 ///
63 BitVector ReservedRegs;
6461
6562 /// RegsAvailable - The current state of all the physical registers immediately
6663 /// before MBBI. One bit per physical register. If bit is set that means it's
129126 void setUsed(unsigned Reg);
130127 private:
131128 /// isReserved - Returns true if a register is reserved. It is never "unused".
132 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); }
129 bool isReserved(unsigned Reg) const { return MRI->isReserved(Reg); }
133130
134131 /// isUsed / isUnused - Test if a register is currently being used.
135132 ///
136133 bool isUsed(unsigned Reg) const {
137 return !RegsAvailable.test(Reg) || ReservedRegs.test(Reg);
134 return !RegsAvailable.test(Reg) || isReserved(Reg);
138135 }
139136
140137 /// isAliasUsed - Is Reg or an alias currently in use?
3232 const MachineRegisterInfo *MRI;
3333 const TargetInstrInfo *TII;
3434 BitVector LivePhysRegs;
35 BitVector ReservedRegs;
3635
3736 public:
3837 static char ID; // Pass identification, replacement for typeid
6968 unsigned Reg = MO.getReg();
7069 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
7170 // Don't delete live physreg defs, or any reserved register defs.
72 if (LivePhysRegs.test(Reg) || ReservedRegs.test(Reg))
71 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg))
7372 return false;
7473 } else {
7574 if (!MRI->use_nodbg_empty(Reg))
8988 TRI = MF.getTarget().getRegisterInfo();
9089 TII = MF.getTarget().getInstrInfo();
9190
92 // Treat reserved registers as always live.
93 ReservedRegs = TRI->getReservedRegs(MF);
94
9591 // Loop over all instructions in all blocks, from bottom to top, so that it's
9692 // more likely that chains of dependent but ultimately dead instructions will
9793 // be cleaned up.
10096 MachineBasicBlock *MBB = &*I;
10197
10298 // Start out assuming that reserved registers are live out of this block.
103 LivePhysRegs = ReservedRegs;
99 LivePhysRegs = MRI->getReservedRegs();
104100
105101 // Also add any explicit live-out physregs for this block.
106102 if (!MBB->empty() && MBB->back().isReturn())
502502 MRI = &mf.getRegInfo();
503503 TRI = MF->getTarget().getRegisterInfo();
504504
505 ReservedRegisters = TRI->getReservedRegs(mf);
506
507505 unsigned NumRegs = TRI->getNumRegs();
508506 PhysRegDef = new MachineInstr*[NumRegs];
509507 PhysRegUse = new MachineInstr*[NumRegs];
587585 unsigned MOReg = UseRegs[i];
588586 if (TargetRegisterInfo::isVirtualRegister(MOReg))
589587 HandleVirtRegUse(MOReg, MBB, MI);
590 else if (!ReservedRegisters[MOReg])
588 else if (!MRI->isReserved(MOReg))
591589 HandlePhysRegUse(MOReg, MI);
592590 }
593591
600598 unsigned MOReg = DefRegs[i];
601599 if (TargetRegisterInfo::isVirtualRegister(MOReg))
602600 HandleVirtRegDef(MOReg, MI);
603 else if (!ReservedRegisters[MOReg])
601 else if (!MRI->isReserved(MOReg))
604602 HandlePhysRegDef(MOReg, MI, Defs);
605603 }
606604 UpdatePhysRegDefs(MI, Defs);
6363 ScopeMap.clear();
6464 Exps.clear();
6565 AllocatableRegs.clear();
66 ReservedRegs.clear();
6766 }
6867
6968 private:
7877 SmallVector Exps;
7978 unsigned CurrVN;
8079 BitVector AllocatableRegs;
81 BitVector ReservedRegs;
8280
8381 bool PerformTrivialCoalescing(MachineInstr *MI, MachineBasicBlock *MBB);
8482 bool isPhysDefTriviallyDead(unsigned Reg,
241239 return false;
242240
243241 for (unsigned i = 0, e = PhysDefs.size(); i != e; ++i) {
244 if (AllocatableRegs.test(PhysDefs[i]) || ReservedRegs.test(PhysDefs[i]))
242 if (MRI->isAllocatable(PhysDefs[i]) || MRI->isReserved(PhysDefs[i]))
245243 // Avoid extending live range of physical registers if they are
246244 //allocatable or reserved.
247245 return false;
635633 AA = &getAnalysis();
636634 DT = &getAnalysis();
637635 AllocatableRegs = TRI->getAllocatableSet(MF);
638 ReservedRegs = TRI->getReservedRegs(MF);
639636 return PerformCSE(DT->getRootNode());
640637 }
1515 #include "llvm/Pass.h"
1616 #include "llvm/CodeGen/MachineFunction.h"
1717 #include "llvm/CodeGen/MachineFunctionPass.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
1819 #include "llvm/Target/TargetRegisterInfo.h"
1920 #include "llvm/Support/Debug.h"
2021 #include "llvm/Support/ErrorHandling.h"
3132 namespace {
3233 class MachineCopyPropagation : public MachineFunctionPass {
3334 const TargetRegisterInfo *TRI;
34 BitVector ReservedRegs;
35 MachineRegisterInfo *MRI;
3536
3637 public:
3738 static char ID; // Pass identification, replacement for typeid
145146 DenseMap::iterator CI = AvailCopyMap.find(Src);
146147 if (CI != AvailCopyMap.end()) {
147148 MachineInstr *CopyMI = CI->second;
148 if (!ReservedRegs.test(Def) &&
149 (!ReservedRegs.test(Src) || NoInterveningSideEffect(CopyMI, MI)) &&
149 if (!MRI->isReserved(Def) &&
150 (!MRI->isReserved(Src) || NoInterveningSideEffect(CopyMI, MI)) &&
150151 isNopCopy(CopyMI, Def, Src, TRI)) {
151152 // The two copies cancel out and the source of the first copy
152153 // hasn't been overridden, eliminate the second one. e.g.
258259 DI = MaybeDeadCopies.begin(), DE = MaybeDeadCopies.end();
259260 DI != DE; ++DI) {
260261 unsigned Reg = (*DI)->getOperand(0).getReg();
261 if (ReservedRegs.test(Reg) || !MaskMO.clobbersPhysReg(Reg))
262 if (MRI->isReserved(Reg) || !MaskMO.clobbersPhysReg(Reg))
262263 continue;
263264 (*DI)->eraseFromParent();
264265 Changed = true;
295296 for (SmallSetVector::iterator
296297 DI = MaybeDeadCopies.begin(), DE = MaybeDeadCopies.end();
297298 DI != DE; ++DI) {
298 if (!ReservedRegs.test((*DI)->getOperand(0).getReg())) {
299 if (!MRI->isReserved((*DI)->getOperand(0).getReg())) {
299300 (*DI)->eraseFromParent();
300301 Changed = true;
301302 ++NumDeletes;
310311 bool Changed = false;
311312
312313 TRI = MF.getTarget().getRegisterInfo();
313 ReservedRegs = TRI->getReservedRegs(MF);
314 MRI = &MF.getRegInfo();
314315
315316 for (MachineFunction::iterator I = MF.begin(), E = MF.end(); I != E; ++I)
316317 Changed |= CopyPropagateBlock(*I);
426426
427427 void MachineVerifier::visitMachineFunctionBefore() {
428428 lastIndex = SlotIndex();
429 regsReserved = TRI->getReservedRegs(*MF);
429 regsReserved = MRI->getReservedRegs();
430430
431431 // A sub-register of a reserved register is also reserved
432432 for (int Reg = regsReserved.find_first(); Reg>=0;
489489 DEBUG(dbgs() << "Fixup kills for BB#" << MBB->getNumber() << '\n');
490490
491491 BitVector killedRegs(TRI->getNumRegs());
492 BitVector ReservedRegs = TRI->getReservedRegs(MF);
493492
494493 StartBlockForKills(MBB);
495494
530529 MachineOperand &MO = MI->getOperand(i);
531530 if (!MO.isReg() || !MO.isUse()) continue;
532531 unsigned Reg = MO.getReg();
533 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
532 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
534533
535534 bool kill = false;
536535 if (!killedRegs.test(Reg)) {
565564 MachineOperand &MO = MI->getOperand(i);
566565 if (!MO.isReg() || !MO.isUse() || MO.isUndef()) continue;
567566 unsigned Reg = MO.getReg();
568 if ((Reg == 0) || ReservedRegs.test(Reg)) continue;
567 if ((Reg == 0) || MRI.isReserved(Reg)) continue;
569568
570569 LiveRegs.set(Reg);
571570
207207 mri->setPhysRegUsed(Reg);
208208 }
209209
210 BitVector reservedRegs = tri->getReservedRegs(*mf);
211
212210 // Iterate over vregs.
213211 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end();
214212 vregItr != vregEnd; ++vregItr) {
226224 ArrayRef rawOrder = trc->getRawAllocationOrder(*mf);
227225 for (unsigned i = 0; i != rawOrder.size(); ++i) {
228226 unsigned preg = rawOrder[i];
229 if (reservedRegs.test(preg))
227 if (mri->isReserved(preg))
230228 continue;
231229
232230 // vregLI crosses a regmask operand that clobbers preg.
1414 //===----------------------------------------------------------------------===//
1515
1616 #define DEBUG_TYPE "regalloc"
17 #include "llvm/CodeGen/RegisterClassInfo.h"
1718 #include "llvm/CodeGen/MachineFunction.h"
18 #include "llvm/CodeGen/RegisterClassInfo.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
1920 #include "llvm/Target/TargetMachine.h"
2021 #include "llvm/Support/CommandLine.h"
2122 #include "llvm/Support/Debug.h"
5657 CalleeSaved = CSR;
5758
5859 // Different reserved registers?
59 BitVector RR = TRI->getReservedRegs(*MF);
60 if (RR != Reserved)
60 const BitVector &RR = MF->getRegInfo().getReservedRegs();
61 if (Reserved.size() != RR.size() || RR != Reserved) {
6162 Update = true;
62 Reserved = RR;
63 Reserved = RR;
64 }
6365
6466 // Invalidate cached information from previous function.
6567 if (Update)
9090 RegsAvailable.resize(NumPhysRegs);
9191 KillRegs.resize(NumPhysRegs);
9292 DefRegs.resize(NumPhysRegs);
93
94 // Create reserved registers bitvector.
95 ReservedRegs = TRI->getReservedRegs(MF);
9693
9794 // Create callee-saved registers bitvector.
9895 CalleeSavedRegs.resize(NumPhysRegs);
224221 used = RegsAvailable;
225222 used.flip();
226223 if (includeReserved)
227 used |= ReservedRegs;
224 used |= MRI->getReservedRegs();
228225 else
229 used.reset(ReservedRegs);
226 used.reset(MRI->getReservedRegs());
230227 }
231228
232229 unsigned RegScavenger::FindUnusedReg(const TargetRegisterClass *RC) const {
256256 SmallVector SuperDeads;
257257 SmallVector SuperDefs;
258258 SmallVector SuperKills;
259 #ifndef NDEBUG
260 BitVector Reserved = TRI->getReservedRegs(*MF);
261 #endif
262259
263260 for (MachineFunction::iterator MBBI = MF->begin(), MBBE = MF->end();
264261 MBBI != MBBE; ++MBBI) {
282279 unsigned PhysReg = VRM->getPhys(VirtReg);
283280 assert(PhysReg != VirtRegMap::NO_PHYS_REG &&
284281 "Instruction uses unmapped VirtReg");
285 assert(!Reserved.test(PhysReg) && "Reserved register assignment");
282 assert(!MRI->isReserved(PhysReg) && "Reserved register assignment");
286283
287284 // Preserve semantics of sub-register operands.
288285 if (MO.getSubReg()) {