llvm.org GIT mirror llvm / fb662d9
Merging r223220: ------------------------------------------------------------------------ r223220 | hfinkel | 2014-12-03 09:37:50 +0000 (Wed, 03 Dec 2014) | 23 lines [PowerPC] Print all inline-asm consts as signed numbers Almost all immediates in PowerPC assembly (both 32-bit and 64-bit) are signed numbers, and it is important that we print them as such. To make sure that happens, we change PPCTargetLowering::LowerAsmOperandForConstraint so that it does all intermediate checks on a signed-extended int64_t value, and then creates the resulting target constant using MVT::i64. This will ensure that all negative values are printed as negative values (mirroring what is done in other backends to achieve the same sign-extension effect). This came up in the context of inline assembly like this: "add%I2 %0,%0,%2", ..., "Ir"(-1ll) where we used to print: addi 3,3,4294967295 and gcc would print: addi 3,3,-1 and gas accepts both forms, but our builtin assembler (correctly) does not. Now we print -1 like gcc does. While here, I replaced a bunch of custom integer checks with isInt<16> and friends from MathExtras.h. Thanks to Paul Hargrove for the bug report. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_35@223745 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 5 years ago
2 changed file(s) with 43 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
90019001 case 'P': {
90029002 ConstantSDNode *CST = dyn_cast(Op);
90039003 if (!CST) return; // Must be an immediate to match.
9004 unsigned Value = CST->getZExtValue();
9004 int64_t Value = CST->getSExtValue();
9005 EVT TCVT = MVT::i64; // All constants taken to be 64 bits so that negative
9006 // numbers are printed as such.
90059007 switch (Letter) {
90069008 default: llvm_unreachable("Unknown constraint letter!");
90079009 case 'I': // "I" is a signed 16-bit constant.
9008 if ((short)Value == (int)Value)
9009 Result = DAG.getTargetConstant(Value, Op.getValueType());
9010 if (isInt<16>(Value))
9011 Result = DAG.getTargetConstant(Value, TCVT);
90109012 break;
90119013 case 'J': // "J" is a constant with only the high-order 16 bits nonzero.
9014 if (isShiftedUInt<16, 16>(Value))
9015 Result = DAG.getTargetConstant(Value, TCVT);
9016 break;
90129017 case 'L': // "L" is a signed 16-bit constant shifted left 16 bits.
9013 if ((short)Value == 0)
9014 Result = DAG.getTargetConstant(Value, Op.getValueType());
9018 if (isShiftedInt<16, 16>(Value))
9019 Result = DAG.getTargetConstant(Value, TCVT);
90159020 break;
90169021 case 'K': // "K" is a constant with only the low-order 16 bits nonzero.
9017 if ((Value >> 16) == 0)
9018 Result = DAG.getTargetConstant(Value, Op.getValueType());
9022 if (isUInt<16>(Value))
9023 Result = DAG.getTargetConstant(Value, TCVT);
90199024 break;
90209025 case 'M': // "M" is a constant that is greater than 31.
90219026 if (Value > 31)
9022 Result = DAG.getTargetConstant(Value, Op.getValueType());
9027 Result = DAG.getTargetConstant(Value, TCVT);
90239028 break;
90249029 case 'N': // "N" is a positive constant that is an exact power of two.
9025 if ((int)Value > 0 && isPowerOf2_32(Value))
9026 Result = DAG.getTargetConstant(Value, Op.getValueType());
9030 if (Value > 0 && isPowerOf2_64(Value))
9031 Result = DAG.getTargetConstant(Value, TCVT);
90279032 break;
90289033 case 'O': // "O" is the constant zero.
90299034 if (Value == 0)
9030 Result = DAG.getTargetConstant(Value, Op.getValueType());
9035 Result = DAG.getTargetConstant(Value, TCVT);
90319036 break;
90329037 case 'P': // "P" is a constant whose negation is a signed 16-bit constant.
9033 if ((short)-Value == (int)-Value)
9034 Result = DAG.getTargetConstant(Value, Op.getValueType());
9038 if (isInt<16>(-Value))
9039 Result = DAG.getTargetConstant(Value, TCVT);
90359040 break;
90369041 }
90379042 break;
0 ; RUN: llc -mcpu=pwr7 < %s | FileCheck %s
1 target datalayout = "E-m:e-i64:64-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 @.str = private unnamed_addr constant [5 x i8] c"%ld\0A\00", align 1
5
6 ; Function Attrs: nounwind
7 define i64 @main() #0 {
8 entry:
9 %x = alloca i64, align 8
10 store i64 0, i64* %x, align 8
11 %0 = call i64 asm sideeffect "ld $0,$1\0A\09add${2:I} $0,$0,$2", "=&r,*m,Ir"(i64* %x, i64 -1) #0
12 ret i64 %0
13 }
14
15 ; CHECK: ld
16 ; CHECK-NOT: addi 3,3,4294967295
17 ; CHECK: addi 3,3,-1
18 ; CHECK: blr
19
20 ; Function Attrs: nounwind
21 declare signext i32 @printf(i8* nocapture readonly, ...) #0
22
23 attributes #0 = { nounwind }
24