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[X86][AVX] extract_subvector(any_extend(x)) -> any_extend_vector_inreg(x) Part of fixing the X86 regression noted in D63281 - I've split this into X86 and generic parts - the generic commit will be coming shortly and will fix the vector-reduce-mul-widen.ll regression introduced here. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@363693 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Pilgrim 5 months ago
2 changed file(s) with 11 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
68746874 return true;
68756875 }
68766876 case ISD::ZERO_EXTEND:
6877 case ISD::ANY_EXTEND:
68776878 case ISD::ZERO_EXTEND_VECTOR_INREG:
68786879 case ISD::ANY_EXTEND_VECTOR_INREG: {
68796880 SDValue Src = N.getOperand(0);
68856886 return false;
68866887
68876888 unsigned NumSrcBitsPerElt = SrcVT.getScalarSizeInBits();
6888 bool IsAnyExtend = (ISD::ANY_EXTEND_VECTOR_INREG == Opcode);
6889 bool IsAnyExtend =
6890 (ISD::ANY_EXTEND == Opcode || ISD::ANY_EXTEND_VECTOR_INREG == Opcode);
68896891 DecodeZeroExtendMask(NumSrcBitsPerElt, NumBitsPerElt, NumElts, IsAnyExtend,
68906892 Mask);
68916893
4354043542 InOpcode == ISD::SIGN_EXTEND) &&
4354143543 VT.is128BitVector() &&
4354243544 InVec.getOperand(0).getSimpleValueType().is128BitVector()) {
43543 unsigned ExtOp = InOpcode == ISD::SIGN_EXTEND
43544 ? ISD::SIGN_EXTEND_VECTOR_INREG
43545 : ISD::ZERO_EXTEND_VECTOR_INREG;
43545 unsigned ExtOp;
43546 switch(InOpcode) {
43547 default: llvm_unreachable("Unknown extension opcode");
43548 case ISD::ANY_EXTEND: ExtOp = ISD::ANY_EXTEND_VECTOR_INREG; break;
43549 case ISD::SIGN_EXTEND: ExtOp = ISD::SIGN_EXTEND_VECTOR_INREG; break;
43550 case ISD::ZERO_EXTEND: ExtOp = ISD::ZERO_EXTEND_VECTOR_INREG; break;
43551 }
4354643552 return DAG.getNode(ExtOp, SDLoc(N), VT, InVec.getOperand(0));
4354743553 }
4354843554 if ((InOpcode == ISD::ANY_EXTEND_VECTOR_INREG ||
18361836 ; AVX2-NEXT: vpand %xmm1, %xmm0, %xmm0
18371837 ; AVX2-NEXT: vpackuswb %xmm0, %xmm0, %xmm1
18381838 ; AVX2-NEXT: vpsrlw $8, %xmm1, %xmm1
1839 ; AVX2-NEXT: vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
18391840 ; AVX2-NEXT: vpmullw %xmm1, %xmm0, %xmm0
18401841 ; AVX2-NEXT: vpextrb $0, %xmm0, %eax
18411842 ; AVX2-NEXT: # kill: def $al killed $al killed $eax