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[ARM] Handling for coprocessor instructions that are undefined starting from ARMv8 (ARM encodings) git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194261 91177308-0d34-0410-b5e6-96231b3b80d8 Artyom Skrobov 6 years ago
3 changed file(s) with 59 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
46754675 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
46764676 NoItinerary, "cdp", "\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
46774677 [(int_arm_cdp imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4678 imm:$CRm, imm:$opc2)]> {
4678 imm:$CRm, imm:$opc2)]>,
4679 Requires<[PreV8]> {
46794680 bits<4> opc1;
46804681 bits<4> CRn;
46814682 bits<4> CRd;
46964697 c_imm:$CRd, c_imm:$CRn, c_imm:$CRm, imm0_7:$opc2),
46974698 NoItinerary, "cdp2\t$cop, $opc1, $CRd, $CRn, $CRm, $opc2",
46984699 [(int_arm_cdp2 imm:$cop, imm:$opc1, imm:$CRd, imm:$CRn,
4699 imm:$CRm, imm:$opc2)]> {
4700 imm:$CRm, imm:$opc2)]>,
4701 Requires<[PreV8]> {
47004702 let Inst{31-28} = 0b1111;
47014703 bits<4> opc1;
47024704 bits<4> CRn;
48744876 defm LDCL : LdStCop <1, 1, "ldcl">;
48754877 defm STC : LdStCop <0, 0, "stc">;
48764878 defm STCL : LdStCop <0, 1, "stcl">;
4877 defm LDC2 : LdSt2Cop<1, 0, "ldc2">;
4878 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">;
4879 defm STC2 : LdSt2Cop<0, 0, "stc2">;
4880 defm STC2L : LdSt2Cop<0, 1, "stc2l">;
4879 defm LDC2 : LdSt2Cop<1, 0, "ldc2">, Requires<[PreV8]>;
4880 defm LDC2L : LdSt2Cop<1, 1, "ldc2l">, Requires<[PreV8]>;
4881 defm STC2 : LdSt2Cop<0, 0, "stc2">, Requires<[PreV8]>;
4882 defm STC2L : LdSt2Cop<0, 1, "stc2l">, Requires<[PreV8]>;
48814883
48824884 //===----------------------------------------------------------------------===//
48834885 // Move between coprocessor and ARM core register.
49544956 (ins p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
49554957 c_imm:$CRm, imm0_7:$opc2),
49564958 [(int_arm_mcr2 imm:$cop, imm:$opc1, GPR:$Rt, imm:$CRn,
4957 imm:$CRm, imm:$opc2)]>;
4959 imm:$CRm, imm:$opc2)]>,
4960 Requires<[PreV8]>;
49584961 def : ARMInstAlias<"mcr2$ $cop, $opc1, $Rt, $CRn, $CRm",
49594962 (MCR2 p_imm:$cop, imm0_7:$opc1, GPR:$Rt, c_imm:$CRn,
49604963 c_imm:$CRm, 0)>;
49614964 def MRC2 : MovRCopro2<"mrc2", 1 /* from coprocessor to ARM core register */,
49624965 (outs GPRwithAPSR:$Rt),
49634966 (ins p_imm:$cop, imm0_7:$opc1, c_imm:$CRn, c_imm:$CRm,
4964 imm0_7:$opc2), []>;
4967 imm0_7:$opc2), []>,
4968 Requires<[PreV8]>;
49654969 def : ARMInstAlias<"mrc2$ $cop, $opc1, $Rt, $CRn, $CRm",
49664970 (MRC2 GPRwithAPSR:$Rt, p_imm:$cop, imm0_7:$opc1, c_imm:$CRn,
49674971 c_imm:$CRm, 0)>;
49985002 class MovRRCopro2 pattern = []>
49995003 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
50005004 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
5001 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
5005 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern>,
5006 Requires<[PreV8]> {
50025007 let Inst{31-28} = 0b1111;
50035008 let Inst{23-21} = 0b010;
50045009 let Inst{20} = direction;
13611361 default:
13621362 break;
13631363 }
1364
1365 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
1366 .getFeatureBits();
1367 if ((featureBits & ARM::HasV8Ops) && (coproc != 14))
1368 return MCDisassembler::Fail;
13641369
13651370 Inst.addOperand(MCOperand::CreateImm(coproc));
13661371 Inst.addOperand(MCOperand::CreateImm(CRd));
38133818 if (Val == 0xA || Val == 0xB)
38143819 return MCDisassembler::Fail;
38153820
3821 uint64_t featureBits = ((const MCDisassembler*)Decoder)->getSubtargetInfo()
3822 .getFeatureBits();
3823 if ((featureBits & ARM::HasV8Ops) && !(Val == 14 || Val == 15))
3824 return MCDisassembler::Fail;
3825
38163826 Inst.addOperand(MCOperand::CreateImm(Val));
38173827 return MCDisassembler::Success;
38183828 }
2020
2121 0x05 0xf0 0x20 0xe3
2222 # CHECK: sevl
23
24
25 # These are the only coprocessor instructions that remain defined in ARMv8
26 # (The operations on p10/p11 disassemble into FP/NEON instructions)
27
28 0x10 0x0e 0x00 0xee
29 # CHECK: mcr p14
30
31 0x10 0x0f 0x00 0xee
32 # CHECK: mcr p15
33
34 0x10 0x0e 0x10 0xee
35 # CHECK: mrc p14
36
37 0x10 0x0f 0x10 0xee
38 # CHECK: mrc p15
39
40 0x00 0x0e 0x40 0xec
41 # CHECK: mcrr p14
42
43 0x00 0x0f 0x40 0xec
44 # CHECK: mcrr p15
45
46 0x00 0x0e 0x50 0xec
47 # CHECK: mrrc p14
48
49 0x00 0x0f 0x50 0xec
50 # CHECK: mrrc p15
51
52 0x00 0x0e 0x80 0xec
53 # CHECK: stc p14
54
55 0x00 0x0e 0x90 0xec
56 # CHECK: ldc p14
57