llvm.org GIT mirror llvm / fa5bd27
Add mcr* and mr*c support to thumb targets git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@123917 91177308-0d34-0410-b5e6-96231b3b80d8 Bruno Cardoso Lopes 9 years ago
4 changed file(s) with 81 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
798798 let Inst{31-27} = opcod1;
799799 let Inst{15-14} = opcod2;
800800 let Inst{12} = opcod3;
801 }
802
803 // Move to/from coprocessor instructions
804 class T1Cop pattern>
805 : ThumbI,
806 Encoding, Requires<[IsThumb, HasV6]> {
807 let Inst{31-28} = 0b1110;
801808 }
802809
803810 // BR_JT instructions
13221322 Size2Bytes, IIC_iALUi, []>;
13231323
13241324 //===----------------------------------------------------------------------===//
1325 // Move between coprocessor and ARM core register -- for disassembly only
1326 //
1327
1328 class tMovRCopro
1329 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1,
1330 GPR:$Rt, c_imm:$CRn, c_imm:$CRm, i32imm:$opc2),
1331 !strconcat(opc, "\t$cop, $opc1, $Rt, $CRn, $CRm, $opc2"),
1332 [/* For disassembly only; pattern left blank */]> {
1333 let Inst{27-24} = 0b1110;
1334 let Inst{20} = direction;
1335 let Inst{4} = 1;
1336
1337 bits<4> Rt;
1338 bits<4> cop;
1339 bits<3> opc1;
1340 bits<3> opc2;
1341 bits<4> CRm;
1342 bits<4> CRn;
1343
1344 let Inst{15-12} = Rt;
1345 let Inst{11-8} = cop;
1346 let Inst{23-21} = opc1;
1347 let Inst{7-5} = opc2;
1348 let Inst{3-0} = CRm;
1349 let Inst{19-16} = CRn;
1350 }
1351
1352 def tMCR : tMovRCopro<"mcr", 0 /* from ARM core register to coprocessor */>;
1353 def tMRC : tMovRCopro<"mrc", 1 /* from coprocessor to ARM core register */>;
1354
1355 class tMovRRCopro
1356 : T1Cop<(outs), (ins p_imm:$cop, i32imm:$opc1, GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
1357 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"),
1358 [/* For disassembly only; pattern left blank */]> {
1359 let Inst{27-24} = 0b1100;
1360 let Inst{23-21} = 0b010;
1361 let Inst{20} = direction;
1362
1363 bits<4> Rt;
1364 bits<4> Rt2;
1365 bits<4> cop;
1366 bits<4> opc1;
1367 bits<4> CRm;
1368
1369 let Inst{15-12} = Rt;
1370 let Inst{19-16} = Rt2;
1371 let Inst{11-8} = cop;
1372 let Inst{7-4} = opc1;
1373 let Inst{3-0} = CRm;
1374 }
1375
1376 def tMCRR : tMovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */>;
1377 def tMRRC : tMovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
1378
1379 //===----------------------------------------------------------------------===//
13251380 // TLS Instructions
13261381 //
13271382
11921192 Mnemonic == "cps" || Mnemonic == "mcr2" || Mnemonic == "it" ||
11931193 Mnemonic == "mcrr2" || Mnemonic == "cbz" || Mnemonic == "cdp2" ||
11941194 Mnemonic == "trap" || Mnemonic == "mrc2" || Mnemonic == "mrrc2" ||
1195 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb" ||
1196 (isThumb && Mnemonic == "bkpt")) {
1195 Mnemonic == "dsb" || Mnemonic == "movs" || Mnemonic == "isb") {
11971196 CanAcceptPredicationCode = false;
11981197 } else {
11991198 CanAcceptPredicationCode = true;
12001199 }
1200
1201 if (isThumb)
1202 if (Mnemonic == "bkpt" || Mnemonic == "mcr" || Mnemonic == "mcrr" ||
1203 Mnemonic == "mrc" || Mnemonic == "mrrc")
1204 CanAcceptPredicationCode = false;
12011205 }
12021206
12031207 /// Parse an arm instruction mnemonic followed by its operands.
3737
3838 @ CHECK: bkpt #2 @ encoding: [0x02,0xbe]
3939 bkpt #2
40
41 @ CHECK: mcr p7, #1, r5, c1, c1, #4 @ encoding: [0x21,0xee,0x91,0x57]
42 mcr p7, #1, r5, c1, c1, #4
43
44 @ CHECK: mrc p14, #0, r1, c1, c2, #4 @ encoding: [0x11,0xee,0x92,0x1e]
45 mrc p14, #0, r1, c1, c2, #4
46
47 @ CHECK: mcrr p7, #1, r5, r4, c1 @ encoding: [0x44,0xec,0x11,0x57]
48 mcrr p7, #1, r5, r4, c1
49
50 @ CHECK: mrrc p7, #1, r5, r4, c1 @ encoding: [0x54,0xec,0x11,0x57]
51 mrrc p7, #1, r5, r4, c1
52