llvm.org GIT mirror llvm / fa2d986
Move the guts of TargetInstrInfoImpl into the TargetInstrInfo class. The *Impl class no longer serves a purpose now that the super-class implementation is in CodeGen. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@168759 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 8 years ago
4 changed file(s) with 686 addition(s) and 793 deletion(s). Raw diff Collapse all Expand all
142142 /// missed.
143143 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
144144 const MachineMemOperand *&MMO,
145 int &FrameIndex) const {
146 return 0;
147 }
145 int &FrameIndex) const;
148146
149147 /// isStoreToStackSlot - If the specified machine instruction is a direct
150148 /// store to a stack slot, return the virtual or physical register number of
172170 /// stack. This is just a hint, as some cases may be missed.
173171 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
174172 const MachineMemOperand *&MMO,
175 int &FrameIndex) const {
176 return 0;
177 }
173 int &FrameIndex) const;
178174
179175 /// reMaterialize - Re-issue the specified 'original' instruction at the
180176 /// specific location targeting a new destination register.
185181 MachineBasicBlock::iterator MI,
186182 unsigned DestReg, unsigned SubIdx,
187183 const MachineInstr *Orig,
188 const TargetRegisterInfo &TRI) const = 0;
184 const TargetRegisterInfo &TRI) const;
189185
190186 /// duplicate - Create a duplicate of the Orig instruction in MF. This is like
191187 /// MachineFunction::CloneMachineInstr(), but the target may update operands
193189 ///
194190 /// The instruction must be duplicable as indicated by isNotDuplicable().
195191 virtual MachineInstr *duplicate(MachineInstr *Orig,
196 MachineFunction &MF) const = 0;
192 MachineFunction &MF) const;
197193
198194 /// convertToThreeAddress - This method must be implemented by targets that
199195 /// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
220216 /// method for a non-commutable instruction, but there may be some cases
221217 /// where this method fails and returns null.
222218 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
223 bool NewMI = false) const = 0;
219 bool NewMI = false) const;
224220
225221 /// findCommutedOpIndices - If specified MI is commutable, return the two
226222 /// operand indices that would swap value. Return false if the instruction
227223 /// is not in a form which this routine understands.
228224 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
229 unsigned &SrcOpIdx2) const = 0;
225 unsigned &SrcOpIdx2) const;
230226
231227 /// produceSameValue - Return true if two machine instructions would produce
232228 /// identical values. By default, this is only true when the two instructions
235231 /// aggressive checks.
236232 virtual bool produceSameValue(const MachineInstr *MI0,
237233 const MachineInstr *MI1,
238 const MachineRegisterInfo *MRI = 0) const = 0;
234 const MachineRegisterInfo *MRI = 0) const;
239235
240236 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
241237 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
297293 /// after it, replacing it with an unconditional branch to NewDest. This is
298294 /// used by the tail merging pass.
299295 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
300 MachineBasicBlock *NewDest) const = 0;
296 MachineBasicBlock *NewDest) const;
301297
302298 /// isLegalToSplitMBBAt - Return true if it's legal to split the given basic
303299 /// block at the specified instruction (i.e. instruction would be the start
568564 /// folding is possible.
569565 virtual
570566 bool canFoldMemoryOperand(const MachineInstr *MI,
571 const SmallVectorImpl &Ops) const =0;
567 const SmallVectorImpl &Ops) const;
572568
573569 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
574570 /// a store or a load and a store into two or more instruction. If this is
668664
669665 /// isUnpredicatedTerminator - Returns true if the instruction is a
670666 /// terminator instruction that has not been predicated.
671 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const = 0;
667 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
672668
673669 /// PredicateInstruction - Convert the instruction into a predicated
674670 /// instruction. It returns true if the operation was successful.
675671 virtual
676672 bool PredicateInstruction(MachineInstr *MI,
677 const SmallVectorImpl &Pred) const = 0;
673 const SmallVectorImpl &Pred) const;
678674
679675 /// SubsumesPredicate - Returns true if the first specified predicate
680676 /// subsumes the second, e.g. GE subsumes GT.
710706 /// terminators.
711707 virtual bool isSchedulingBoundary(const MachineInstr *MI,
712708 const MachineBasicBlock *MBB,
713 const MachineFunction &MF) const = 0;
709 const MachineFunction &MF) const;
714710
715711 /// Measure the specified inline asm to determine an approximation of its
716712 /// length.
722718 /// register allocation.
723719 virtual ScheduleHazardRecognizer*
724720 CreateTargetHazardRecognizer(const TargetMachine *TM,
725 const ScheduleDAG *DAG) const = 0;
721 const ScheduleDAG *DAG) const;
726722
727723 /// CreateTargetMIHazardRecognizer - Allocate and return a hazard recognizer
728724 /// to use for this target when scheduling the machine instructions before
729725 /// register allocation.
730726 virtual ScheduleHazardRecognizer*
731727 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
732 const ScheduleDAG *DAG) const = 0;
728 const ScheduleDAG *DAG) const;
733729
734730 /// CreateTargetPostRAHazardRecognizer - Allocate and return a hazard
735731 /// recognizer to use for this target when scheduling the machine instructions
736732 /// after register allocation.
737733 virtual ScheduleHazardRecognizer*
738734 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
739 const ScheduleDAG *DAG) const = 0;
735 const ScheduleDAG *DAG) const;
736
737 /// Provide a global flag for disabling the PreRA hazard recognizer that
738 /// targets may choose to honor.
739 bool usePreRAHazardRecognizer() const;
740740
741741 /// analyzeCompare - For a comparison instruction, return the source registers
742742 /// in SrcReg and SrcReg2 if having two register operands, and the value it
784784 /// IssueWidth is the number of microops that can be dispatched each
785785 /// cycle. An instruction with zero microops takes no dispatch resources.
786786 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
787 const MachineInstr *MI) const = 0;
787 const MachineInstr *MI) const;
788788
789789 /// isZeroCost - Return true for pseudo instructions that don't consume any
790790 /// machine resources in their current form. These are common cases that the
796796
797797 virtual int getOperandLatency(const InstrItineraryData *ItinData,
798798 SDNode *DefNode, unsigned DefIdx,
799 SDNode *UseNode, unsigned UseIdx) const = 0;
799 SDNode *UseNode, unsigned UseIdx) const;
800800
801801 /// getOperandLatency - Compute and return the use operand latency of a given
802802 /// pair of def and use.
809809 virtual int getOperandLatency(const InstrItineraryData *ItinData,
810810 const MachineInstr *DefMI, unsigned DefIdx,
811811 const MachineInstr *UseMI,
812 unsigned UseIdx) const = 0;
812 unsigned UseIdx) const;
813813
814814 /// computeOperandLatency - Compute and return the latency of the given data
815815 /// dependent def and use when the operand indices are already known.
825825 /// PredCost.
826826 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
827827 const MachineInstr *MI,
828 unsigned *PredCost = 0) const = 0;
828 unsigned *PredCost = 0) const;
829829
830830 virtual int getInstrLatency(const InstrItineraryData *ItinData,
831 SDNode *Node) const = 0;
831 SDNode *Node) const;
832832
833833 /// Return the default expected latency for a def based on it's opcode.
834834 unsigned defaultDefLatency(const MCSchedModel *SchedModel,
858858 /// if the target considered it 'low'.
859859 virtual
860860 bool hasLowDefLatency(const InstrItineraryData *ItinData,
861 const MachineInstr *DefMI, unsigned DefIdx) const = 0;
861 const MachineInstr *DefMI, unsigned DefIdx) const;
862862
863863 /// verifyInstruction - Perform target specific instruction verification.
864864 virtual
975975 int CallFrameSetupOpcode, CallFrameDestroyOpcode;
976976 };
977977
978 /// TargetInstrInfoImpl - This is the default implementation of
979 /// TargetInstrInfo, which just provides a couple of default implementations
980 /// for various methods. This separated out because it is implemented in
981 /// libcodegen, not in libtarget.
982 class TargetInstrInfoImpl : public TargetInstrInfo {
983 protected:
984 TargetInstrInfoImpl(int CallFrameSetupOpcode = -1,
985 int CallFrameDestroyOpcode = -1)
986 : TargetInstrInfo(CallFrameSetupOpcode, CallFrameDestroyOpcode) {}
987 public:
988 virtual void ReplaceTailWithBranchTo(MachineBasicBlock::iterator OldInst,
989 MachineBasicBlock *NewDest) const;
990 virtual MachineInstr *commuteInstruction(MachineInstr *MI,
991 bool NewMI = false) const;
992 virtual bool findCommutedOpIndices(MachineInstr *MI, unsigned &SrcOpIdx1,
993 unsigned &SrcOpIdx2) const;
994 virtual bool canFoldMemoryOperand(const MachineInstr *MI,
995 const SmallVectorImpl &Ops) const;
996 virtual bool hasLoadFromStackSlot(const MachineInstr *MI,
997 const MachineMemOperand *&MMO,
998 int &FrameIndex) const;
999 virtual bool hasStoreToStackSlot(const MachineInstr *MI,
1000 const MachineMemOperand *&MMO,
1001 int &FrameIndex) const;
1002 virtual bool isUnpredicatedTerminator(const MachineInstr *MI) const;
1003 virtual bool PredicateInstruction(MachineInstr *MI,
1004 const SmallVectorImpl &Pred) const;
1005 virtual void reMaterialize(MachineBasicBlock &MBB,
1006 MachineBasicBlock::iterator MI,
1007 unsigned DestReg, unsigned SubReg,
1008 const MachineInstr *Orig,
1009 const TargetRegisterInfo &TRI) const;
1010 virtual MachineInstr *duplicate(MachineInstr *Orig,
1011 MachineFunction &MF) const;
1012 virtual bool produceSameValue(const MachineInstr *MI0,
1013 const MachineInstr *MI1,
1014 const MachineRegisterInfo *MRI) const;
1015 virtual bool isSchedulingBoundary(const MachineInstr *MI,
1016 const MachineBasicBlock *MBB,
1017 const MachineFunction &MF) const;
1018
1019 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1020 SDNode *DefNode, unsigned DefIdx,
1021 SDNode *UseNode, unsigned UseIdx) const;
1022
1023 virtual int getInstrLatency(const InstrItineraryData *ItinData,
1024 SDNode *Node) const;
1025
1026 virtual unsigned getNumMicroOps(const InstrItineraryData *ItinData,
1027 const MachineInstr *MI) const;
1028
1029 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1030 const MachineInstr *MI,
1031 unsigned *PredCost = 0) const;
1032
1033 virtual
1034 bool hasLowDefLatency(const InstrItineraryData *ItinData,
1035 const MachineInstr *DefMI, unsigned DefIdx) const;
1036
1037 virtual int getOperandLatency(const InstrItineraryData *ItinData,
1038 const MachineInstr *DefMI, unsigned DefIdx,
1039 const MachineInstr *UseMI,
1040 unsigned UseIdx) const;
1041
1042 bool usePreRAHazardRecognizer() const;
1043
1044 virtual ScheduleHazardRecognizer *
1045 CreateTargetHazardRecognizer(const TargetMachine*, const ScheduleDAG*) const;
1046
1047 virtual ScheduleHazardRecognizer *
1048 CreateTargetMIHazardRecognizer(const InstrItineraryData*,
1049 const ScheduleDAG*) const;
1050
1051 virtual ScheduleHazardRecognizer *
1052 CreateTargetPostRAHazardRecognizer(const InstrItineraryData*,
1053 const ScheduleDAG*) const;
1054 };
978 // Temporary typedef until all TargetInstrInfoImpl references are gone.
979 typedef TargetInstrInfo TargetInstrInfoImpl;
1055980
1056981 } // End llvm namespace
1057982
9999 TailDuplication.cpp
100100 TargetFrameLoweringImpl.cpp
101101 TargetInstrInfo.cpp
102 TargetInstrInfoImpl.cpp
103102 TargetLoweringObjectFileImpl.cpp
104103 TargetOptionsImpl.cpp
105104 TargetRegisterInfo.cpp
1111 //===----------------------------------------------------------------------===//
1212
1313 #include "llvm/Target/TargetInstrInfo.h"
14 #include "llvm/Target/TargetRegisterInfo.h"
14 #include "llvm/CodeGen/MachineFrameInfo.h"
15 #include "llvm/CodeGen/MachineMemOperand.h"
16 #include "llvm/CodeGen/MachineRegisterInfo.h"
17 #include "llvm/CodeGen/PseudoSourceValue.h"
18 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
1519 #include "llvm/MC/MCAsmInfo.h"
1620 #include "llvm/MC/MCInstrItineraries.h"
21 #include "llvm/Support/CommandLine.h"
1722 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/raw_ostream.h"
24 #include "llvm/Target/TargetRegisterInfo.h"
25 #include "llvm/Target/TargetLowering.h"
26 #include "llvm/Target/TargetMachine.h"
1827 #include
1928 using namespace llvm;
2029
21 //===----------------------------------------------------------------------===//
22 // TargetInstrInfo
23 //
24 // Methods that depend on CodeGen are implemented in
25 // TargetInstrInfoImpl.cpp. Invoking them without linking libCodeGen raises a
26 // link error.
27 // ===----------------------------------------------------------------------===//
30 static cl::opt DisableHazardRecognizer(
31 "disable-sched-hazard", cl::Hidden, cl::init(false),
32 cl::desc("Disable hazard detection during preRA scheduling"));
2833
2934 TargetInstrInfo::~TargetInstrInfo() {
3035 }
8590
8691 return Length;
8792 }
93
94 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
95 /// after it, replacing it with an unconditional branch to NewDest.
96 void
97 TargetInstrInfo::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
98 MachineBasicBlock *NewDest) const {
99 MachineBasicBlock *MBB = Tail->getParent();
100
101 // Remove all the old successors of MBB from the CFG.
102 while (!MBB->succ_empty())
103 MBB->removeSuccessor(MBB->succ_begin());
104
105 // Remove all the dead instructions from the end of MBB.
106 MBB->erase(Tail, MBB->end());
107
108 // If MBB isn't immediately before MBB, insert a branch to it.
109 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
110 InsertBranch(*MBB, NewDest, 0, SmallVector(),
111 Tail->getDebugLoc());
112 MBB->addSuccessor(NewDest);
113 }
114
115 // commuteInstruction - The default implementation of this method just exchanges
116 // the two operands returned by findCommutedOpIndices.
117 MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI,
118 bool NewMI) const {
119 const MCInstrDesc &MCID = MI->getDesc();
120 bool HasDef = MCID.getNumDefs();
121 if (HasDef && !MI->getOperand(0).isReg())
122 // No idea how to commute this instruction. Target should implement its own.
123 return 0;
124 unsigned Idx1, Idx2;
125 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
126 std::string msg;
127 raw_string_ostream Msg(msg);
128 Msg << "Don't know how to commute: " << *MI;
129 report_fatal_error(Msg.str());
130 }
131
132 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
133 "This only knows how to commute register operands so far");
134 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
135 unsigned Reg1 = MI->getOperand(Idx1).getReg();
136 unsigned Reg2 = MI->getOperand(Idx2).getReg();
137 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
138 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
139 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
140 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
141 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
142 // If destination is tied to either of the commuted source register, then
143 // it must be updated.
144 if (HasDef && Reg0 == Reg1 &&
145 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
146 Reg2IsKill = false;
147 Reg0 = Reg2;
148 SubReg0 = SubReg2;
149 } else if (HasDef && Reg0 == Reg2 &&
150 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
151 Reg1IsKill = false;
152 Reg0 = Reg1;
153 SubReg0 = SubReg1;
154 }
155
156 if (NewMI) {
157 // Create a new instruction.
158 MachineFunction &MF = *MI->getParent()->getParent();
159 MI = MF.CloneMachineInstr(MI);
160 }
161
162 if (HasDef) {
163 MI->getOperand(0).setReg(Reg0);
164 MI->getOperand(0).setSubReg(SubReg0);
165 }
166 MI->getOperand(Idx2).setReg(Reg1);
167 MI->getOperand(Idx1).setReg(Reg2);
168 MI->getOperand(Idx2).setSubReg(SubReg1);
169 MI->getOperand(Idx1).setSubReg(SubReg2);
170 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
171 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
172 return MI;
173 }
174
175 /// findCommutedOpIndices - If specified MI is commutable, return the two
176 /// operand indices that would swap value. Return true if the instruction
177 /// is not in a form which this routine understands.
178 bool TargetInstrInfo::findCommutedOpIndices(MachineInstr *MI,
179 unsigned &SrcOpIdx1,
180 unsigned &SrcOpIdx2) const {
181 assert(!MI->isBundle() &&
182 "TargetInstrInfo::findCommutedOpIndices() can't handle bundles");
183
184 const MCInstrDesc &MCID = MI->getDesc();
185 if (!MCID.isCommutable())
186 return false;
187 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
188 // is not true, then the target must implement this.
189 SrcOpIdx1 = MCID.getNumDefs();
190 SrcOpIdx2 = SrcOpIdx1 + 1;
191 if (!MI->getOperand(SrcOpIdx1).isReg() ||
192 !MI->getOperand(SrcOpIdx2).isReg())
193 // No idea.
194 return false;
195 return true;
196 }
197
198
199 bool
200 TargetInstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
201 if (!MI->isTerminator()) return false;
202
203 // Conditional branch is a special case.
204 if (MI->isBranch() && !MI->isBarrier())
205 return true;
206 if (!MI->isPredicable())
207 return true;
208 return !isPredicated(MI);
209 }
210
211
212 bool TargetInstrInfo::PredicateInstruction(MachineInstr *MI,
213 const SmallVectorImpl &Pred) const {
214 bool MadeChange = false;
215
216 assert(!MI->isBundle() &&
217 "TargetInstrInfo::PredicateInstruction() can't handle bundles");
218
219 const MCInstrDesc &MCID = MI->getDesc();
220 if (!MI->isPredicable())
221 return false;
222
223 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
224 if (MCID.OpInfo[i].isPredicate()) {
225 MachineOperand &MO = MI->getOperand(i);
226 if (MO.isReg()) {
227 MO.setReg(Pred[j].getReg());
228 MadeChange = true;
229 } else if (MO.isImm()) {
230 MO.setImm(Pred[j].getImm());
231 MadeChange = true;
232 } else if (MO.isMBB()) {
233 MO.setMBB(Pred[j].getMBB());
234 MadeChange = true;
235 }
236 ++j;
237 }
238 }
239 return MadeChange;
240 }
241
242 bool TargetInstrInfo::hasLoadFromStackSlot(const MachineInstr *MI,
243 const MachineMemOperand *&MMO,
244 int &FrameIndex) const {
245 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
246 oe = MI->memoperands_end();
247 o != oe;
248 ++o) {
249 if ((*o)->isLoad() && (*o)->getValue())
250 if (const FixedStackPseudoSourceValue *Value =
251 dyn_cast((*o)->getValue())) {
252 FrameIndex = Value->getFrameIndex();
253 MMO = *o;
254 return true;
255 }
256 }
257 return false;
258 }
259
260 bool TargetInstrInfo::hasStoreToStackSlot(const MachineInstr *MI,
261 const MachineMemOperand *&MMO,
262 int &FrameIndex) const {
263 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
264 oe = MI->memoperands_end();
265 o != oe;
266 ++o) {
267 if ((*o)->isStore() && (*o)->getValue())
268 if (const FixedStackPseudoSourceValue *Value =
269 dyn_cast((*o)->getValue())) {
270 FrameIndex = Value->getFrameIndex();
271 MMO = *o;
272 return true;
273 }
274 }
275 return false;
276 }
277
278 void TargetInstrInfo::reMaterialize(MachineBasicBlock &MBB,
279 MachineBasicBlock::iterator I,
280 unsigned DestReg,
281 unsigned SubIdx,
282 const MachineInstr *Orig,
283 const TargetRegisterInfo &TRI) const {
284 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
285 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
286 MBB.insert(I, MI);
287 }
288
289 bool
290 TargetInstrInfo::produceSameValue(const MachineInstr *MI0,
291 const MachineInstr *MI1,
292 const MachineRegisterInfo *MRI) const {
293 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
294 }
295
296 MachineInstr *TargetInstrInfo::duplicate(MachineInstr *Orig,
297 MachineFunction &MF) const {
298 assert(!Orig->isNotDuplicable() &&
299 "Instruction cannot be duplicated");
300 return MF.CloneMachineInstr(Orig);
301 }
302
303 // If the COPY instruction in MI can be folded to a stack operation, return
304 // the register class to use.
305 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
306 unsigned FoldIdx) {
307 assert(MI->isCopy() && "MI must be a COPY instruction");
308 if (MI->getNumOperands() != 2)
309 return 0;
310 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
311
312 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
313 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
314
315 if (FoldOp.getSubReg() || LiveOp.getSubReg())
316 return 0;
317
318 unsigned FoldReg = FoldOp.getReg();
319 unsigned LiveReg = LiveOp.getReg();
320
321 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
322 "Cannot fold physregs");
323
324 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
325 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
326
327 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
328 return RC->contains(LiveOp.getReg()) ? RC : 0;
329
330 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
331 return RC;
332
333 // FIXME: Allow folding when register classes are memory compatible.
334 return 0;
335 }
336
337 bool TargetInstrInfo::
338 canFoldMemoryOperand(const MachineInstr *MI,
339 const SmallVectorImpl &Ops) const {
340 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
341 }
342
343 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
344 /// slot into the specified machine instruction for the specified operand(s).
345 /// If this is possible, a new instruction is returned with the specified
346 /// operand folded, otherwise NULL is returned. The client is responsible for
347 /// removing the old instruction and adding the new one in the instruction
348 /// stream.
349 MachineInstr*
350 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
351 const SmallVectorImpl &Ops,
352 int FI) const {
353 unsigned Flags = 0;
354 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
355 if (MI->getOperand(Ops[i]).isDef())
356 Flags |= MachineMemOperand::MOStore;
357 else
358 Flags |= MachineMemOperand::MOLoad;
359
360 MachineBasicBlock *MBB = MI->getParent();
361 assert(MBB && "foldMemoryOperand needs an inserted instruction");
362 MachineFunction &MF = *MBB->getParent();
363
364 // Ask the target to do the actual folding.
365 if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
366 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
367 assert((!(Flags & MachineMemOperand::MOStore) ||
368 NewMI->mayStore()) &&
369 "Folded a def to a non-store!");
370 assert((!(Flags & MachineMemOperand::MOLoad) ||
371 NewMI->mayLoad()) &&
372 "Folded a use to a non-load!");
373 const MachineFrameInfo &MFI = *MF.getFrameInfo();
374 assert(MFI.getObjectOffset(FI) != -1);
375 MachineMemOperand *MMO =
376 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
377 Flags, MFI.getObjectSize(FI),
378 MFI.getObjectAlignment(FI));
379 NewMI->addMemOperand(MF, MMO);
380
381 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
382 return MBB->insert(MI, NewMI);
383 }
384
385 // Straight COPY may fold as load/store.
386 if (!MI->isCopy() || Ops.size() != 1)
387 return 0;
388
389 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
390 if (!RC)
391 return 0;
392
393 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
394 MachineBasicBlock::iterator Pos = MI;
395 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
396
397 if (Flags == MachineMemOperand::MOStore)
398 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
399 else
400 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
401 return --Pos;
402 }
403
404 /// foldMemoryOperand - Same as the previous version except it allows folding
405 /// of any load and store from / to any address, not just from a specific
406 /// stack slot.
407 MachineInstr*
408 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
409 const SmallVectorImpl &Ops,
410 MachineInstr* LoadMI) const {
411 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
412 #ifndef NDEBUG
413 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
414 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
415 #endif
416 MachineBasicBlock &MBB = *MI->getParent();
417 MachineFunction &MF = *MBB.getParent();
418
419 // Ask the target to do the actual folding.
420 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
421 if (!NewMI) return 0;
422
423 NewMI = MBB.insert(MI, NewMI);
424
425 // Copy the memoperands from the load to the folded instruction.
426 NewMI->setMemRefs(LoadMI->memoperands_begin(),
427 LoadMI->memoperands_end());
428
429 return NewMI;
430 }
431
432 bool TargetInstrInfo::
433 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
434 AliasAnalysis *AA) const {
435 const MachineFunction &MF = *MI->getParent()->getParent();
436 const MachineRegisterInfo &MRI = MF.getRegInfo();
437 const TargetMachine &TM = MF.getTarget();
438 const TargetInstrInfo &TII = *TM.getInstrInfo();
439
440 // Remat clients assume operand 0 is the defined register.
441 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
442 return false;
443 unsigned DefReg = MI->getOperand(0).getReg();
444
445 // A sub-register definition can only be rematerialized if the instruction
446 // doesn't read the other parts of the register. Otherwise it is really a
447 // read-modify-write operation on the full virtual register which cannot be
448 // moved safely.
449 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
450 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
451 return false;
452
453 // A load from a fixed stack slot can be rematerialized. This may be
454 // redundant with subsequent checks, but it's target-independent,
455 // simple, and a common case.
456 int FrameIdx = 0;
457 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
458 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
459 return true;
460
461 // Avoid instructions obviously unsafe for remat.
462 if (MI->isNotDuplicable() || MI->mayStore() ||
463 MI->hasUnmodeledSideEffects())
464 return false;
465
466 // Don't remat inline asm. We have no idea how expensive it is
467 // even if it's side effect free.
468 if (MI->isInlineAsm())
469 return false;
470
471 // Avoid instructions which load from potentially varying memory.
472 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
473 return false;
474
475 // If any of the registers accessed are non-constant, conservatively assume
476 // the instruction is not rematerializable.
477 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
478 const MachineOperand &MO = MI->getOperand(i);
479 if (!MO.isReg()) continue;
480 unsigned Reg = MO.getReg();
481 if (Reg == 0)
482 continue;
483
484 // Check for a well-behaved physical register.
485 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
486 if (MO.isUse()) {
487 // If the physreg has no defs anywhere, it's just an ambient register
488 // and we can freely move its uses. Alternatively, if it's allocatable,
489 // it could get allocated to something with a def during allocation.
490 if (!MRI.isConstantPhysReg(Reg, MF))
491 return false;
492 } else {
493 // A physreg def. We can't remat it.
494 return false;
495 }
496 continue;
497 }
498
499 // Only allow one virtual-register def. There may be multiple defs of the
500 // same virtual register, though.
501 if (MO.isDef() && Reg != DefReg)
502 return false;
503
504 // Don't allow any virtual-register uses. Rematting an instruction with
505 // virtual register uses would length the live ranges of the uses, which
506 // is not necessarily a good idea, certainly not "trivial".
507 if (MO.isUse())
508 return false;
509 }
510
511 // Everything checked out.
512 return true;
513 }
514
515 /// isSchedulingBoundary - Test if the given instruction should be
516 /// considered a scheduling boundary. This primarily includes labels
517 /// and terminators.
518 bool TargetInstrInfo::isSchedulingBoundary(const MachineInstr *MI,
519 const MachineBasicBlock *MBB,
520 const MachineFunction &MF) const {
521 // Terminators and labels can't be scheduled around.
522 if (MI->isTerminator() || MI->isLabel())
523 return true;
524
525 // Don't attempt to schedule around any instruction that defines
526 // a stack-oriented pointer, as it's unlikely to be profitable. This
527 // saves compile time, because it doesn't require every single
528 // stack slot reference to depend on the instruction that does the
529 // modification.
530 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
531 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
532 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
533 return true;
534
535 return false;
536 }
537
538 // Provide a global flag for disabling the PreRA hazard recognizer that targets
539 // may choose to honor.
540 bool TargetInstrInfo::usePreRAHazardRecognizer() const {
541 return !DisableHazardRecognizer;
542 }
543
544 // Default implementation of CreateTargetRAHazardRecognizer.
545 ScheduleHazardRecognizer *TargetInstrInfo::
546 CreateTargetHazardRecognizer(const TargetMachine *TM,
547 const ScheduleDAG *DAG) const {
548 // Dummy hazard recognizer allows all instructions to issue.
549 return new ScheduleHazardRecognizer();
550 }
551
552 // Default implementation of CreateTargetMIHazardRecognizer.
553 ScheduleHazardRecognizer *TargetInstrInfo::
554 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
555 const ScheduleDAG *DAG) const {
556 return (ScheduleHazardRecognizer *)
557 new ScoreboardHazardRecognizer(II, DAG, "misched");
558 }
559
560 // Default implementation of CreateTargetPostRAHazardRecognizer.
561 ScheduleHazardRecognizer *TargetInstrInfo::
562 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
563 const ScheduleDAG *DAG) const {
564 return (ScheduleHazardRecognizer *)
565 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
566 }
567
568 //===----------------------------------------------------------------------===//
569 // SelectionDAG latency interface.
570 //===----------------------------------------------------------------------===//
571
572 int
573 TargetInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
574 SDNode *DefNode, unsigned DefIdx,
575 SDNode *UseNode, unsigned UseIdx) const {
576 if (!ItinData || ItinData->isEmpty())
577 return -1;
578
579 if (!DefNode->isMachineOpcode())
580 return -1;
581
582 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
583 if (!UseNode->isMachineOpcode())
584 return ItinData->getOperandCycle(DefClass, DefIdx);
585 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
586 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
587 }
588
589 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
590 SDNode *N) const {
591 if (!ItinData || ItinData->isEmpty())
592 return 1;
593
594 if (!N->isMachineOpcode())
595 return 1;
596
597 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
598 }
599
600 //===----------------------------------------------------------------------===//
601 // MachineInstr latency interface.
602 //===----------------------------------------------------------------------===//
603
604 unsigned
605 TargetInstrInfo::getNumMicroOps(const InstrItineraryData *ItinData,
606 const MachineInstr *MI) const {
607 if (!ItinData || ItinData->isEmpty())
608 return 1;
609
610 unsigned Class = MI->getDesc().getSchedClass();
611 int UOps = ItinData->Itineraries[Class].NumMicroOps;
612 if (UOps >= 0)
613 return UOps;
614
615 // The # of u-ops is dynamically determined. The specific target should
616 // override this function to return the right number.
617 return 1;
618 }
619
620 /// Return the default expected latency for a def based on it's opcode.
621 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
622 const MachineInstr *DefMI) const {
623 if (DefMI->isTransient())
624 return 0;
625 if (DefMI->mayLoad())
626 return SchedModel->LoadLatency;
627 if (isHighLatencyDef(DefMI->getOpcode()))
628 return SchedModel->HighLatency;
629 return 1;
630 }
631
632 unsigned TargetInstrInfo::
633 getInstrLatency(const InstrItineraryData *ItinData,
634 const MachineInstr *MI,
635 unsigned *PredCost) const {
636 // Default to one cycle for no itinerary. However, an "empty" itinerary may
637 // still have a MinLatency property, which getStageLatency checks.
638 if (!ItinData)
639 return MI->mayLoad() ? 2 : 1;
640
641 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
642 }
643
644 bool TargetInstrInfo::hasLowDefLatency(const InstrItineraryData *ItinData,
645 const MachineInstr *DefMI,
646 unsigned DefIdx) const {
647 if (!ItinData || ItinData->isEmpty())
648 return false;
649
650 unsigned DefClass = DefMI->getDesc().getSchedClass();
651 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
652 return (DefCycle != -1 && DefCycle <= 1);
653 }
654
655 /// Both DefMI and UseMI must be valid. By default, call directly to the
656 /// itinerary. This may be overriden by the target.
657 int TargetInstrInfo::
658 getOperandLatency(const InstrItineraryData *ItinData,
659 const MachineInstr *DefMI, unsigned DefIdx,
660 const MachineInstr *UseMI, unsigned UseIdx) const {
661 unsigned DefClass = DefMI->getDesc().getSchedClass();
662 unsigned UseClass = UseMI->getDesc().getSchedClass();
663 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
664 }
665
666 /// If we can determine the operand latency from the def only, without itinerary
667 /// lookup, do so. Otherwise return -1.
668 int TargetInstrInfo::computeDefOperandLatency(
669 const InstrItineraryData *ItinData,
670 const MachineInstr *DefMI, bool FindMin) const {
671
672 // Let the target hook getInstrLatency handle missing itineraries.
673 if (!ItinData)
674 return getInstrLatency(ItinData, DefMI);
675
676 // Return a latency based on the itinerary properties and defining instruction
677 // if possible. Some common subtargets don't require per-operand latency,
678 // especially for minimum latencies.
679 if (FindMin) {
680 // If MinLatency is valid, call getInstrLatency. This uses Stage latency if
681 // it exists before defaulting to MinLatency.
682 if (ItinData->SchedModel->MinLatency >= 0)
683 return getInstrLatency(ItinData, DefMI);
684
685 // If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
686 // For empty itineraries, short-cirtuit the check and default to one cycle.
687 if (ItinData->isEmpty())
688 return 1;
689 }
690 else if(ItinData->isEmpty())
691 return defaultDefLatency(ItinData->SchedModel, DefMI);
692
693 // ...operand lookup required
694 return -1;
695 }
696
697 /// computeOperandLatency - Compute and return the latency of the given data
698 /// dependent def and use when the operand indices are already known. UseMI may
699 /// be NULL for an unknown use.
700 ///
701 /// FindMin may be set to get the minimum vs. expected latency. Minimum
702 /// latency is used for scheduling groups, while expected latency is for
703 /// instruction cost and critical path.
704 ///
705 /// Depending on the subtarget's itinerary properties, this may or may not need
706 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
707 /// UseIdx to compute min latency.
708 unsigned TargetInstrInfo::
709 computeOperandLatency(const InstrItineraryData *ItinData,
710 const MachineInstr *DefMI, unsigned DefIdx,
711 const MachineInstr *UseMI, unsigned UseIdx,
712 bool FindMin) const {
713
714 int DefLatency = computeDefOperandLatency(ItinData, DefMI, FindMin);
715 if (DefLatency >= 0)
716 return DefLatency;
717
718 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
719
720 int OperLatency = 0;
721 if (UseMI)
722 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
723 else {
724 unsigned DefClass = DefMI->getDesc().getSchedClass();
725 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
726 }
727 if (OperLatency >= 0)
728 return OperLatency;
729
730 // No operand latency was found.
731 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
732
733 // Expected latency is the max of the stage latency and itinerary props.
734 if (!FindMin)
735 InstrLatency = std::max(InstrLatency,
736 defaultDefLatency(ItinData->SchedModel, DefMI));
737 return InstrLatency;
738 }
+0
-682
lib/CodeGen/TargetInstrInfoImpl.cpp less more
None //===-- TargetInstrInfoImpl.cpp - Target Instruction Information ----------===//
1 //
2 // The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file implements the TargetInstrInfoImpl class, it just provides default
10 // implementations of various methods.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "llvm/Target/TargetInstrInfo.h"
15 #include "llvm/Target/TargetLowering.h"
16 #include "llvm/Target/TargetMachine.h"
17 #include "llvm/Target/TargetRegisterInfo.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineMemOperand.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/ScoreboardHazardRecognizer.h"
25 #include "llvm/CodeGen/PseudoSourceValue.h"
26 #include "llvm/MC/MCInstrItineraries.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/Debug.h"
29 #include "llvm/Support/ErrorHandling.h"
30 #include "llvm/Support/raw_ostream.h"
31 using namespace llvm;
32
33 static cl::opt DisableHazardRecognizer(
34 "disable-sched-hazard", cl::Hidden, cl::init(false),
35 cl::desc("Disable hazard detection during preRA scheduling"));
36
37 /// ReplaceTailWithBranchTo - Delete the instruction OldInst and everything
38 /// after it, replacing it with an unconditional branch to NewDest.
39 void
40 TargetInstrInfoImpl::ReplaceTailWithBranchTo(MachineBasicBlock::iterator Tail,
41 MachineBasicBlock *NewDest) const {
42 MachineBasicBlock *MBB = Tail->getParent();
43
44 // Remove all the old successors of MBB from the CFG.
45 while (!MBB->succ_empty())
46 MBB->removeSuccessor(MBB->succ_begin());
47
48 // Remove all the dead instructions from the end of MBB.
49 MBB->erase(Tail, MBB->end());
50
51 // If MBB isn't immediately before MBB, insert a branch to it.
52 if (++MachineFunction::iterator(MBB) != MachineFunction::iterator(NewDest))
53 InsertBranch(*MBB, NewDest, 0, SmallVector(),
54 Tail->getDebugLoc());
55 MBB->addSuccessor(NewDest);
56 }
57
58 // commuteInstruction - The default implementation of this method just exchanges
59 // the two operands returned by findCommutedOpIndices.
60 MachineInstr *TargetInstrInfoImpl::commuteInstruction(MachineInstr *MI,
61 bool NewMI) const {
62 const MCInstrDesc &MCID = MI->getDesc();
63 bool HasDef = MCID.getNumDefs();
64 if (HasDef && !MI->getOperand(0).isReg())
65 // No idea how to commute this instruction. Target should implement its own.
66 return 0;
67 unsigned Idx1, Idx2;
68 if (!findCommutedOpIndices(MI, Idx1, Idx2)) {
69 std::string msg;
70 raw_string_ostream Msg(msg);
71 Msg << "Don't know how to commute: " << *MI;
72 report_fatal_error(Msg.str());
73 }
74
75 assert(MI->getOperand(Idx1).isReg() && MI->getOperand(Idx2).isReg() &&
76 "This only knows how to commute register operands so far");
77 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
78 unsigned Reg1 = MI->getOperand(Idx1).getReg();
79 unsigned Reg2 = MI->getOperand(Idx2).getReg();
80 unsigned SubReg0 = HasDef ? MI->getOperand(0).getSubReg() : 0;
81 unsigned SubReg1 = MI->getOperand(Idx1).getSubReg();
82 unsigned SubReg2 = MI->getOperand(Idx2).getSubReg();
83 bool Reg1IsKill = MI->getOperand(Idx1).isKill();
84 bool Reg2IsKill = MI->getOperand(Idx2).isKill();
85 // If destination is tied to either of the commuted source register, then
86 // it must be updated.
87 if (HasDef && Reg0 == Reg1 &&
88 MI->getDesc().getOperandConstraint(Idx1, MCOI::TIED_TO) == 0) {
89 Reg2IsKill = false;
90 Reg0 = Reg2;
91 SubReg0 = SubReg2;
92 } else if (HasDef && Reg0 == Reg2 &&
93 MI->getDesc().getOperandConstraint(Idx2, MCOI::TIED_TO) == 0) {
94 Reg1IsKill = false;
95 Reg0 = Reg1;
96 SubReg0 = SubReg1;
97 }
98
99 if (NewMI) {
100 // Create a new instruction.
101 MachineFunction &MF = *MI->getParent()->getParent();
102 MI = MF.CloneMachineInstr(MI);
103 }
104
105 if (HasDef) {
106 MI->getOperand(0).setReg(Reg0);
107 MI->getOperand(0).setSubReg(SubReg0);
108 }
109 MI->getOperand(Idx2).setReg(Reg1);
110 MI->getOperand(Idx1).setReg(Reg2);
111 MI->getOperand(Idx2).setSubReg(SubReg1);
112 MI->getOperand(Idx1).setSubReg(SubReg2);
113 MI->getOperand(Idx2).setIsKill(Reg1IsKill);
114 MI->getOperand(Idx1).setIsKill(Reg2IsKill);
115 return MI;
116 }
117
118 /// findCommutedOpIndices - If specified MI is commutable, return the two
119 /// operand indices that would swap value. Return true if the instruction
120 /// is not in a form which this routine understands.
121 bool TargetInstrInfoImpl::findCommutedOpIndices(MachineInstr *MI,
122 unsigned &SrcOpIdx1,
123 unsigned &SrcOpIdx2) const {
124 assert(!MI->isBundle() &&
125 "TargetInstrInfoImpl::findCommutedOpIndices() can't handle bundles");
126
127 const MCInstrDesc &MCID = MI->getDesc();
128 if (!MCID.isCommutable())
129 return false;
130 // This assumes v0 = op v1, v2 and commuting would swap v1 and v2. If this
131 // is not true, then the target must implement this.
132 SrcOpIdx1 = MCID.getNumDefs();
133 SrcOpIdx2 = SrcOpIdx1 + 1;
134 if (!MI->getOperand(SrcOpIdx1).isReg() ||
135 !MI->getOperand(SrcOpIdx2).isReg())
136 // No idea.
137 return false;
138 return true;
139 }
140
141
142 bool
143 TargetInstrInfoImpl::isUnpredicatedTerminator(const MachineInstr *MI) const {
144 if (!MI->isTerminator()) return false;
145
146 // Conditional branch is a special case.
147 if (MI->isBranch() && !MI->isBarrier())
148 return true;
149 if (!MI->isPredicable())
150 return true;
151 return !isPredicated(MI);
152 }
153
154
155 bool TargetInstrInfoImpl::PredicateInstruction(MachineInstr *MI,
156 const SmallVectorImpl &Pred) const {
157 bool MadeChange = false;
158
159 assert(!MI->isBundle() &&
160 "TargetInstrInfoImpl::PredicateInstruction() can't handle bundles");
161
162 const MCInstrDesc &MCID = MI->getDesc();
163 if (!MI->isPredicable())
164 return false;
165
166 for (unsigned j = 0, i = 0, e = MI->getNumOperands(); i != e; ++i) {
167 if (MCID.OpInfo[i].isPredicate()) {
168 MachineOperand &MO = MI->getOperand(i);
169 if (MO.isReg()) {
170 MO.setReg(Pred[j].getReg());
171 MadeChange = true;
172 } else if (MO.isImm()) {
173 MO.setImm(Pred[j].getImm());
174 MadeChange = true;
175 } else if (MO.isMBB()) {
176 MO.setMBB(Pred[j].getMBB());
177 MadeChange = true;
178 }
179 ++j;
180 }
181 }
182 return MadeChange;
183 }
184
185 bool TargetInstrInfoImpl::hasLoadFromStackSlot(const MachineInstr *MI,
186 const MachineMemOperand *&MMO,
187 int &FrameIndex) const {
188 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
189 oe = MI->memoperands_end();
190 o != oe;
191 ++o) {
192 if ((*o)->isLoad() && (*o)->getValue())
193 if (const FixedStackPseudoSourceValue *Value =
194 dyn_cast((*o)->getValue())) {
195 FrameIndex = Value->getFrameIndex();
196 MMO = *o;
197 return true;
198 }
199 }
200 return false;
201 }
202
203 bool TargetInstrInfoImpl::hasStoreToStackSlot(const MachineInstr *MI,
204 const MachineMemOperand *&MMO,
205 int &FrameIndex) const {
206 for (MachineInstr::mmo_iterator o = MI->memoperands_begin(),
207 oe = MI->memoperands_end();
208 o != oe;
209 ++o) {
210 if ((*o)->isStore() && (*o)->getValue())
211 if (const FixedStackPseudoSourceValue *Value =
212 dyn_cast((*o)->getValue())) {
213 FrameIndex = Value->getFrameIndex();
214 MMO = *o;
215 return true;
216 }
217 }
218 return false;
219 }
220
221 void TargetInstrInfoImpl::reMaterialize(MachineBasicBlock &MBB,
222 MachineBasicBlock::iterator I,
223 unsigned DestReg,
224 unsigned SubIdx,
225 const MachineInstr *Orig,
226 const TargetRegisterInfo &TRI) const {
227 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
228 MI->substituteRegister(MI->getOperand(0).getReg(), DestReg, SubIdx, TRI);
229 MBB.insert(I, MI);
230 }
231
232 bool
233 TargetInstrInfoImpl::produceSameValue(const MachineInstr *MI0,
234 const MachineInstr *MI1,
235 const MachineRegisterInfo *MRI) const {
236 return MI0->isIdenticalTo(MI1, MachineInstr::IgnoreVRegDefs);
237 }
238
239 MachineInstr *TargetInstrInfoImpl::duplicate(MachineInstr *Orig,
240 MachineFunction &MF) const {
241 assert(!Orig->isNotDuplicable() &&
242 "Instruction cannot be duplicated");
243 return MF.CloneMachineInstr(Orig);
244 }
245
246 // If the COPY instruction in MI can be folded to a stack operation, return
247 // the register class to use.
248 static const TargetRegisterClass *canFoldCopy(const MachineInstr *MI,
249 unsigned FoldIdx) {
250 assert(MI->isCopy() && "MI must be a COPY instruction");
251 if (MI->getNumOperands() != 2)
252 return 0;
253 assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
254
255 const MachineOperand &FoldOp = MI->getOperand(FoldIdx);
256 const MachineOperand &LiveOp = MI->getOperand(1-FoldIdx);
257
258 if (FoldOp.getSubReg() || LiveOp.getSubReg())
259 return 0;
260
261 unsigned FoldReg = FoldOp.getReg();
262 unsigned LiveReg = LiveOp.getReg();
263
264 assert(TargetRegisterInfo::isVirtualRegister(FoldReg) &&
265 "Cannot fold physregs");
266
267 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo();
268 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg);
269
270 if (TargetRegisterInfo::isPhysicalRegister(LiveOp.getReg()))
271 return RC->contains(LiveOp.getReg()) ? RC : 0;
272
273 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg)))
274 return RC;
275
276 // FIXME: Allow folding when register classes are memory compatible.
277 return 0;
278 }
279
280 bool TargetInstrInfoImpl::
281 canFoldMemoryOperand(const MachineInstr *MI,
282 const SmallVectorImpl &Ops) const {
283 return MI->isCopy() && Ops.size() == 1 && canFoldCopy(MI, Ops[0]);
284 }
285
286 /// foldMemoryOperand - Attempt to fold a load or store of the specified stack
287 /// slot into the specified machine instruction for the specified operand(s).
288 /// If this is possible, a new instruction is returned with the specified
289 /// operand folded, otherwise NULL is returned. The client is responsible for
290 /// removing the old instruction and adding the new one in the instruction
291 /// stream.
292 MachineInstr*
293 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
294 const SmallVectorImpl &Ops,
295 int FI) const {
296 unsigned Flags = 0;
297 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
298 if (MI->getOperand(Ops[i]).isDef())
299 Flags |= MachineMemOperand::MOStore;
300 else
301 Flags |= MachineMemOperand::MOLoad;
302
303 MachineBasicBlock *MBB = MI->getParent();
304 assert(MBB && "foldMemoryOperand needs an inserted instruction");
305 MachineFunction &MF = *MBB->getParent();
306
307 // Ask the target to do the actual folding.
308 if (MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, FI)) {
309 // Add a memory operand, foldMemoryOperandImpl doesn't do that.
310 assert((!(Flags & MachineMemOperand::MOStore) ||
311 NewMI->mayStore()) &&
312 "Folded a def to a non-store!");
313 assert((!(Flags & MachineMemOperand::MOLoad) ||
314 NewMI->mayLoad()) &&
315 "Folded a use to a non-load!");
316 const MachineFrameInfo &MFI = *MF.getFrameInfo();
317 assert(MFI.getObjectOffset(FI) != -1);
318 MachineMemOperand *MMO =
319 MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FI),
320 Flags, MFI.getObjectSize(FI),
321 MFI.getObjectAlignment(FI));
322 NewMI->addMemOperand(MF, MMO);
323
324 // FIXME: change foldMemoryOperandImpl semantics to also insert NewMI.
325 return MBB->insert(MI, NewMI);
326 }
327
328 // Straight COPY may fold as load/store.
329 if (!MI->isCopy() || Ops.size() != 1)
330 return 0;
331
332 const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
333 if (!RC)
334 return 0;
335
336 const MachineOperand &MO = MI->getOperand(1-Ops[0]);
337 MachineBasicBlock::iterator Pos = MI;
338 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
339
340 if (Flags == MachineMemOperand::MOStore)
341 storeRegToStackSlot(*MBB, Pos, MO.getReg(), MO.isKill(), FI, RC, TRI);
342 else
343 loadRegFromStackSlot(*MBB, Pos, MO.getReg(), FI, RC, TRI);
344 return --Pos;
345 }
346
347 /// foldMemoryOperand - Same as the previous version except it allows folding
348 /// of any load and store from / to any address, not just from a specific
349 /// stack slot.
350 MachineInstr*
351 TargetInstrInfo::foldMemoryOperand(MachineBasicBlock::iterator MI,
352 const SmallVectorImpl &Ops,
353 MachineInstr* LoadMI) const {
354 assert(LoadMI->canFoldAsLoad() && "LoadMI isn't foldable!");
355 #ifndef NDEBUG
356 for (unsigned i = 0, e = Ops.size(); i != e; ++i)
357 assert(MI->getOperand(Ops[i]).isUse() && "Folding load into def!");
358 #endif
359 MachineBasicBlock &MBB = *MI->getParent();
360 MachineFunction &MF = *MBB.getParent();
361
362 // Ask the target to do the actual folding.
363 MachineInstr *NewMI = foldMemoryOperandImpl(MF, MI, Ops, LoadMI);
364 if (!NewMI) return 0;
365
366 NewMI = MBB.insert(MI, NewMI);
367
368 // Copy the memoperands from the load to the folded instruction.
369 NewMI->setMemRefs(LoadMI->memoperands_begin(),
370 LoadMI->memoperands_end());
371
372 return NewMI;
373 }
374
375 bool TargetInstrInfo::
376 isReallyTriviallyReMaterializableGeneric(const MachineInstr *MI,
377 AliasAnalysis *AA) const {
378 const MachineFunction &MF = *MI->getParent()->getParent();
379 const MachineRegisterInfo &MRI = MF.getRegInfo();
380 const TargetMachine &TM = MF.getTarget();
381 const TargetInstrInfo &TII = *TM.getInstrInfo();
382
383 // Remat clients assume operand 0 is the defined register.
384 if (!MI->getNumOperands() || !MI->getOperand(0).isReg())
385 return false;
386 unsigned DefReg = MI->getOperand(0).getReg();
387
388 // A sub-register definition can only be rematerialized if the instruction
389 // doesn't read the other parts of the register. Otherwise it is really a
390 // read-modify-write operation on the full virtual register which cannot be
391 // moved safely.
392 if (TargetRegisterInfo::isVirtualRegister(DefReg) &&
393 MI->getOperand(0).getSubReg() && MI->readsVirtualRegister(DefReg))
394 return false;
395
396 // A load from a fixed stack slot can be rematerialized. This may be
397 // redundant with subsequent checks, but it's target-independent,
398 // simple, and a common case.
399 int FrameIdx = 0;
400 if (TII.isLoadFromStackSlot(MI, FrameIdx) &&
401 MF.getFrameInfo()->isImmutableObjectIndex(FrameIdx))
402 return true;
403
404 // Avoid instructions obviously unsafe for remat.
405 if (MI->isNotDuplicable() || MI->mayStore() ||
406 MI->hasUnmodeledSideEffects())
407 return false;
408
409 // Don't remat inline asm. We have no idea how expensive it is
410 // even if it's side effect free.
411 if (MI->isInlineAsm())
412 return false;
413
414 // Avoid instructions which load from potentially varying memory.
415 if (MI->mayLoad() && !MI->isInvariantLoad(AA))
416 return false;
417
418 // If any of the registers accessed are non-constant, conservatively assume
419 // the instruction is not rematerializable.
420 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
421 const MachineOperand &MO = MI->getOperand(i);
422 if (!MO.isReg()) continue;
423 unsigned Reg = MO.getReg();
424 if (Reg == 0)
425 continue;
426
427 // Check for a well-behaved physical register.
428 if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
429 if (MO.isUse()) {
430 // If the physreg has no defs anywhere, it's just an ambient register
431 // and we can freely move its uses. Alternatively, if it's allocatable,
432 // it could get allocated to something with a def during allocation.
433 if (!MRI.isConstantPhysReg(Reg, MF))
434 return false;
435 } else {
436 // A physreg def. We can't remat it.
437 return false;
438 }
439 continue;
440 }
441
442 // Only allow one virtual-register def. There may be multiple defs of the
443 // same virtual register, though.
444 if (MO.isDef() && Reg != DefReg)
445 return false;
446
447 // Don't allow any virtual-register uses. Rematting an instruction with
448 // virtual register uses would length the live ranges of the uses, which
449 // is not necessarily a good idea, certainly not "trivial".
450 if (MO.isUse())
451 return false;
452 }
453
454 // Everything checked out.
455 return true;
456 }
457
458 /// isSchedulingBoundary - Test if the given instruction should be
459 /// considered a scheduling boundary. This primarily includes labels
460 /// and terminators.
461 bool TargetInstrInfoImpl::isSchedulingBoundary(const MachineInstr *MI,
462 const MachineBasicBlock *MBB,
463 const MachineFunction &MF) const{
464 // Terminators and labels can't be scheduled around.
465 if (MI->isTerminator() || MI->isLabel())
466 return true;
467
468 // Don't attempt to schedule around any instruction that defines
469 // a stack-oriented pointer, as it's unlikely to be profitable. This
470 // saves compile time, because it doesn't require every single
471 // stack slot reference to depend on the instruction that does the
472 // modification.
473 const TargetLowering &TLI = *MF.getTarget().getTargetLowering();
474 const TargetRegisterInfo *TRI = MF.getTarget().getRegisterInfo();
475 if (MI->modifiesRegister(TLI.getStackPointerRegisterToSaveRestore(), TRI))
476 return true;
477
478 return false;
479 }
480
481 // Provide a global flag for disabling the PreRA hazard recognizer that targets
482 // may choose to honor.
483 bool TargetInstrInfoImpl::usePreRAHazardRecognizer() const {
484 return !DisableHazardRecognizer;
485 }
486
487 // Default implementation of CreateTargetRAHazardRecognizer.
488 ScheduleHazardRecognizer *TargetInstrInfoImpl::
489 CreateTargetHazardRecognizer(const TargetMachine *TM,
490 const ScheduleDAG *DAG) const {
491 // Dummy hazard recognizer allows all instructions to issue.
492 return new ScheduleHazardRecognizer();
493 }
494
495 // Default implementation of CreateTargetMIHazardRecognizer.
496 ScheduleHazardRecognizer *TargetInstrInfoImpl::
497 CreateTargetMIHazardRecognizer(const InstrItineraryData *II,
498 const ScheduleDAG *DAG) const {
499 return (ScheduleHazardRecognizer *)
500 new ScoreboardHazardRecognizer(II, DAG, "misched");
501 }
502
503 // Default implementation of CreateTargetPostRAHazardRecognizer.
504 ScheduleHazardRecognizer *TargetInstrInfoImpl::
505 CreateTargetPostRAHazardRecognizer(const InstrItineraryData *II,
506 const ScheduleDAG *DAG) const {
507 return (ScheduleHazardRecognizer *)
508 new ScoreboardHazardRecognizer(II, DAG, "post-RA-sched");
509 }
510
511 //===----------------------------------------------------------------------===//
512 // SelectionDAG latency interface.
513 //===----------------------------------------------------------------------===//
514
515 int
516 TargetInstrInfoImpl::getOperandLatency(const InstrItineraryData *ItinData,
517 SDNode *DefNode, unsigned DefIdx,
518 SDNode *UseNode, unsigned UseIdx) const {
519 if (!ItinData || ItinData->isEmpty())
520 return -1;
521
522 if (!DefNode->isMachineOpcode())
523 return -1;
524
525 unsigned DefClass = get(DefNode->getMachineOpcode()).getSchedClass();
526 if (!UseNode->isMachineOpcode())
527 return ItinData->getOperandCycle(DefClass, DefIdx);
528 unsigned UseClass = get(UseNode->getMachineOpcode()).getSchedClass();
529 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
530 }
531
532 int TargetInstrInfoImpl::getInstrLatency(const InstrItineraryData *ItinData,
533 SDNode *N) const {
534 if (!ItinData || ItinData->isEmpty())
535 return 1;
536
537 if (!N->isMachineOpcode())
538 return 1;
539
540 return ItinData->getStageLatency(get(N->getMachineOpcode()).getSchedClass());
541 }
542
543 //===----------------------------------------------------------------------===//
544 // MachineInstr latency interface.
545 //===----------------------------------------------------------------------===//
546
547 unsigned
548 TargetInstrInfoImpl::getNumMicroOps(const InstrItineraryData *ItinData,
549 const MachineInstr *MI) const {
550 if (!ItinData || ItinData->isEmpty())
551 return 1;
552
553 unsigned Class = MI->getDesc().getSchedClass();
554 int UOps = ItinData->Itineraries[Class].NumMicroOps;
555 if (UOps >= 0)
556 return UOps;
557
558 // The # of u-ops is dynamically determined. The specific target should
559 // override this function to return the right number.
560 return 1;
561 }
562
563 /// Return the default expected latency for a def based on it's opcode.
564 unsigned TargetInstrInfo::defaultDefLatency(const MCSchedModel *SchedModel,
565 const MachineInstr *DefMI) const {
566 if (DefMI->isTransient())
567 return 0;
568 if (DefMI->mayLoad())
569 return SchedModel->LoadLatency;
570 if (isHighLatencyDef(DefMI->getOpcode()))
571 return SchedModel->HighLatency;
572 return 1;
573 }
574
575 unsigned TargetInstrInfoImpl::
576 getInstrLatency(const InstrItineraryData *ItinData,
577 const MachineInstr *MI,
578 unsigned *PredCost) const {
579 // Default to one cycle for no itinerary. However, an "empty" itinerary may
580 // still have a MinLatency property, which getStageLatency checks.
581 if (!ItinData)
582 return MI->mayLoad() ? 2 : 1;
583
584 return ItinData->getStageLatency(MI->getDesc().getSchedClass());
585 }
586
587 bool TargetInstrInfoImpl::hasLowDefLatency(const InstrItineraryData *ItinData,
588 const MachineInstr *DefMI,
589 unsigned DefIdx) const {
590 if (!ItinData || ItinData->isEmpty())
591 return false;
592
593 unsigned DefClass = DefMI->getDesc().getSchedClass();
594 int DefCycle = ItinData->getOperandCycle(DefClass, DefIdx);
595 return (DefCycle != -1 && DefCycle <= 1);
596 }
597
598 /// Both DefMI and UseMI must be valid. By default, call directly to the
599 /// itinerary. This may be overriden by the target.
600 int TargetInstrInfoImpl::
601 getOperandLatency(const InstrItineraryData *ItinData,
602 const MachineInstr *DefMI, unsigned DefIdx,
603 const MachineInstr *UseMI, unsigned UseIdx) const {
604 unsigned DefClass = DefMI->getDesc().getSchedClass();
605 unsigned UseClass = UseMI->getDesc().getSchedClass();
606 return ItinData->getOperandLatency(DefClass, DefIdx, UseClass, UseIdx);
607 }
608
609 /// If we can determine the operand latency from the def only, without itinerary
610 /// lookup, do so. Otherwise return -1.
611 int TargetInstrInfo::computeDefOperandLatency(
612 const InstrItineraryData *ItinData,
613 const MachineInstr *DefMI, bool FindMin) const {
614
615 // Let the target hook getInstrLatency handle missing itineraries.
616 if (!ItinData)
617 return getInstrLatency(ItinData, DefMI);
618
619 // Return a latency based on the itinerary properties and defining instruction
620 // if possible. Some common subtargets don't require per-operand latency,
621 // especially for minimum latencies.
622 if (FindMin) {
623 // If MinLatency is valid, call getInstrLatency. This uses Stage latency if
624 // it exists before defaulting to MinLatency.
625 if (ItinData->SchedModel->MinLatency >= 0)
626 return getInstrLatency(ItinData, DefMI);
627
628 // If MinLatency is invalid, OperandLatency is interpreted as MinLatency.
629 // For empty itineraries, short-cirtuit the check and default to one cycle.
630 if (ItinData->isEmpty())
631 return 1;
632 }
633 else if(ItinData->isEmpty())
634 return defaultDefLatency(ItinData->SchedModel, DefMI);
635
636 // ...operand lookup required
637 return -1;
638 }
639
640 /// computeOperandLatency - Compute and return the latency of the given data
641 /// dependent def and use when the operand indices are already known. UseMI may
642 /// be NULL for an unknown use.
643 ///
644 /// FindMin may be set to get the minimum vs. expected latency. Minimum
645 /// latency is used for scheduling groups, while expected latency is for
646 /// instruction cost and critical path.
647 ///
648 /// Depending on the subtarget's itinerary properties, this may or may not need
649 /// to call getOperandLatency(). For most subtargets, we don't need DefIdx or
650 /// UseIdx to compute min latency.
651 unsigned TargetInstrInfo::
652 computeOperandLatency(const InstrItineraryData *ItinData,
653 const MachineInstr *DefMI, unsigned DefIdx,
654 const MachineInstr *UseMI, unsigned UseIdx,
655 bool FindMin) const {
656
657 int DefLatency = computeDefOperandLatency(ItinData, DefMI, FindMin);
658 if (DefLatency >= 0)
659 return DefLatency;
660
661 assert(ItinData && !ItinData->isEmpty() && "computeDefOperandLatency fail");
662
663 int OperLatency = 0;
664 if (UseMI)
665 OperLatency = getOperandLatency(ItinData, DefMI, DefIdx, UseMI, UseIdx);
666 else {
667 unsigned DefClass = DefMI->getDesc().getSchedClass();
668 OperLatency = ItinData->getOperandCycle(DefClass, DefIdx);
669 }
670 if (OperLatency >= 0)
671 return OperLatency;
672
673 // No operand latency was found.
674 unsigned InstrLatency = getInstrLatency(ItinData, DefMI);
675
676 // Expected latency is the max of the stage latency and itinerary props.
677 if (!FindMin)
678 InstrLatency = std::max(InstrLatency,
679 defaultDefLatency(ItinData->SchedModel, DefMI));
680 return InstrLatency;
681 }