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Added support for unpredictable mcrr/mcrr2/mrrc/mrrc2 ARM instruction in the disassembler. Since the upredicability conditions are complex, C++ code was added to handle them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@155001 91177308-0d34-0410-b5e6-96231b3b80d8 Silviu Baranga 7 years ago
4 changed file(s) with 53 addition(s) and 4 deletion(s). Raw diff Collapse all Expand all
45894589
45904590 class MovRRCopro pattern = []>
45914591 : ABI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4592 GPR:$Rt, GPR:$Rt2, c_imm:$CRm),
4592 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm),
45934593 NoItinerary, opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm", pattern> {
45944594 let Inst{23-21} = 0b010;
45954595 let Inst{20} = direction;
46084608 }
46094609
46104610 def MCRR : MovRRCopro<"mcrr", 0 /* from ARM core register to coprocessor */,
4611 [(int_arm_mcrr imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4611 [(int_arm_mcrr imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2,
46124612 imm:$CRm)]>;
46134613 def MRRC : MovRRCopro<"mrrc", 1 /* from coprocessor to ARM core register */>;
46144614
46154615 class MovRRCopro2 pattern = []>
46164616 : ABXI<0b1100, (outs), (ins p_imm:$cop, imm0_15:$opc1,
4617 GPR:$Rt, GPR:$Rt2, c_imm:$CRm), NoItinerary,
4617 GPRnopc:$Rt, GPRnopc:$Rt2, c_imm:$CRm), NoItinerary,
46184618 !strconcat(opc, "\t$cop, $opc1, $Rt, $Rt2, $CRm"), pattern> {
46194619 let Inst{31-28} = 0b1111;
46204620 let Inst{23-21} = 0b010;
46314631 let Inst{11-8} = cop;
46324632 let Inst{7-4} = opc1;
46334633 let Inst{3-0} = CRm;
4634
4635 let DecoderMethod = "DecodeMRRC2";
46344636 }
46354637
46364638 def MCRR2 : MovRRCopro2<"mcrr2", 0 /* from ARM core register to coprocessor */,
4637 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPR:$Rt, GPR:$Rt2,
4639 [(int_arm_mcrr2 imm:$cop, imm:$opc1, GPRnopc:$Rt, GPRnopc:$Rt2,
46384640 imm:$CRm)]>;
46394641 def MRRC2 : MovRRCopro2<"mrrc2", 1 /* from coprocessor to ARM core register */>;
46404642
324324 uint64_t Address, const void *Decoder);
325325
326326 static DecodeStatus DecodeLDR(MCInst &Inst, unsigned Val,
327 uint64_t Address, const void *Decoder);
328 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
327329 uint64_t Address, const void *Decoder);
328330 #include "ARMGenDisassemblerTables.inc"
329331 #include "ARMGenInstrInfo.inc"
44024404 return S;
44034405 }
44044406
4407 static DecodeStatus DecodeMRRC2(llvm::MCInst &Inst, unsigned Val,
4408 uint64_t Address, const void *Decoder) {
4409
4410 DecodeStatus S = MCDisassembler::Success;
4411
4412 unsigned CRm = fieldFromInstruction32(Val, 0, 4);
4413 unsigned opc1 = fieldFromInstruction32(Val, 4, 4);
4414 unsigned cop = fieldFromInstruction32(Val, 8, 4);
4415 unsigned Rt = fieldFromInstruction32(Val, 12, 4);
4416 unsigned Rt2 = fieldFromInstruction32(Val, 16, 4);
4417
4418 if ((cop & ~0x1) == 0xa)
4419 return MCDisassembler::Fail;
4420
4421 if (Rt == Rt2)
4422 S = MCDisassembler::SoftFail;
4423
4424 Inst.addOperand(MCOperand::CreateImm(cop));
4425 Inst.addOperand(MCOperand::CreateImm(opc1));
4426 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt, Address, Decoder)))
4427 return MCDisassembler::Fail;
4428 if (!Check(S, DecodeGPRnopcRegisterClass(Inst, Rt2, Address, Decoder)))
4429 return MCDisassembler::Fail;
4430 Inst.addOperand(MCOperand::CreateImm(CRm));
4431
4432 return S;
4433 }
4434
0 # RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
1
2 # CHECK: invalid instruction encoding
3 0x00 0x1a 0x50 0xfc
0 # RUN: llvm-mc --disassemble %s -triple=armv7-linux-gnueabi |& FileCheck %s
1
2 # CHECK: potentially undefined
3 # CHECK: 0x00 0x10 0x51 0xfc
4 0x00 0x10 0x51 0xfc
5
6 # CHECK: potentially undefined
7 # CHECK: 0x00 0xf0 0x41 0x0c
8 0x00 0xf0 0x41 0x0c
9
10 # CHECK: potentially undefined
11 # CHECK: 0x00 0x00 0x4f 0x0c
12 0x00 0x00 0x4f 0x0c