llvm.org GIT mirror llvm / fa16354
Change createPostRAScheduler so it can be turned off at llc -O1. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@84273 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
6 changed file(s) with 32 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
1414 #ifndef LLVM_CODEGEN_PASSES_H
1515 #define LLVM_CODEGEN_PASSES_H
1616
17 #include "llvm/Target/TargetMachine.h"
1718 #include
1819
1920 namespace llvm {
2021
2122 class FunctionPass;
2223 class PassInfo;
23 class TargetMachine;
2424 class TargetLowering;
2525 class RegisterCoalescer;
2626 class raw_ostream;
118118 ///
119119 FunctionPass *createLowerSubregsPass();
120120
121 /// createPostRAScheduler - under development.
122 FunctionPass *createPostRAScheduler();
121 /// createPostRAScheduler - This pass performs post register allocation
122 /// scheduling.
123 FunctionPass *createPostRAScheduler(CodeGenOpt::Level OptLevel);
123124
124125 /// BranchFolding Pass - This pass performs machine code CFG based
125126 /// optimizations to delete branches to branches, eliminate branches to
1212
1313 #ifndef LLVM_TARGET_TARGETSUBTARGET_H
1414 #define LLVM_TARGET_TARGETSUBTARGET_H
15
16 #include "llvm/Target/TargetMachine.h"
1517
1618 namespace llvm {
1719
3840 /// should be attempted.
3941 virtual unsigned getSpecialAddressLatency() const { return 0; }
4042
41 // enablePostRAScheduler - Return true to enable
42 // post-register-allocation scheduling.
43 virtual bool enablePostRAScheduler() const { return false; }
43 // enablePostRAScheduler - If the target can benefit from post-regalloc
44 // scheduling and the specified optimization level meets the requirement
45 // return true to enable post-register-allocation scheduling.
46 virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
47 return false;
48 }
4449
4550 // adjustSchedDependency - Perform target specific adjustments to
4651 // the latency of a schedule dependency.
322322
323323 // Second pass scheduler.
324324 if (OptLevel != CodeGenOpt::None) {
325 PM.add(createPostRAScheduler());
325 PM.add(createPostRAScheduler(OptLevel));
326326 printAndVerify(PM);
327327 }
328328
7777 namespace {
7878 class VISIBILITY_HIDDEN PostRAScheduler : public MachineFunctionPass {
7979 AliasAnalysis *AA;
80 CodeGenOpt::Level OptLevel;
8081
8182 public:
8283 static char ID;
83 PostRAScheduler() : MachineFunctionPass(&ID) {}
84 PostRAScheduler(CodeGenOpt::Level ol) :
85 MachineFunctionPass(&ID), OptLevel(ol) {}
8486
8587 void getAnalysisUsage(AnalysisUsage &AU) const {
8688 AU.setPreservesCFG();
237239 } else {
238240 // Check that post-RA scheduling is enabled for this target.
239241 const TargetSubtarget &ST = Fn.getTarget().getSubtarget();
240 if (!ST.enablePostRAScheduler())
242 if (!ST.enablePostRAScheduler(OptLevel))
241243 return false;
242244 }
243245
11941196 // Public Constructor Functions
11951197 //===----------------------------------------------------------------------===//
11961198
1197 FunctionPass *llvm::createPostRAScheduler() {
1198 return new PostRAScheduler();
1199 }
1199 FunctionPass *llvm::createPostRAScheduler(CodeGenOpt::Level OptLevel) {
1200 return new PostRAScheduler(OptLevel);
1201 }
125125
126126 const std::string & getCPUString() const { return CPUString; }
127127
128 /// enablePostRAScheduler - From TargetSubtarget, return true to
129 /// enable post-RA scheduler.
130 bool enablePostRAScheduler() const { return PostRAScheduler; }
128 /// enablePostRAScheduler - True at 'More' optimization except
129 /// for Thumb1.
130 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
131 return PostRAScheduler && OptLevel >= CodeGenOpt::Default;
132 }
131133
132134 /// getInstrItins - Return the instruction itineraies based on subtarget
133135 /// selection.
214214 /// indicating the number of scheduling cycles of backscheduling that
215215 /// should be attempted.
216216 unsigned getSpecialAddressLatency() const;
217
218 /// enablePostRAScheduler - X86 target is enabling post-alloc scheduling
219 /// at 'More' optimization level.
220 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel) const {
221 // FIXME: This causes llvm to miscompile itself on i386. :-(
222 return false/*OptLevel >= CodeGenOpt::Default*/;
223 }
217224 };
218225
219226 } // End llvm namespace