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Merging r295990: ------------------------------------------------------------------------ r295990 | jvesely | 2017-02-23 08:12:21 -0800 (Thu, 23 Feb 2017) | 5 lines AMDGPU/SI: Fix trunc i16 pattern Hit on ASICs that support 16bit instructions. Differential Revision: https://reviews.llvm.org/D30281 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_40@296158 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 2 years ago
3 changed file(s) with 65 addition(s) and 37 deletion(s). Raw diff Collapse all Expand all
996996 >;
997997
998998 def : Pat <
999 (i1 (trunc i16:$a)),
1000 (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1), $a), (i32 1))
1001 >;
1002
1003 def : Pat <
9991004 (i1 (trunc i64:$a)),
10001005 (V_CMP_EQ_U32_e64 (S_AND_B32 (i32 1),
10011006 (i32 (EXTRACT_SUBREG $a, sub0))), (i32 1))
606606 (COPY $src)
607607 >;
608608
609 def : Pat<
610 (i1 (trunc i16:$src)),
611 (COPY $src)
612 >;
613
614
615609 def : Pat <
616610 (i16 (trunc i64:$src)),
617611 (EXTRACT_SUBREG $src, sub0)
None ; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=SI %s
0 ; RUN: llc -march=amdgcn -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
1 ; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs< %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
12 ; RUN: llc -march=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG %s
23
34 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
45
56 define void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, i64 %in) {
6 ; SI-LABEL: {{^}}trunc_i64_to_i32_store:
7 ; SI: s_load_dword [[SLOAD:s[0-9]+]], s[0:1], 0xb
8 ; SI: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
7 ; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
8 ; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
9 ; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
910 ; SI: buffer_store_dword [[VLOAD]]
11 ; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]
1012
1113 ; EG-LABEL: {{^}}trunc_i64_to_i32_store:
1214 ; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
1719 ret void
1820 }
1921
20 ; SI-LABEL: {{^}}trunc_load_shl_i64:
21 ; SI-DAG: s_load_dwordx2
22 ; SI-DAG: s_load_dword [[SREG:s[0-9]+]],
23 ; SI: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
24 ; SI: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
25 ; SI: buffer_store_dword [[VSHL]],
22 ; GCN-LABEL: {{^}}trunc_load_shl_i64:
23 ; GCN-DAG: s_load_dwordx2
24 ; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],
25 ; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
26 ; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
27 ; SI: buffer_store_dword [[VSHL]]
28 ; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]
29
2630 define void @trunc_load_shl_i64(i32 addrspace(1)* %out, i64 %a) {
2731 %b = shl i64 %a, 2
2832 %result = trunc i64 %b to i32
3034 ret void
3135 }
3236
33 ; SI-LABEL: {{^}}trunc_shl_i64:
37 ; GCN-LABEL: {{^}}trunc_shl_i64:
3438 ; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
35 ; SI: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
36 ; SI: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
37 ; SI: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
38 ; SI: s_addc_u32
39 ; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
40 ; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
41 ; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
42 ; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
43 ; GCN: s_addc_u32
3944 ; SI: buffer_store_dword v[[LO_VREG]],
40 ; SI: v_mov_b32_e32
41 ; SI: v_mov_b32_e32
45 ; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
46 ; GCN: v_mov_b32_e32
47 ; GCN: v_mov_b32_e32
4248 define void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
4349 %aa = add i64 %a, 234 ; Prevent shrinking store.
4450 %b = shl i64 %aa, 2
4854 ret void
4955 }
5056
51 ; SI-LABEL: {{^}}trunc_i32_to_i1:
52 ; SI: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
53 ; SI: v_cmp_eq_u32
57 ; GCN-LABEL: {{^}}trunc_i32_to_i1:
58 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
59 ; GCN: v_cmp_eq_u32
5460 define void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
5561 %a = load i32, i32 addrspace(1)* %ptr, align 4
5662 %trunc = trunc i32 %a to i1
5965 ret void
6066 }
6167
62 ; SI-LABEL: {{^}}sgpr_trunc_i32_to_i1:
63 ; SI: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
64 ; SI: v_cmp_eq_u32
68 ; GCN-LABEL: {{^}}trunc_i8_to_i1:
69 ; GCN: v_and_b32_e32 v{{[0-9]+}}, 1, v{{[0-9]+}}
70 ; GCN: v_cmp_eq_u32
71 define void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
72 %a = load i8, i8 addrspace(1)* %ptr, align 4
73 %trunc = trunc i8 %a to i1
74 %result = select i1 %trunc, i8 1, i8 0
75 store i8 %result, i8 addrspace(1)* %out, align 4
76 ret void
77 }
78
79 ; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
80 ; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
81 ; GCN: v_cmp_eq_u32
82 define void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
83 %trunc = trunc i16 %a to i1
84 %result = select i1 %trunc, i16 1, i16 0
85 store i16 %result, i16 addrspace(1)* %out, align 4
86 ret void
87 }
88
89 ; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
90 ; GCN: s_and_b32 s{{[0-9]+}}, 1, s{{[0-9]+}}
91 ; GCN: v_cmp_eq_u32
6592 define void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
6693 %trunc = trunc i32 %a to i1
6794 %result = select i1 %trunc, i32 1, i32 0
6996 ret void
7097 }
7198
72 ; SI-LABEL: {{^}}s_trunc_i64_to_i1:
99 ; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
73100 ; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0xb
74 ; SI: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
75 ; SI: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
76 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
101 ; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x2c
102 ; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
103 ; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
104 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
77105 define void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 %x) {
78106 %trunc = trunc i64 %x to i1
79107 %sel = select i1 %trunc, i32 63, i32 -12
81109 ret void
82110 }
83111
84 ; SI-LABEL: {{^}}v_trunc_i64_to_i1:
112 ; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
85113 ; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
86 ; SI: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
87 ; SI: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
88 ; SI: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
114 ; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
115 ; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
116 ; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
117 ; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
89118 define void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
90119 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
91120 %gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid