llvm.org GIT mirror llvm / fa0cf99
Remove special FP opcode maps and instead add enough MRM_XX formats to handle all the FP operations. This increases format by 1 bit, but decreases opcode map by 1 bit so the TSFlags size doesn't change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@201649 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 5 years ago
7 changed file(s) with 208 addition(s) and 226 deletion(s). Raw diff Collapse all Expand all
305305 MRM_CB = 40, MRM_D0 = 41, MRM_D1 = 42, MRM_D4 = 43,
306306 MRM_D5 = 44, MRM_D6 = 45, MRM_D8 = 46, MRM_D9 = 47,
307307 MRM_DA = 48, MRM_DB = 49, MRM_DC = 50, MRM_DD = 51,
308 MRM_DE = 52, MRM_DF = 53, MRM_E0 = 54, MRM_E8 = 55,
309 MRM_F0 = 56, MRM_F8 = 57, MRM_F9 = 58,
310
311 FormMask = 63,
308 MRM_DE = 52, MRM_DF = 53, MRM_E0 = 54, MRM_E1 = 55,
309 MRM_E2 = 56, MRM_E3 = 57, MRM_E4 = 58, MRM_E5 = 59,
310 MRM_E8 = 60, MRM_E9 = 61, MRM_EA = 62, MRM_EB = 63,
311 MRM_EC = 64, MRM_ED = 65, MRM_EE = 66, MRM_F0 = 67,
312 MRM_F1 = 68, MRM_F2 = 69, MRM_F3 = 70, MRM_F4 = 71,
313 MRM_F5 = 72, MRM_F6 = 73, MRM_F7 = 74, MRM_F8 = 75,
314 MRM_F9 = 76, MRM_FA = 77, MRM_FB = 78, MRM_FC = 79,
315 MRM_FD = 80, MRM_FE = 81, MRM_FF = 82,
316
317 FormMask = 127,
312318
313319 //===------------------------------------------------------------------===//
314320 // Actual flags...
317323 // OpSize16 means this is a 16-bit instruction and needs 0x66 prefix in
318324 // 32-bit mode. OpSize32 means this is a 32-bit instruction needs a 0x66
319325 // prefix in 16-bit mode.
320 OpSizeShift = 6,
326 OpSizeShift = 7,
321327 OpSizeMask = 0x3 << OpSizeShift,
322328
323329 OpSize16 = 1,
326332 // AsSize - Set if this instruction requires an operand size prefix (0x67),
327333 // which most often indicates that the instruction address 16 bit address
328334 // instead of 32 bit address (or 32 bit address in 64 bit mode).
329 AdSize = 1 << 8,
335 AdSizeShift = OpSizeShift + 2,
336 AdSize = 1 << AdSizeShift,
330337
331338 //===------------------------------------------------------------------===//
332339 // OpPrefix - There are several prefix bytes that are used as opcode
333340 // extensions. These are 0x66, 0xF3, and 0xF2. If this field is 0 there is
334341 // no prefix.
335342 //
336 OpPrefixShift = 9,
343 OpPrefixShift = AdSizeShift + 1,
337344 OpPrefixMask = 0x7 << OpPrefixShift,
338345
339346 // PS, PD - Prefix code for packed single and double precision vector
349356 // belongs to. i.e. one-byte, two-byte, 0x0f 0x38, 0x0f 0x3a, etc.
350357 //
351358 OpMapShift = OpPrefixShift + 3,
352 OpMapMask = 0xf << OpMapShift,
359 OpMapMask = 0x7 << OpMapShift,
353360
354361 // OB - OneByte - Set if this instruction has a one byte opcode.
355362 OB = 0 << OpMapShift,
369376
370377 // XOPA - Prefix to encode 0xA in VEX.MMMM of XOP instructions.
371378 XOPA = 6 << OpMapShift,
372
373 // D8-DF - These escape opcodes are used by the floating point unit. These
374 // values must remain sequential.
375 D8 = 7 << OpMapShift, D9 = 8 << OpMapShift,
376 DA = 9 << OpMapShift, DB = 10 << OpMapShift,
377 DC = 11 << OpMapShift, DD = 12 << OpMapShift,
378 DE = 13 << OpMapShift, DF = 14 << OpMapShift,
379379
380380 //===------------------------------------------------------------------===//
381381 // REX_W - REX prefixes are instruction prefixes used in 64-bit mode.
383383 // etc. We only cares about REX.W and REX.R bits and only the former is
384384 // statically determined.
385385 //
386 REXShift = OpMapShift + 4,
386 REXShift = OpMapShift + 3,
387387 REX_W = 1 << REXShift,
388388
389389 //===------------------------------------------------------------------===//
694694 case X86II::MRM_C0: case X86II::MRM_C1: case X86II::MRM_C2:
695695 case X86II::MRM_C3: case X86II::MRM_C4: case X86II::MRM_C8:
696696 case X86II::MRM_C9: case X86II::MRM_CA: case X86II::MRM_CB:
697 case X86II::MRM_E8: case X86II::MRM_F0: case X86II::MRM_F8:
698 case X86II::MRM_F9: case X86II::MRM_D0: case X86II::MRM_D1:
699 case X86II::MRM_D4: case X86II::MRM_D5: case X86II::MRM_D6:
700 case X86II::MRM_D8: case X86II::MRM_D9: case X86II::MRM_DA:
701 case X86II::MRM_DB: case X86II::MRM_DC: case X86II::MRM_DD:
702 case X86II::MRM_DE: case X86II::MRM_DF: case X86II::MRM_E0:
697 case X86II::MRM_D0: case X86II::MRM_D1: case X86II::MRM_D4:
698 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
699 case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
700 case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
701 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
702 case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
703 case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
704 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
705 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
706 case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
707 case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
708 case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
709 case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
710 case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
703711 return -1;
704712 }
705713 }
11511151 case X86II::TA: // 0F 3A
11521152 EmitByte(0x0F, CurByte, OS);
11531153 break;
1154 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
1155 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
1156 EmitByte(0xD8+(((TSFlags & X86II::OpMapMask) - X86II::D8) >>
1157 X86II::OpMapShift), CurByte, OS);
1158 break;
11591154 }
11601155
11611156 switch (TSFlags & X86II::OpMapMask) {
14541449 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
14551450 case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
14561451 case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
1457 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E8:
1458 case X86II::MRM_F0: case X86II::MRM_F8: case X86II::MRM_F9:
1452 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
1453 case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
1454 case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
1455 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1456 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
1457 case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
1458 case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
1459 case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
1460 case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
1461 case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
14591462 EmitByte(BaseOpcode, CurByte, OS);
14601463
14611464 unsigned char MRM;
14841487 case X86II::MRM_DE: MRM = 0xDE; break;
14851488 case X86II::MRM_DF: MRM = 0xDF; break;
14861489 case X86II::MRM_E0: MRM = 0xE0; break;
1490 case X86II::MRM_E1: MRM = 0xE1; break;
1491 case X86II::MRM_E2: MRM = 0xE2; break;
1492 case X86II::MRM_E3: MRM = 0xE3; break;
1493 case X86II::MRM_E4: MRM = 0xE4; break;
1494 case X86II::MRM_E5: MRM = 0xE5; break;
14871495 case X86II::MRM_E8: MRM = 0xE8; break;
1496 case X86II::MRM_E9: MRM = 0xE9; break;
1497 case X86II::MRM_EA: MRM = 0xEA; break;
1498 case X86II::MRM_EB: MRM = 0xEB; break;
1499 case X86II::MRM_EC: MRM = 0xEC; break;
1500 case X86II::MRM_ED: MRM = 0xED; break;
1501 case X86II::MRM_EE: MRM = 0xEE; break;
14881502 case X86II::MRM_F0: MRM = 0xF0; break;
1503 case X86II::MRM_F1: MRM = 0xF1; break;
1504 case X86II::MRM_F2: MRM = 0xF2; break;
1505 case X86II::MRM_F3: MRM = 0xF3; break;
1506 case X86II::MRM_F4: MRM = 0xF4; break;
1507 case X86II::MRM_F5: MRM = 0xF5; break;
1508 case X86II::MRM_F6: MRM = 0xF6; break;
1509 case X86II::MRM_F7: MRM = 0xF7; break;
14891510 case X86II::MRM_F8: MRM = 0xF8; break;
14901511 case X86II::MRM_F9: MRM = 0xF9; break;
1512 case X86II::MRM_FA: MRM = 0xFA; break;
1513 case X86II::MRM_FB: MRM = 0xFB; break;
1514 case X86II::MRM_FC: MRM = 0xFC; break;
1515 case X86II::MRM_FD: MRM = 0xFD; break;
1516 case X86II::MRM_FE: MRM = 0xFE; break;
1517 case X86II::MRM_FF: MRM = 0xFF; break;
14911518 }
14921519 EmitByte(MRM, CurByte, OS);
14931520 break;
683683 case X86II::TA: // 0F 3A
684684 MCE.emitByte(0x0F);
685685 break;
686 case X86II::D8: case X86II::D9: case X86II::DA: case X86II::DB:
687 case X86II::DC: case X86II::DD: case X86II::DE: case X86II::DF:
688 MCE.emitByte(0xD8+
689 (((Desc->TSFlags & X86II::OpMapMask)-X86II::D8)
690 >> X86II::OpMapShift));
691 break;
692686 }
693687
694688 switch (Desc->TSFlags & X86II::OpMapMask) {
13771371 case X86II::MRM_D5: case X86II::MRM_D6: case X86II::MRM_D8:
13781372 case X86II::MRM_D9: case X86II::MRM_DA: case X86II::MRM_DB:
13791373 case X86II::MRM_DC: case X86II::MRM_DD: case X86II::MRM_DE:
1380 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E8:
1381 case X86II::MRM_F0: case X86II::MRM_F8:
1374 case X86II::MRM_DF: case X86II::MRM_E0: case X86II::MRM_E1:
1375 case X86II::MRM_E2: case X86II::MRM_E3: case X86II::MRM_E4:
1376 case X86II::MRM_E5: case X86II::MRM_E8: case X86II::MRM_E9:
1377 case X86II::MRM_EA: case X86II::MRM_EB: case X86II::MRM_EC:
1378 case X86II::MRM_ED: case X86II::MRM_EE: case X86II::MRM_F0:
1379 case X86II::MRM_F1: case X86II::MRM_F2: case X86II::MRM_F3:
1380 case X86II::MRM_F4: case X86II::MRM_F5: case X86II::MRM_F6:
1381 case X86II::MRM_F7: case X86II::MRM_F8: case X86II::MRM_F9:
1382 case X86II::MRM_FA: case X86II::MRM_FB: case X86II::MRM_FC:
1383 case X86II::MRM_FD: case X86II::MRM_FE: case X86II::MRM_FF:
13821384 MCE.emitByte(BaseOpcode);
13831385
13841386 unsigned char MRM;
14071409 case X86II::MRM_DE: MRM = 0xDE; break;
14081410 case X86II::MRM_DF: MRM = 0xDF; break;
14091411 case X86II::MRM_E0: MRM = 0xE0; break;
1412 case X86II::MRM_E1: MRM = 0xE1; break;
1413 case X86II::MRM_E2: MRM = 0xE2; break;
1414 case X86II::MRM_E3: MRM = 0xE3; break;
1415 case X86II::MRM_E4: MRM = 0xE4; break;
1416 case X86II::MRM_E5: MRM = 0xE5; break;
14101417 case X86II::MRM_E8: MRM = 0xE8; break;
1418 case X86II::MRM_E9: MRM = 0xE9; break;
1419 case X86II::MRM_EA: MRM = 0xEA; break;
1420 case X86II::MRM_EB: MRM = 0xEB; break;
1421 case X86II::MRM_EC: MRM = 0xEC; break;
1422 case X86II::MRM_ED: MRM = 0xED; break;
1423 case X86II::MRM_EE: MRM = 0xEE; break;
14111424 case X86II::MRM_F0: MRM = 0xF0; break;
1425 case X86II::MRM_F1: MRM = 0xF1; break;
1426 case X86II::MRM_F2: MRM = 0xF2; break;
1427 case X86II::MRM_F3: MRM = 0xF3; break;
1428 case X86II::MRM_F4: MRM = 0xF4; break;
1429 case X86II::MRM_F5: MRM = 0xF5; break;
1430 case X86II::MRM_F6: MRM = 0xF6; break;
1431 case X86II::MRM_F7: MRM = 0xF7; break;
14121432 case X86II::MRM_F8: MRM = 0xF8; break;
14131433 case X86II::MRM_F9: MRM = 0xF9; break;
1434 case X86II::MRM_FA: MRM = 0xFA; break;
1435 case X86II::MRM_FB: MRM = 0xFB; break;
1436 case X86II::MRM_FC: MRM = 0xFC; break;
1437 case X86II::MRM_FD: MRM = 0xFD; break;
1438 case X86II::MRM_FE: MRM = 0xFE; break;
1439 case X86II::MRM_FF: MRM = 0xFF; break;
14141440 }
14151441 MCE.emitByte(MRM);
14161442 break;
250250 def COMP_FST0r : FPST0rInst ;
251251
252252 // Unary operations.
253 multiclass FPUnarybits<8> opcode, string asmstring> {
253 multiclass FPUnaryFormat fp, string asmstring> {
254254 def _Fp32 : FpIf32<(outs RFP32:$dst), (ins RFP32:$src), OneArgFPRW,
255255 [(set RFP32:$dst, (OpNode RFP32:$src))]>;
256256 def _Fp64 : FpIf64<(outs RFP64:$dst), (ins RFP64:$src), OneArgFPRW,
257257 [(set RFP64:$dst, (OpNode RFP64:$src))]>;
258258 def _Fp80 : FpI_<(outs RFP80:$dst), (ins RFP80:$src), OneArgFPRW,
259259 [(set RFP80:$dst, (OpNode RFP80:$src))]>;
260 def _F : FPI<opcode, RawFrm, (outs), (ins), asmstring>, D9;
260 def _F : FPI<0xD9, fp, (outs), (ins), asmstring>;
261261 }
262262
263263 let Defs = [FPSW] in {
264 defm CHS : FPUnary;
265 defm ABS : FPUnary;
266 defm SQRT: FPUnary;
267 defm SIN : FPUnary;
268 defm COS : FPUnarys">;
264 defm CHS : FPUnarys">;
265 defm ABS : FPUnary;
266 defm SQRT: FPUnary;
267 defm SIN : FPUnary;
268 defm COS : FPUnary;
269269
270270 let neverHasSideEffects = 1 in {
271271 def TST_Fp32 : FpIf32<(outs), (ins RFP32:$src), OneArgFP, []>;
272272 def TST_Fp64 : FpIf64<(outs), (ins RFP64:$src), OneArgFP, []>;
273273 def TST_Fp80 : FpI_<(outs), (ins RFP80:$src), OneArgFP, []>;
274274 }
275 def TST_F : FPI<0xE4, RawFrm, (outs), (ins), "ftst">, D9;
275 def TST_F : FPI<0xD9, MRM_E4, (outs), (ins), "ftst">;
276276 } // Defs = [FPSW]
277277
278278 // Versions of FP instructions that take a single memory operand. Added for the
514514 }
515515
516516 let SchedRW = [WriteZero] in {
517 def LD_F0 : FPI<0xEE, RawFrm, (outs), (ins), "fldz", IIC_FLDZ>, D9;
518 def LD_F1 : FPI<0xE8, RawFrm, (outs), (ins), "fld1", IIC_FIST>, D9;
517 def LD_F0 : FPI<0xD9, MRM_EE, (outs), (ins), "fldz", IIC_FLDZ>;
518 def LD_F1 : FPI<0xD9, MRM_E8, (outs), (ins), "fld1", IIC_FIST>;
519519 }
520520
521521 // Floating point compares.
545545 (outs), (ins RST:$reg), "fucom\t$reg", IIC_FUCOM>;
546546 def UCOM_FPr : FPI<0xDD, MRM5r, // FPSW = cmp ST(0) with ST(i), pop
547547 (outs), (ins RST:$reg), "fucomp\t$reg", IIC_FUCOM>;
548 def UCOM_FPPr : FPI<0xE9, RawFrm, // cmp ST(0) with ST(1), pop, pop
549 (outs), (ins), "fucompp", IIC_FUCOM>, DA;
548 def UCOM_FPPr : FPI<0xDA, MRM_E9, // cmp ST(0) with ST(1), pop, pop
549 (outs), (ins), "fucompp", IIC_FUCOM>;
550550 }
551551
552552 let Defs = [EFLAGS, FPSW], Uses = [ST0] in {
567567 // Floating point flag ops.
568568 let SchedRW = [WriteALU] in {
569569 let Defs = [AX], Uses = [FPSW] in
570 def FNSTSW16r : I<0xE0, RawFrm, // AX = fp flags
570 def FNSTSW16r : I<0xDF, MRM_E0, // AX = fp flags
571571 (outs), (ins), "fnstsw\t{%ax|ax}",
572 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>, DF;
572 [(set AX, (X86fp_stsw FPSW))], IIC_FNSTSW>;
573573
574574 def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world
575575 (outs), (ins i16mem:$dst), "fnstcw\t$dst",
583583 // FPU control instructions
584584 let SchedRW = [WriteMicrocoded] in {
585585 let Defs = [FPSW] in
586 def FNINIT : I<0xE3, RawFrm, (outs), (ins), "fninit", [], IIC_FNINIT>, DB;
586 def FNINIT : I<0xDB, MRM_E3, (outs), (ins), "fninit", [], IIC_FNINIT>;
587587 def FFREE : FPI<0xDD, MRM0r, (outs), (ins RST:$reg),
588588 "ffree\t$reg", IIC_FFREE>;
589589 // Clear exceptions
590590
591591 let Defs = [FPSW] in
592 def FNCLEX : I<0xE2, RawFrm, (outs), (ins), "fnclex", [], IIC_FNCLEX>, DB;
592 def FNCLEX : I<0xDB, MRM_E2, (outs), (ins), "fnclex", [], IIC_FNCLEX>;
593593 } // SchedRW
594594
595595 // Operandless floating-point instructions for the disassembler.
596596 let SchedRW = [WriteMicrocoded] in {
597597 def WAIT : I<0x9B, RawFrm, (outs), (ins), "wait", [], IIC_WAIT>;
598598
599 def FNOP : I<0xD0, RawFrm, (outs), (ins), "fnop", [], IIC_FNOP>, D9;
600 def FXAM : I<0xE5, RawFrm, (outs), (ins), "fxam", [], IIC_FXAM>, D9;
601 def FLDL2T : I<0xE9, RawFrm, (outs), (ins), "fldl2t", [], IIC_FLDL>, D9;
602 def FLDL2E : I<0xEA, RawFrm, (outs), (ins), "fldl2e", [], IIC_FLDL>, D9;
603 def FLDPI : I<0xEB, RawFrm, (outs), (ins), "fldpi", [], IIC_FLDL>, D9;
604 def FLDLG2 : I<0xEC, RawFrm, (outs), (ins), "fldlg2", [], IIC_FLDL>, D9;
605 def FLDLN2 : I<0xED, RawFrm, (outs), (ins), "fldln2", [], IIC_FLDL>, D9;
606 def F2XM1 : I<0xF0, RawFrm, (outs), (ins), "f2xm1", [], IIC_F2XM1>, D9;
607 def FYL2X : I<0xF1, RawFrm, (outs), (ins), "fyl2x", [], IIC_FYL2X>, D9;
608 def FPTAN : I<0xF2, RawFrm, (outs), (ins), "fptan", [], IIC_FPTAN>, D9;
609 def FPATAN : I<0xF3, RawFrm, (outs), (ins), "fpatan", [], IIC_FPATAN>, D9;
610 def FXTRACT : I<0xF4, RawFrm, (outs), (ins), "fxtract", [], IIC_FXTRACT>, D9;
611 def FPREM1 : I<0xF5, RawFrm, (outs), (ins), "fprem1", [], IIC_FPREM1>, D9;
612 def FDECSTP : I<0xF6, RawFrm, (outs), (ins), "fdecstp", [], IIC_FPSTP>, D9;
613 def FINCSTP : I<0xF7, RawFrm, (outs), (ins), "fincstp", [], IIC_FPSTP>, D9;
614 def FPREM : I<0xF8, RawFrm, (outs), (ins), "fprem", [], IIC_FPREM>, D9;
615 def FYL2XP1 : I<0xF9, RawFrm, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>, D9;
616 def FSINCOS : I<0xFB, RawFrm, (outs), (ins), "fsincos", [], IIC_FSINCOS>, D9;
617 def FRNDINT : I<0xFC, RawFrm, (outs), (ins), "frndint", [], IIC_FRNDINT>, D9;
618 def FSCALE : I<0xFD, RawFrm, (outs), (ins), "fscale", [], IIC_FSCALE>, D9;
619 def FCOMPP : I<0xD9, RawFrm, (outs), (ins), "fcompp", [], IIC_FCOMPP>, DE;
599 def FNOP : I<0xD9, MRM_D0, (outs), (ins), "fnop", [], IIC_FNOP>;
600 def FXAM : I<0xD9, MRM_E5, (outs), (ins), "fxam", [], IIC_FXAM>;
601 def FLDL2T : I<0xD9, MRM_E9, (outs), (ins), "fldl2t", [], IIC_FLDL>;
602 def FLDL2E : I<0xD9, MRM_EA, (outs), (ins), "fldl2e", [], IIC_FLDL>;
603 def FLDPI : I<0xD9, MRM_EB, (outs), (ins), "fldpi", [], IIC_FLDL>;
604 def FLDLG2 : I<0xD9, MRM_EC, (outs), (ins), "fldlg2", [], IIC_FLDL>;
605 def FLDLN2 : I<0xD9, MRM_ED, (outs), (ins), "fldln2", [], IIC_FLDL>;
606 def F2XM1 : I<0xD9, MRM_F0, (outs), (ins), "f2xm1", [], IIC_F2XM1>;
607 def FYL2X : I<0xD9, MRM_F1, (outs), (ins), "fyl2x", [], IIC_FYL2X>;
608 def FPTAN : I<0xD9, MRM_F2, (outs), (ins), "fptan", [], IIC_FPTAN>;
609 def FPATAN : I<0xD9, MRM_F3, (outs), (ins), "fpatan", [], IIC_FPATAN>;
610 def FXTRACT : I<0xD9, MRM_F4, (outs), (ins), "fxtract", [], IIC_FXTRACT>;
611 def FPREM1 : I<0xD9, MRM_F5, (outs), (ins), "fprem1", [], IIC_FPREM1>;
612 def FDECSTP : I<0xD9, MRM_F6, (outs), (ins), "fdecstp", [], IIC_FPSTP>;
613 def FINCSTP : I<0xD9, MRM_F7, (outs), (ins), "fincstp", [], IIC_FPSTP>;
614 def FPREM : I<0xD9, MRM_F8, (outs), (ins), "fprem", [], IIC_FPREM>;
615 def FYL2XP1 : I<0xD9, MRM_F9, (outs), (ins), "fyl2xp1", [], IIC_FYL2XP1>;
616 def FSINCOS : I<0xD9, MRM_FB, (outs), (ins), "fsincos", [], IIC_FSINCOS>;
617 def FRNDINT : I<0xD9, MRM_FC, (outs), (ins), "frndint", [], IIC_FRNDINT>;
618 def FSCALE : I<0xD9, MRM_FD, (outs), (ins), "fscale", [], IIC_FSCALE>;
619 def FCOMPP : I<0xDE, MRM_D9, (outs), (ins), "fcompp", [], IIC_FCOMPP>;
620620
621621 def FXSAVE : I<0xAE, MRM0m, (outs opaque512mem:$dst), (ins),
622622 "fxsave\t$dst", [], IIC_FXSAVE>, TB;
1313 // Format specifies the encoding used by the instruction. This is part of the
1414 // ad-hoc solution used to emit machine instruction encodings by our machine
1515 // code emitter.
16 class Format val> {
17 bits<6> Value = val;
16 class Format val> {
17 bits<7> Value = val;
1818 }
1919
2020 def Pseudo : Format<0>; def RawFrm : Format<1>;
3232 def MRM0m : Format<24>; def MRM1m : Format<25>; def MRM2m : Format<26>;
3333 def MRM3m : Format<27>; def MRM4m : Format<28>; def MRM5m : Format<29>;
3434 def MRM6m : Format<30>; def MRM7m : Format<31>;
35 def MRM_C0 : Format<32>;
36 def MRM_C1 : Format<33>;
37 def MRM_C2 : Format<34>;
38 def MRM_C3 : Format<35>;
39 def MRM_C4 : Format<36>;
40 def MRM_C8 : Format<37>;
41 def MRM_C9 : Format<38>;
42 def MRM_CA : Format<39>;
43 def MRM_CB : Format<40>;
44 def MRM_D0 : Format<41>;
45 def MRM_D1 : Format<42>;
46 def MRM_D4 : Format<43>;
47 def MRM_D5 : Format<44>;
48 def MRM_D6 : Format<45>;
49 def MRM_D8 : Format<46>;
50 def MRM_D9 : Format<47>;
51 def MRM_DA : Format<48>;
52 def MRM_DB : Format<49>;
53 def MRM_DC : Format<50>;
54 def MRM_DD : Format<51>;
55 def MRM_DE : Format<52>;
56 def MRM_DF : Format<53>;
57 def MRM_E0 : Format<54>;
58 def MRM_E8 : Format<55>;
59 def MRM_F0 : Format<56>;
60 def MRM_F8 : Format<57>;
61 def MRM_F9 : Format<58>;
35 def MRM_C0 : Format<32>; def MRM_C1 : Format<33>; def MRM_C2 : Format<34>;
36 def MRM_C3 : Format<35>; def MRM_C4 : Format<36>; def MRM_C8 : Format<37>;
37 def MRM_C9 : Format<38>; def MRM_CA : Format<39>; def MRM_CB : Format<40>;
38 def MRM_D0 : Format<41>; def MRM_D1 : Format<42>; def MRM_D4 : Format<43>;
39 def MRM_D5 : Format<44>; def MRM_D6 : Format<45>; def MRM_D8 : Format<46>;
40 def MRM_D9 : Format<47>; def MRM_DA : Format<48>; def MRM_DB : Format<49>;
41 def MRM_DC : Format<50>; def MRM_DD : Format<51>; def MRM_DE : Format<52>;
42 def MRM_DF : Format<53>; def MRM_E0 : Format<54>; def MRM_E1 : Format<55>;
43 def MRM_E2 : Format<56>; def MRM_E3 : Format<57>; def MRM_E4 : Format<58>;
44 def MRM_E5 : Format<59>; def MRM_E8 : Format<60>; def MRM_E9 : Format<61>;
45 def MRM_EA : Format<62>; def MRM_EB : Format<63>; def MRM_EC : Format<64>;
46 def MRM_ED : Format<65>; def MRM_EE : Format<66>; def MRM_F0 : Format<67>;
47 def MRM_F1 : Format<68>; def MRM_F2 : Format<69>; def MRM_F3 : Format<70>;
48 def MRM_F4 : Format<71>; def MRM_F5 : Format<72>; def MRM_F6 : Format<73>;
49 def MRM_F7 : Format<74>; def MRM_F8 : Format<75>; def MRM_F9 : Format<76>;
50 def MRM_FA : Format<77>; def MRM_FB : Format<78>; def MRM_FC : Format<79>;
51 def MRM_FD : Format<80>; def MRM_FE : Format<81>; def MRM_FF : Format<82>;
6252
6353 // ImmType - This specifies the immediate type used by an instruction. This is
6454 // part of the ad-hoc solution used to emit machine instruction encodings by our
125115 def XD : Prefix<4>;
126116
127117 // Class specifying the opcode map.
128 class Map val> {
129 bits<4> Value = val;
118 class Map val> {
119 bits<3> Value = val;
130120 }
131121 def OB : Map<0>;
132122 def TB : Map<1>;
135125 def XOP8 : Map<4>;
136126 def XOP9 : Map<5>;
137127 def XOPA : Map<6>;
138 def D8 : Map<7>;
139 def D9 : Map<8>;
140 def DA : Map<9>;
141 def DB : Map<10>;
142 def DC : Map<11>;
143 def DD : Map<12>;
144 def DE : Map<13>;
145 def DF : Map<14>;
146128
147129 // Class specifying the encoding
148130 class Encoding val> {
170152 class LOCK { bit hasLockPrefix = 1; }
171153 class REP { bit hasREPPrefix = 1; }
172154 class TB { Map OpMap = TB; }
173 class D8 { Map OpMap = D8; }
174 class D9 { Map OpMap = D9; }
175 class DA { Map OpMap = DA; }
176 class DB { Map OpMap = DB; }
177 class DC { Map OpMap = DC; }
178 class DD { Map OpMap = DD; }
179 class DE { Map OpMap = DE; }
180 class DF { Map OpMap = DF; }
181155 class T8 { Map OpMap = T8; }
182156 class TA { Map OpMap = TA; }
183157 class XOP8 { Map OpMap = XOP8; Prefix OpPrefix = PS; }
230204
231205 bits<8> Opcode = opcod;
232206 Format Form = f;
233 bits<6> FormBits = Form.Value;
207 bits<7> FormBits = Form.Value;
234208 ImmType ImmT = i;
235209
236210 dag OutOperandList = outs;
280254 bit hasEVEX_RC = 0; // Explicitly specified rounding control in FP instruction.
281255
282256 // TSFlags layout should be kept in sync with X86InstrInfo.h.
283 let TSFlags{5-0} = FormBits;
284 let TSFlags{7-6} = OpSize.Value;
285 let TSFlags{8} = hasAdSizePrefix;
286 let TSFlags{11-9} = OpPrefix.Value;
287 let TSFlags{15-12} = OpMap.Value;
257 let TSFlags{6-0} = FormBits;
258 let TSFlags{8-7} = OpSize.Value;
259 let TSFlags{9} = hasAdSizePrefix;
260 let TSFlags{12-10} = OpPrefix.Value;
261 let TSFlags{15-13} = OpMap.Value;
288262 let TSFlags{16} = hasREX_WPrefix;
289263 let TSFlags{20-17} = ImmT.Value;
290264 let TSFlags{23-21} = FPForm.Value;
22 xstore
33 // CHECK: xstore
44 // CHECK: encoding: [0x0f,0xa7,0xc0]
5
6 xstorerng
7 // CHECK: xstore
8 // CHECK: encoding: [0x0f,0xa7,0xc0]
9
10 rep xcryptecb
11 // CHECK: rep
12 // CHECK: encoding: [0xf3]
13 // CHECK: xcryptecb
14 // CHECK: encoding: [0x0f,0xa7,0xc8]
15
16 rep xcryptcbc
17 // CHECK: rep
18 // CHECK: encoding: [0xf3]
19 // CHECK: xcryptcbc
20 // CHECK: encoding: [0x0f,0xa7,0xd0]
21
22 rep xcryptctr
23 // CHECK: rep
24 // CHECK: encoding: [0xf3]
25 // CHECK: xcryptctr
26 // CHECK: encoding: [0x0f,0xa7,0xd8]
27
28 rep xcryptcfb
29 // CHECK: rep
30 // CHECK: encoding: [0xf3]
31 // CHECK: xcryptcfb
32 // CHECK: encoding: [0x0f,0xa7,0xe0]
33
34 rep xcryptofb
35 // CHECK: rep
36 // CHECK: encoding: [0xf3]
37 // CHECK: xcryptofb
38 // CHECK: encoding: [0x0f,0xa7,0xe8]
39
40 rep xsha1
41 // CHECK: rep
42 // CHECK: encoding: [0xf3]
43 // CHECK: xsha1
44 // CHECK: encoding: [0x0f,0xa6,0xc8]
45
46 rep xsha256
47 // CHECK: rep
48 // CHECK: encoding: [0xf3]
49 // CHECK: xsha256
50 // CHECK: encoding: [0x0f,0xa6,0xd0]
51
52 rep montmul
53 // CHECK: rep
54 // CHECK: encoding: [0xf3]
55 // CHECK: montmul
56 // CHECK: encoding: [0x0f,0xa6,0xc0]
4545 MAP(DE, 52) \
4646 MAP(DF, 53) \
4747 MAP(E0, 54) \
48 MAP(E8, 55) \
49 MAP(F0, 56) \
50 MAP(F8, 57) \
51 MAP(F9, 58)
48 MAP(E1, 55) \
49 MAP(E2, 56) \
50 MAP(E3, 57) \
51 MAP(E4, 58) \
52 MAP(E5, 59) \
53 MAP(E8, 60) \
54 MAP(E9, 61) \
55 MAP(EA, 62) \
56 MAP(EB, 63) \
57 MAP(EC, 64) \
58 MAP(ED, 65) \
59 MAP(EE, 66) \
60 MAP(F0, 67) \
61 MAP(F1, 68) \
62 MAP(F2, 69) \
63 MAP(F3, 70) \
64 MAP(F4, 71) \
65 MAP(F5, 72) \
66 MAP(F6, 73) \
67 MAP(F7, 74) \
68 MAP(F8, 75) \
69 MAP(F9, 76) \
70 MAP(FA, 77) \
71 MAP(FB, 78) \
72 MAP(FC, 79) \
73 MAP(FD, 80) \
74 MAP(FE, 81) \
75 MAP(FF, 82)
5276
5377 // A clone of X86 since we can't depend on something that is generated.
5478 namespace X86Local {
78102 };
79103
80104 enum {
81 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6,
82 D8 = 7, D9 = 8, DA = 9, DB = 10,
83 DC = 11, DD = 12, DE = 13, DF = 14
105 OB = 0, TB = 1, T8 = 2, TA = 3, XOP8 = 4, XOP9 = 5, XOPA = 6
84106 };
85107
86108 enum {
731753 HANDLE_OPERAND(relocation)
732754 }
733755 break;
734 case X86Local::MRM_C0:
735 case X86Local::MRM_C1:
736 case X86Local::MRM_C2:
737 case X86Local::MRM_C3:
738 case X86Local::MRM_C4:
739 case X86Local::MRM_C8:
740 case X86Local::MRM_C9:
741 case X86Local::MRM_CA:
742 case X86Local::MRM_CB:
743 case X86Local::MRM_E8:
744 case X86Local::MRM_F0:
745 case X86Local::MRM_F9:
746 case X86Local::MRM_D0:
747 case X86Local::MRM_D1:
748 case X86Local::MRM_D4:
749 case X86Local::MRM_D5:
750 case X86Local::MRM_D6:
751 case X86Local::MRM_D8:
752 case X86Local::MRM_D9:
753 case X86Local::MRM_DA:
754 case X86Local::MRM_DB:
755 case X86Local::MRM_DC:
756 case X86Local::MRM_DD:
757 case X86Local::MRM_DE:
758 case X86Local::MRM_DF:
759 case X86Local::MRM_E0:
756 case X86Local::MRM_C0: case X86Local::MRM_C1: case X86Local::MRM_C2:
757 case X86Local::MRM_C3: case X86Local::MRM_C4: case X86Local::MRM_C8:
758 case X86Local::MRM_C9: case X86Local::MRM_CA: case X86Local::MRM_CB:
759 case X86Local::MRM_D0: case X86Local::MRM_D1: case X86Local::MRM_D4:
760 case X86Local::MRM_D5: case X86Local::MRM_D6: case X86Local::MRM_D8:
761 case X86Local::MRM_D9: case X86Local::MRM_DA: case X86Local::MRM_DB:
762 case X86Local::MRM_DC: case X86Local::MRM_DD: case X86Local::MRM_DE:
763 case X86Local::MRM_DF: case X86Local::MRM_E0: case X86Local::MRM_E1:
764 case X86Local::MRM_E2: case X86Local::MRM_E3: case X86Local::MRM_E4:
765 case X86Local::MRM_E5: case X86Local::MRM_E8: case X86Local::MRM_E9:
766 case X86Local::MRM_EA: case X86Local::MRM_EB: case X86Local::MRM_EC:
767 case X86Local::MRM_ED: case X86Local::MRM_EE: case X86Local::MRM_F0:
768 case X86Local::MRM_F1: case X86Local::MRM_F2: case X86Local::MRM_F3:
769 case X86Local::MRM_F4: case X86Local::MRM_F5: case X86Local::MRM_F6:
770 case X86Local::MRM_F7: case X86Local::MRM_F9: case X86Local::MRM_FA:
771 case X86Local::MRM_FB: case X86Local::MRM_FC: case X86Local::MRM_FD:
772 case X86Local::MRM_FE: case X86Local::MRM_FF:
760773 // Ignored.
761774 break;
762775 }
823836 } // switch (Form)
824837
825838 opcodeToSet = Opcode;
826 break;
827 case X86Local::D8:
828 case X86Local::D9:
829 case X86Local::DA:
830 case X86Local::DB:
831 case X86Local::DC:
832 case X86Local::DD:
833 case X86Local::DE:
834 case X86Local::DF:
835 assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode");
836 assert(Form == X86Local::RawFrm);
837 opcodeType = ONEBYTE;
838 filter = new ExactFilter(Opcode);
839 opcodeToSet = 0xd8 + (OpMap - X86Local::D8);
840839 break;
841840 } // switch (OpMap)
842841