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Merging r348461: ------------------------------------------------------------------------ r348461 | lebedevri | 2018-12-06 00:11:20 -0800 (Thu, 06 Dec 2018) | 4 lines [NFC][InstCombine] Add more miscompile tests for foldICmpWithLowBitMaskedVal() We also have to me aware of vector constants. If at least one element is -1, we can't transform. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_70@348535 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 10 months ago
2 changed file(s) with 74 addition(s) and 26 deletion(s). Raw diff Collapse all Expand all
1919 ;
2020 %tmp0 = and i8 %x, 3
2121 %ret = icmp sge i8 %tmp0, %x
22 ret i1 %ret
23 }
24
25 define i1 @pv(i8 %x, i8 %y) {
26 ; CHECK-LABEL: @pv(
27 ; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
28 ; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
29 ; CHECK-NEXT: [[RET:%.*]] = icmp sge i8 [[TMP1]], [[X]]
30 ; CHECK-NEXT: ret i1 [[RET]]
31 ;
32 %tmp0 = lshr i8 -1, %y
33 %tmp1 = and i8 %tmp0, %x
34 %ret = icmp sge i8 %tmp1, %x
3522 ret i1 %ret
3623 }
3724
197184 %ret = icmp sge <2 x i8> %tmp0, %x
198185 ret <2 x i1> %ret
199186 }
187
188 ; ============================================================================ ;
189 ; Potential miscompiles.
190 ; ============================================================================ ;
191
192 define i1 @nv(i8 %x, i8 %y) {
193 ; CHECK-LABEL: @nv(
194 ; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
195 ; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
196 ; CHECK-NEXT: [[RET:%.*]] = icmp sge i8 [[TMP1]], [[X]]
197 ; CHECK-NEXT: ret i1 [[RET]]
198 ;
199 %tmp0 = lshr i8 -1, %y
200 %tmp1 = and i8 %tmp0, %x
201 %ret = icmp sge i8 %tmp1, %x
202 ret i1 %ret
203 }
204
205 define <2 x i1> @n3_vec(<2 x i8> %x) {
206 ; CHECK-LABEL: @n3_vec(
207 ; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <2 x i8> [[X:%.*]],
208 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
209 ;
210 %tmp0 = and <2 x i8> %x,
211 %ret = icmp sge <2 x i8> %tmp0, %x
212 ret <2 x i1> %ret
213 }
214
215 define <3 x i1> @n4_vec(<3 x i8> %x) {
216 ; CHECK-LABEL: @n4_vec(
217 ; CHECK-NEXT: [[TMP1:%.*]] = icmp slt <3 x i8> [[X:%.*]],
218 ; CHECK-NEXT: ret <3 x i1> [[TMP1]]
219 ;
220 %tmp0 = and <3 x i8> %x,
221 %ret = icmp sge <3 x i8> %tmp0, %x
222 ret <3 x i1> %ret
223 }
1919 ;
2020 %tmp0 = and i8 %x, 3
2121 %ret = icmp slt i8 %tmp0, %x
22 ret i1 %ret
23 }
24
25 define i1 @pv(i8 %x, i8 %y) {
26 ; CHECK-LABEL: @pv(
27 ; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
28 ; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
29 ; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[TMP1]], [[X]]
30 ; CHECK-NEXT: ret i1 [[RET]]
31 ;
32 %tmp0 = lshr i8 -1, %y
33 %tmp1 = and i8 %tmp0, %x
34 %ret = icmp slt i8 %tmp1, %x
3522 ret i1 %ret
3623 }
3724
197184 %ret = icmp slt <2 x i8> %tmp0, %x
198185 ret <2 x i1> %ret
199186 }
187
188 ; ============================================================================ ;
189 ; Potential miscompiles.
190 ; ============================================================================ ;
191
192 define i1 @nv(i8 %x, i8 %y) {
193 ; CHECK-LABEL: @nv(
194 ; CHECK-NEXT: [[TMP0:%.*]] = lshr i8 -1, [[Y:%.*]]
195 ; CHECK-NEXT: [[TMP1:%.*]] = and i8 [[TMP0]], [[X:%.*]]
196 ; CHECK-NEXT: [[RET:%.*]] = icmp slt i8 [[TMP1]], [[X]]
197 ; CHECK-NEXT: ret i1 [[RET]]
198 ;
199 %tmp0 = lshr i8 -1, %y
200 %tmp1 = and i8 %tmp0, %x
201 %ret = icmp slt i8 %tmp1, %x
202 ret i1 %ret
203 }
204
205 define <2 x i1> @n3(<2 x i8> %x) {
206 ; CHECK-LABEL: @n3(
207 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <2 x i8> [[X:%.*]],
208 ; CHECK-NEXT: ret <2 x i1> [[TMP1]]
209 ;
210 %tmp0 = and <2 x i8> %x,
211 %ret = icmp slt <2 x i8> %tmp0, %x
212 ret <2 x i1> %ret
213 }
214
215 define <3 x i1> @n4(<3 x i8> %x) {
216 ; CHECK-LABEL: @n4(
217 ; CHECK-NEXT: [[TMP1:%.*]] = icmp sgt <3 x i8> [[X:%.*]],
218 ; CHECK-NEXT: ret <3 x i1> [[TMP1]]
219 ;
220 %tmp0 = and <3 x i8> %x,
221 %ret = icmp slt <3 x i8> %tmp0, %x
222 ret <3 x i1> %ret
223 }