llvm.org GIT mirror llvm / f99a4b8
Followup to 132458, omit unnecessary stack copy when x87 input is a load. rdar://problem/6373334 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@132696 91177308-0d34-0410-b5e6-96231b3b80d8 Stuart Hastings 8 years ago
3 changed file(s) with 56 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
10961096 setTargetDAGCombine(ISD::SUB);
10971097 setTargetDAGCombine(ISD::STORE);
10981098 setTargetDAGCombine(ISD::ZERO_EXTEND);
1099 setTargetDAGCombine(ISD::SINT_TO_FP);
10991100 if (Subtarget->is64Bit())
11001101 setTargetDAGCombine(ISD::MUL);
11011102
66996700 DebugLoc dl = Op.getDebugLoc();
67006701 unsigned Size = SrcVT.getSizeInBits()/8;
67016702 MachineFunction &MF = DAG.getMachineFunction();
6702
6703 SDValue Addr = Op.getOperand(0);
6704 if (Addr.getOpcode() == ISD::LOAD)
6705 return BuildFILD(Op, SrcVT, DAG.getEntryNode(), Addr, DAG);
6706
67076703 int SSFI = MF.getFrameInfo()->CreateStackObject(Size, Size, false);
67086704 SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
67096705 SDValue Chain = DAG.getStore(DAG.getEntryNode(), dl, Op.getOperand(0),
1216812164 return SDValue();
1216912165 }
1217012166
12167 static SDValue PerformSINT_TO_FPCombine(SDNode *N, SelectionDAG &DAG, const X86TargetLowering *XTLI) {
12168 DebugLoc dl = N->getDebugLoc();
12169 SDValue Op0 = N->getOperand(0);
12170 // Transform (SINT_TO_FP (i64 ...)) into an x87 operation if we have
12171 // a 32-bit target where SSE doesn't support i64->FP operations.
12172 if (Op0.getOpcode() == ISD::LOAD) {
12173 LoadSDNode *Ld = cast(Op0.getNode());
12174 EVT VT = Ld->getValueType(0);
12175 if (!Ld->isVolatile() && !N->getValueType(0).isVector() &&
12176 ISD::isNON_EXTLoad(Op0.getNode()) && Op0.hasOneUse() &&
12177 !XTLI->getSubtarget()->is64Bit() &&
12178 !DAG.getTargetLoweringInfo().isTypeLegal(VT)) {
12179 SDValue FILDChain = XTLI->BuildFILD(SDValue(N, 0), Ld->getValueType(0), Ld->getChain(), Op0, DAG);
12180 DAG.ReplaceAllUsesOfValueWith(Op0.getValue(1), FILDChain.getValue(1));
12181 return FILDChain;
12182 }
12183 }
12184 return SDValue();
12185 }
12186
1217112187 // Optimize RES, EFLAGS = X86ISD::ADC LHS, RHS, EFLAGS
1217212188 static SDValue PerformADCCombine(SDNode *N, SelectionDAG &DAG,
1217312189 X86TargetLowering::DAGCombinerInfo &DCI) {
1225212268 case ISD::AND: return PerformAndCombine(N, DAG, DCI, Subtarget);
1225312269 case ISD::OR: return PerformOrCombine(N, DAG, DCI, Subtarget);
1225412270 case ISD::STORE: return PerformSTORECombine(N, DAG, Subtarget);
12271 case ISD::SINT_TO_FP: return PerformSINT_TO_FPCombine(N, DAG, this);
1225512272 case X86ISD::FXOR:
1225612273 case X86ISD::FOR: return PerformFORCombine(N, DAG);
1225712274 case X86ISD::FAND: return PerformFANDCombine(N, DAG);
688688 /// appropriate.
689689 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
690690
691 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
692 SelectionDAG &DAG) const;
693
691694 protected:
692695 std::pair
693696 findRepresentativeClass(EVT VT) const;
779782 SDValue LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const;
780783 SDValue LowerExternalSymbol(SDValue Op, SelectionDAG &DAG) const;
781784 SDValue LowerShiftParts(SDValue Op, SelectionDAG &DAG) const;
782 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
783 SelectionDAG &DAG) const;
784785 SDValue LowerBITCAST(SDValue op, SelectionDAG &DAG) const;
785786 SDValue LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
786787 SDValue LowerUINT_TO_FP(SDValue Op, SelectionDAG &DAG) const;
0 ; RUN: llc < %s -march=x86 | FileCheck %s
1
2 define float @chainfail1(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp {
3 entry:
4 %tmp1 = load i64* %a, align 8
5 ; Insure x87 ops are properly chained, order preserved.
6 ; CHECK: fildll
7 %conv = sitofp i64 %tmp1 to float
8 ; CHECK: fstps
9 store float %conv, float* %f, align 4
10 ; CHECK: idivl
11 %div = sdiv i32 %x, %y
12 %conv5 = sext i32 %div to i64
13 store i64 %conv5, i64* %b, align 8
14 ret float %conv
15 }
16
17 define float @chainfail2(i64* nocapture %a, i64* nocapture %b, i32 %x, i32 %y, float* nocapture %f) nounwind uwtable noinline ssp {
18 entry:
19 ; CHECK: movl $0,
20 store i64 0, i64* %b, align 8
21 %mul = mul nsw i32 %y, %x
22 %sub = add nsw i32 %mul, -1
23 %idxprom = sext i32 %sub to i64
24 %arrayidx = getelementptr inbounds i64* %a, i64 %idxprom
25 %tmp4 = load i64* %arrayidx, align 8
26 ; CHECK: fildll
27 %conv = sitofp i64 %tmp4 to float
28 store float %conv, float* %f, align 4
29 ret float %conv
30 }