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AMDGPU: Start adding global_* instructions git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@305838 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
7 changed file(s) with 193 addition(s) and 6 deletion(s). Raw diff Collapse all Expand all
643643 "Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS">,
644644 AssemblerPredicate<"FeatureCIInsts">;
645645
646 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">;
646 def HasFlatAddressSpace : Predicate<"Subtarget->hasFlatAddressSpace()">,
647 AssemblerPredicate<"FeatureFlatAddressSpace">;
648
649 def HasFlatGlobalInsts : Predicate<"Subtarget->hasFlatGlobalInsts()">,
650 AssemblerPredicate<"FeatureFlatGlobalInsts">;
647651
648652 def Has16BitInsts : Predicate<"Subtarget->has16BitInsts()">,
649653 AssemblerPredicate<"Feature16BitInsts">;
10411041 AMDGPUOperand::Ptr defaultSMRDOffset20() const;
10421042 AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
10431043 AMDGPUOperand::Ptr defaultOffsetU12() const;
1044 AMDGPUOperand::Ptr defaultOffsetS13() const;
10441045
10451046 OperandMatchResultTy parseOModOperand(OperandVector &Operands);
10461047
25532554 return MatchOperand_ParseFail;
25542555
25552556 Parser.Lex();
2557
2558 bool IsMinus = false;
2559 if (getLexer().getKind() == AsmToken::Minus) {
2560 Parser.Lex();
2561 IsMinus = true;
2562 }
2563
25562564 if (getLexer().isNot(AsmToken::Integer))
25572565 return MatchOperand_ParseFail;
25582566
25592567 if (getParser().parseAbsoluteExpression(Int))
25602568 return MatchOperand_ParseFail;
2569
2570 if (IsMinus)
2571 Int = -Int;
25612572 break;
25622573 }
25632574 }
38693880 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
38703881 }
38713882
3883 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultOffsetS13() const {
3884 return AMDGPUOperand::CreateImm(this, 0, SMLoc(), AMDGPUOperand::ImmTyOffset);
3885 }
3886
38723887 //===----------------------------------------------------------------------===//
38733888 // vop3
38743889 //===----------------------------------------------------------------------===//
3030 let VM_CNT = 1;
3131 let LGKM_CNT = 1;
3232
33 let Uses = [EXEC, FLAT_SCR]; // M0
34
3533 let UseNamedOperandTable = 1;
3634 let hasSideEffects = 0;
3735 let SchedRW = [WriteVMEM];
3836
3937 string Mnemonic = opName;
4038 string AsmOperands = asmOps;
39
40 bits<1> is_flat_global = 0;
41 bits<1> is_flat_scratch = 0;
4142
4243 bits<1> has_vdst = 1;
4344 bits<1> has_data = 1;
4445 bits<1> has_glc = 1;
4546 bits<1> glcValue = 0;
47
48 // TODO: M0 if it could possibly access LDS (before gfx9? only)?
49 let Uses = !if(is_flat_global, [EXEC], [EXEC, FLAT_SCR]);
4650 }
4751
4852 class FLAT_Real op, FLAT_Pseudo ps> :
6771
6872 // Only valid on gfx9
6973 bits<1> lds = 0; // XXX - What does this actually do?
70 bits<2> seg; // Segment, 00=flat, 01=scratch, 10=global, 11=reserved
74
75 // Segment, 00=flat, 01=scratch, 10=global, 11=reserved
76 bits<2> seg = !if(ps.is_flat_global, 0b10,
77 !if(ps.is_flat_scratch, 0b01, 0));
7178
7279 // Signed offset. Highest bit ignored for flat and treated as 12-bit
7380 // unsigned for flat acceses.
8087 // Only valid on GFX9+
8188 let Inst{12-0} = offset;
8289 let Inst{13} = lds;
83 let Inst{15-14} = 0;
90 let Inst{15-14} = seg;
8491
8592 let Inst{16} = !if(ps.has_glc, glc, ps.glcValue);
8693 let Inst{17} = slc;
103110 " $vdst, $vaddr$offset$glc$slc"> {
104111 let has_data = 0;
105112 let mayLoad = 1;
113 }
114
115 class FLAT_Global_Load_Pseudo :
116 FLAT_Load_Pseudo {
117 let is_flat_global = 1;
118 }
119
120 class FLAT_Scratch_Load_Pseudo :
121 FLAT_Load_Pseudo {
122 let is_flat_scratch = 1;
106123 }
107124
108125 class FLAT_Store_Pseudo
116133 let mayLoad = 0;
117134 let mayStore = 1;
118135 let has_vdst = 0;
136 }
137
138 class FLAT_Global_Store_Pseudo :
139 FLAT_Store_Pseudo {
140 let is_flat_global = 1;
141 }
142
143 class FLAT_Scratch_Store_Pseudo :
144 FLAT_Store_Pseudo {
145 let is_flat_scratch = 1;
119146 }
120147
121148 multiclass FLAT_Atomic_Pseudo<
304331 VReg_64, f64>;
305332
306333 } // End SubtargetPredicate = isCI
334
335 let SubtargetPredicate = HasFlatGlobalInsts in {
336 def GLOBAL_LOAD_UBYTE : FLAT_Global_Load_Pseudo <"global_load_ubyte", VGPR_32>;
337 def GLOBAL_LOAD_SBYTE : FLAT_Global_Load_Pseudo <"global_load_sbyte", VGPR_32>;
338 def GLOBAL_LOAD_USHORT : FLAT_Global_Load_Pseudo <"global_load_ushort", VGPR_32>;
339 def GLOBAL_LOAD_SSHORT : FLAT_Global_Load_Pseudo <"global_load_sshort", VGPR_32>;
340 def GLOBAL_LOAD_DWORD : FLAT_Global_Load_Pseudo <"global_load_dword", VGPR_32>;
341 def GLOBAL_LOAD_DWORDX2 : FLAT_Global_Load_Pseudo <"global_load_dwordx2", VReg_64>;
342 def GLOBAL_LOAD_DWORDX3 : FLAT_Global_Load_Pseudo <"global_load_dwordx3", VReg_96>;
343 def GLOBAL_LOAD_DWORDX4 : FLAT_Global_Load_Pseudo <"global_load_dwordx4", VReg_128>;
344
345 def GLOBAL_STORE_BYTE : FLAT_Global_Store_Pseudo <"global_store_byte", VGPR_32>;
346 def GLOBAL_STORE_SHORT : FLAT_Global_Store_Pseudo <"global_store_short", VGPR_32>;
347 def GLOBAL_STORE_DWORD : FLAT_Global_Store_Pseudo <"global_store_dword", VGPR_32>;
348 def GLOBAL_STORE_DWORDX2 : FLAT_Global_Store_Pseudo <"global_store_dwordx2", VReg_64>;
349 def GLOBAL_STORE_DWORDX3 : FLAT_Global_Store_Pseudo <"global_store_dwordx3", VReg_96>;
350 def GLOBAL_STORE_DWORDX4 : FLAT_Global_Store_Pseudo <"global_store_dwordx4", VReg_128>;
351
352 } // End SubtargetPredicate = HasFlatGlobalInsts
353
307354
308355 //===----------------------------------------------------------------------===//
309356 // Flat Patterns
556603 defm FLAT_ATOMIC_INC_X2 : FLAT_Real_Atomics_vi <0x6b, FLAT_ATOMIC_INC_X2>;
557604 defm FLAT_ATOMIC_DEC_X2 : FLAT_Real_Atomics_vi <0x6c, FLAT_ATOMIC_DEC_X2>;
558605
606 def GLOBAL_LOAD_UBYTE_vi : FLAT_Real_vi <0x10, GLOBAL_LOAD_UBYTE>;
607 def GLOBAL_LOAD_SBYTE_vi : FLAT_Real_vi <0x11, GLOBAL_LOAD_SBYTE>;
608 def GLOBAL_LOAD_USHORT_vi : FLAT_Real_vi <0x12, GLOBAL_LOAD_USHORT>;
609 def GLOBAL_LOAD_SSHORT_vi : FLAT_Real_vi <0x13, GLOBAL_LOAD_SSHORT>;
610 def GLOBAL_LOAD_DWORD_vi : FLAT_Real_vi <0x14, GLOBAL_LOAD_DWORD>;
611 def GLOBAL_LOAD_DWORDX2_vi : FLAT_Real_vi <0x15, GLOBAL_LOAD_DWORDX2>;
612 def GLOBAL_LOAD_DWORDX4_vi : FLAT_Real_vi <0x17, GLOBAL_LOAD_DWORDX4>;
613 def GLOBAL_LOAD_DWORDX3_vi : FLAT_Real_vi <0x16, GLOBAL_LOAD_DWORDX3>;
614
615 def GLOBAL_STORE_BYTE_vi : FLAT_Real_vi <0x18, GLOBAL_STORE_BYTE>;
616 def GLOBAL_STORE_SHORT_vi : FLAT_Real_vi <0x1a, GLOBAL_STORE_SHORT>;
617 def GLOBAL_STORE_DWORD_vi : FLAT_Real_vi <0x1c, GLOBAL_STORE_DWORD>;
618 def GLOBAL_STORE_DWORDX2_vi : FLAT_Real_vi <0x1d, GLOBAL_STORE_DWORDX2>;
619 def GLOBAL_STORE_DWORDX4_vi : FLAT_Real_vi <0x1f, GLOBAL_STORE_DWORDX4>;
620 def GLOBAL_STORE_DWORDX3_vi : FLAT_Real_vi <0x1e, GLOBAL_STORE_DWORDX3>;
7171 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff);
7272 }
7373
74 void AMDGPUInstPrinter::printS16ImmDecOperand(const MCInst *MI, unsigned OpNo,
75 raw_ostream &O) {
76 O << formatDec(static_cast(MI->getOperand(OpNo).getImm()));
77 }
78
7479 void AMDGPUInstPrinter::printU32ImmOperand(const MCInst *MI, unsigned OpNo,
7580 const MCSubtargetInfo &STI,
7681 raw_ostream &O) {
114119 if (Imm != 0) {
115120 O << ((OpNo == 0)? "offset:" : " offset:");
116121 printU16ImmDecOperand(MI, OpNo, O);
122 }
123 }
124
125 void AMDGPUInstPrinter::printOffsetS13(const MCInst *MI, unsigned OpNo,
126 const MCSubtargetInfo &STI,
127 raw_ostream &O) {
128 uint16_t Imm = MI->getOperand(OpNo).getImm();
129 if (Imm != 0) {
130 O << ((OpNo == 0)? "offset:" : " offset:");
131 printS16ImmDecOperand(MI, OpNo, O);
117132 }
118133 }
119134
4141 void printU4ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4242 void printU8ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4343 void printU16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
44 void printS16ImmDecOperand(const MCInst *MI, unsigned OpNo, raw_ostream &O);
4445 void printU32ImmOperand(const MCInst *MI, unsigned OpNo,
4546 const MCSubtargetInfo &STI, raw_ostream &O);
4647 void printNamedBit(const MCInst *MI, unsigned OpNo, raw_ostream &O,
5152 void printMBUFOffset(const MCInst *MI, unsigned OpNo, raw_ostream &O);
5253 void printOffset(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
5354 raw_ostream &O);
55 void printOffsetS13(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
56 raw_ostream &O);
57
5458 void printOffset0(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
5559 raw_ostream &O);
5660 void printOffset1(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI,
524524 def addr64 : NamedOperandBit<"Addr64", NamedMatchClass<"Addr64">>;
525525
526526 def offset_u12 : NamedOperandU12<"Offset", NamedMatchClass<"OffsetU12">>;
527 def offset_s13 : NamedOperandS13<"Offset", NamedMatchClass<"OffsetS13">>;
527 def offset_s13 : NamedOperandS13<"OffsetS13", NamedMatchClass<"OffsetS13">>;
528528 def offset : NamedOperandU16<"Offset", NamedMatchClass<"Offset">>;
529529 def offset0 : NamedOperandU8<"Offset0", NamedMatchClass<"Offset0">>;
530530 def offset1 : NamedOperandU8<"Offset1", NamedMatchClass<"Offset1">>;
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding %s | FileCheck -check-prefix=GFX9 -check-prefix=GCN %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=gfx900 -show-encoding 2>&1 %s | FileCheck -check-prefix=GFX9-ERR -check-prefix=GCNERR %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding 2>&1 %s | FileCheck -check-prefix=VI-ERR -check-prefix=GCNERR %s
3
4 global_load_ubyte v1, v[3:4]
5 // GFX9: global_load_ubyte v1, v[3:4] ; encoding: [0x00,0x80,0x40,0xdc,0x03,0x00,0x00,0x01]
6 // VI-ERR: instruction not supported on this GPU
7
8 global_load_sbyte v1, v[3:4]
9 // GFX9: global_load_sbyte v1, v[3:4] ; encoding: [0x00,0x80,0x44,0xdc,0x03,0x00,0x00,0x01]
10 // VI-ERR: instruction not supported on this GPU
11
12 global_load_ushort v1, v[3:4]
13 // GFX9: global_load_ushort v1, v[3:4] ; encoding: [0x00,0x80,0x48,0xdc,0x03,0x00,0x00,0x01]
14 // VI-ERR: instruction not supported on this GPU
15
16 global_load_sshort v1, v[3:4]
17 // GFX9: global_load_sshort v1, v[3:4] ; encoding: [0x00,0x80,0x4c,0xdc,0x03,0x00,0x00,0x01]
18 // VI-ERR: instruction not supported on this GPU
19
20 global_load_dword v1, v[3:4]
21 // GFX9: global_load_dword v1, v[3:4] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x00,0x01]
22 // VI-ERR: instruction not supported on this GPU
23
24 global_load_dwordx2 v[1:2], v[3:4]
25 // GFX9: global_load_dwordx2 v[1:2], v[3:4] ; encoding: [0x00,0x80,0x54,0xdc,0x03,0x00,0x00,0x01]
26 // VI-ERR: instruction not supported on this GPU
27
28 global_load_dwordx3 v[1:3], v[3:4]
29 // GFX9: global_load_dwordx3 v[1:3], v[3:4] ; encoding: [0x00,0x80,0x58,0xdc,0x03,0x00,0x00,0x01]
30 // VI-ERR: instruction not supported on this GPU
31
32 global_load_dwordx4 v[1:4], v[3:4]
33 // GFX9: global_load_dwordx4 v[1:4], v[3:4] ; encoding: [0x00,0x80,0x5c,0xdc,0x03,0x00,0x00,0x01]
34 // VI-ERR: instruction not supported on this GPU
35 // FIXME: VI error should be instruction nto supported
36 global_load_dword v1, v[3:4] offset:0
37 // GFX9: global_load_dword v1, v[3:4] ; encoding: [0x00,0x80,0x50,0xdc,0x03,0x00,0x00,0x01]
38 // VI-ERR: :36: error: not a valid operand.
39
40 global_load_dword v1, v[3:4] offset:4095
41 // GFX9: global_load_dword v1, v[3:4] offset:4095 ; encoding: [0xff,0x8f,0x50,0xdc,0x03,0x00,0x00,0x01]
42 // VI-ERR: :36: error: not a valid operand.
43
44 global_load_dword v1, v[3:4] offset:-1
45 // GFX9: global_load_dword v1, v[3:4] offset:-1 ; encoding: [0xff,0x9f,0x50,0xdc,0x03,0x00,0x00,0x01]
46 // VI-ERR: :36: error: not a valid operand.
47
48 global_load_dword v1, v[3:4] offset:-4096
49 // GFX9: global_load_dword v1, v[3:4] offset:-4096 ; encoding: [0x00,0x90,0x50,0xdc,0x03,0x00,0x00,0x01]
50 // VI-ERR: :36: error: not a valid operand.
51
52 global_load_dword v1, v[3:4] offset:4096
53 // GFX9-ERR: :30: error: invalid operand for instruction
54 // VI-ERR: :36: error: not a valid operand.
55
56 global_load_dword v1, v[3:4] offset:-4097
57 // GFX9-ERR: :30: error: invalid operand for instruction
58 // VI-ERR: :36: error: not a valid operand.
59
60 global_store_byte v[3:4], v1
61 // GFX9: global_store_byte v[3:4], v1 ; encoding: [0x00,0x80,0x60,0xdc,0x03,0x01,0x00,0x00]
62 // VI-ERR: instruction not supported on this GPU
63
64 global_store_short v[3:4], v1
65 // GFX9: global_store_short v[3:4], v1 ; encoding: [0x00,0x80,0x68,0xdc,0x03,0x01,0x00,0x00]
66 // VI-ERR: instruction not supported on this GPU
67
68 global_store_dword v[3:4], v1
69 // GFX9: global_store_dword v[3:4], v1 ; encoding: [0x00,0x80,0x70,0xdc,0x03,0x01,0x00,0x00]
70 // VI-ERR: instruction not supported on this GPU
71
72 global_store_dwordx2 v[3:4], v[1:2]
73 // GFX9: global_store_dwordx2 v[3:4], v[1:2] ; encoding: [0x00,0x80,0x74,0xdc,0x03,0x01,0x00,0x00]
74 // VI-ERR: instruction not supported on this GPU
75
76 global_store_dwordx3 v[3:4], v[1:3]
77 // GFX9: global_store_dwordx3 v[3:4], v[1:3] ; encoding: [0x00,0x80,0x78,0xdc,0x03,0x01,0x00,0x00]
78 // VI-ERR: instruction not supported on this GPU
79
80 global_store_dwordx4 v[3:4], v[1:4]
81 // GFX9: global_store_dwordx4 v[3:4], v[1:4] ; encoding: [0x00,0x80,0x7c,0xdc,0x03,0x01,0x00,0x00]
82 // VI-ERR: instruction not supported on this GPU
83
84 global_store_dword v[3:4], v1 offset:12
85 // GFX9: global_store_dword v[3:4], v1 offset:12 ; encoding: [0x0c,0x80,0x70,0xdc,0x03,0x01,0x00,0x00]
86 // VI-ERR: :37: error: not a valid operand