llvm.org GIT mirror llvm / f955f29
Change ARM PKHTB and PKHBT instructions to use a shift_imm operand to avoid printing "lsl #0". This fixes the remaining parts of pr7792. Make corresponding changes for encoding/decoding these instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111251 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
9 changed file(s) with 80 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
12261226
12271227 // Encode shift_imm.
12281228 unsigned ShiftAmt = MI.getOperand(OpIdx).getImm();
1229 if (TID.Opcode == ARM::PKHTB) {
1230 assert(ShiftAmt != 0 && "PKHTB shift_imm is 0!");
1231 if (ShiftAmt == 32)
1232 ShiftAmt = 0;
1233 }
12291234 assert(ShiftAmt < 32 && "shift_imm range is 0 to 31!");
12301235 Binary |= ShiftAmt << ARMII::ShiftShift;
12311236
22392239 let Inst{19-16} = 0b1111;
22402240 }
22412241
2242 def lsl_shift_imm : SDNodeXForm
2243 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::lsl, N->getZExtValue());
2244 return CurDAG->getTargetConstant(Sh, MVT::i32);
2245 }]>;
2246
2247 def lsl_amt : PatLeaf<(i32 imm), [{
2248 return (N->getZExtValue() < 32);
2249 }], lsl_shift_imm>;
2250
22422251 def PKHBT : AMiscA1I<0b01101000, (outs GPR:$dst),
2243 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2244 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2252 (ins GPR:$src1, GPR:$src2, shift_imm:$sh),
2253 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
22452254 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF),
2246 (and (shl GPR:$src2, (i32 imm:$shamt)),
2255 (and (shl GPR:$src2, lsl_amt:$sh),
22472256 0xFFFF0000)))]>,
22482257 Requires<[IsARM, HasV6]> {
22492258 let Inst{6-4} = 0b001;
22522261 // Alternate cases for PKHBT where identities eliminate some nodes.
22532262 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (and GPR:$src2, 0xFFFF0000)),
22542263 (PKHBT GPR:$src1, GPR:$src2, 0)>;
2255 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$shamt)),
2256 (PKHBT GPR:$src1, GPR:$src2, imm16_31:$shamt)>;
2257
2264 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF), (shl GPR:$src2, imm16_31:$sh)),
2265 (PKHBT GPR:$src1, GPR:$src2, (lsl_shift_imm imm16_31:$sh))>;
2266
2267 def asr_shift_imm : SDNodeXForm
2268 unsigned Sh = ARM_AM::getSORegOpc(ARM_AM::asr, N->getZExtValue());
2269 return CurDAG->getTargetConstant(Sh, MVT::i32);
2270 }]>;
2271
2272 def asr_amt : PatLeaf<(i32 imm), [{
2273 return (N->getZExtValue() <= 32);
2274 }], asr_shift_imm>;
22582275
22592276 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
22602277 // will match the pattern below.
22612278 def PKHTB : AMiscA1I<0b01101000, (outs GPR:$dst),
2262 (ins GPR:$src1, GPR:$src2, i32imm:$shamt),
2263 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2279 (ins GPR:$src1, GPR:$src2, shift_imm:$sh),
2280 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh",
22642281 [(set GPR:$dst, (or (and GPR:$src1, 0xFFFF0000),
2265 (and (sra GPR:$src2, imm16_31:$shamt),
2266 0xFFFF)))]>, Requires<[IsARM, HasV6]> {
2282 (and (sra GPR:$src2, asr_amt:$sh),
2283 0xFFFF)))]>,
2284 Requires<[IsARM, HasV6]> {
22672285 let Inst{6-4} = 0b101;
22682286 }
22692287
22702288 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
22712289 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
22722290 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000), (srl GPR:$src2, imm16_31:$sh)),
2273 (PKHTB GPR:$src1, GPR:$src2, imm16_31:$sh)>;
2291 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm16_31:$sh))>;
22742292 def : ARMV6Pat<(or (and GPR:$src1, 0xFFFF0000),
2275 (and (srl GPR:$src2, imm1_15:$shamt), 0xFFFF)),
2276 (PKHTB GPR:$src1, GPR:$src2, imm1_15:$shamt)>;
2293 (and (srl GPR:$src2, imm1_15:$sh), 0xFFFF)),
2294 (PKHTB GPR:$src1, GPR:$src2, (asr_shift_imm imm1_15:$sh))>;
22772295
22782296 //===----------------------------------------------------------------------===//
22792297 // Comparison Instructions...
20842084 (or (srl (and rGPR:$src, 0xFF00), (i32 8)),
20852085 (shl rGPR:$src, (i32 8))), i16))]>;
20862086
2087 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
2088 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2, lsl $shamt",
2087 def t2PKHBT : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2088 IIC_iALUsi, "pkhbt", "\t$dst, $src1, $src2$sh",
20892089 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF),
2090 (and (shl rGPR:$src2, (i32 imm:$shamt)),
2090 (and (shl rGPR:$src2, lsl_amt:$sh),
20912091 0xFFFF0000)))]>,
20922092 Requires<[HasT2ExtractPack]> {
20932093 let Inst{31-27} = 0b11101;
21012101 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (and rGPR:$src2, 0xFFFF0000)),
21022102 (t2PKHBT rGPR:$src1, rGPR:$src2, 0)>,
21032103 Requires<[HasT2ExtractPack]>;
2104 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$shamt)),
2105 (t2PKHBT rGPR:$src1, rGPR:$src2, imm16_31:$shamt)>,
2104 def : T2Pat<(or (and rGPR:$src1, 0xFFFF), (shl rGPR:$src2, imm16_31:$sh)),
2105 (t2PKHBT rGPR:$src1, rGPR:$src2, (lsl_shift_imm imm16_31:$sh))>,
21062106 Requires<[HasT2ExtractPack]>;
21072107
21082108 // Note: Shifts of 1-15 bits will be transformed to srl instead of sra and
21092109 // will match the pattern below.
2110 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, i32imm:$shamt),
2111 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2, asr $shamt",
2110 def t2PKHTB : T2I<(outs rGPR:$dst), (ins rGPR:$src1, rGPR:$src2, shift_imm:$sh),
2111 IIC_iALUsi, "pkhtb", "\t$dst, $src1, $src2$sh",
21122112 [(set rGPR:$dst, (or (and rGPR:$src1, 0xFFFF0000),
2113 (and (sra rGPR:$src2, imm16_31:$shamt),
2114 0xFFFF)))]>,
2113 (and (sra rGPR:$src2, asr_amt:$sh),
2114 0xFFFF)))]>,
21152115 Requires<[HasT2ExtractPack]> {
21162116 let Inst{31-27} = 0b11101;
21172117 let Inst{26-25} = 0b01;
21232123 // Alternate cases for PKHTB where identities eliminate some nodes. Note that
21242124 // a shift amount of 0 is *not legal* here, it is PKHBT instead.
21252125 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000), (srl rGPR:$src2, imm16_31:$sh)),
2126 (t2PKHTB rGPR:$src1, rGPR:$src2, imm16_31:$sh)>,
2126 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm16_31:$sh))>,
21272127 Requires<[HasT2ExtractPack]>;
21282128 def : T2Pat<(or (and rGPR:$src1, 0xFFFF0000),
2129 (and (srl rGPR:$src2, imm1_15:$shamt), 0xFFFF)),
2130 (t2PKHTB rGPR:$src1, rGPR:$src2, imm1_15:$shamt)>,
2129 (and (srl rGPR:$src2, imm1_15:$sh), 0xFFFF)),
2130 (t2PKHTB rGPR:$src1, rGPR:$src2, (asr_shift_imm imm1_15:$sh))>,
21312131 Requires<[HasT2ExtractPack]>;
21322132
21332133 //===----------------------------------------------------------------------===//
455455 //
456456 // A8-11: DecodeImmShift()
457457 static inline void getImmShiftSE(ARM_AM::ShiftOpc &ShOp, unsigned &ShImm) {
458 // If type == 0b11 and imm5 == 0, we have an rrx, instead.
459 if (ShOp == ARM_AM::ror && ShImm == 0)
458 if (ShImm != 0)
459 return;
460 switch (ShOp) {
461 case ARM_AM::lsl:
462 ShOp = ARM_AM::no_shift;
463 break;
464 case ARM_AM::lsr:
465 case ARM_AM::asr:
466 ShImm = 32;
467 break;
468 case ARM_AM::ror:
460469 ShOp = ARM_AM::rrx;
461 // If (lsr or asr) and imm5 == 0, shift amount is 32.
462 if ((ShOp == ARM_AM::lsr || ShOp == ARM_AM::asr) && ShImm == 0)
463 ShImm = 32;
470 break;
471 }
464472 }
465473
466474 // getAMSubModeForBits - getAMSubModeForBits translates from the ARM encoding
14441452 && !OpInfo[OpIdx].isPredicate() && !OpInfo[OpIdx].isOptionalDef()) {
14451453 // Extract the 5-bit immediate field Inst{11-7}.
14461454 unsigned ShiftAmt = (insn >> ARMII::ShiftShift) & 0x1F;
1447 MI.addOperand(MCOperand::CreateImm(ShiftAmt));
1455 ARM_AM::ShiftOpc Opc = ARM_AM::no_shift;
1456 if (Opcode == ARM::PKHBT)
1457 Opc = ARM_AM::lsl;
1458 else if (Opcode == ARM::PKHBT)
1459 Opc = ARM_AM::asr;
1460 getImmShiftSE(Opc, ShiftAmt);
1461 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(Opc, ShiftAmt)));
14481462 ++OpIdx;
14491463 }
14501464
219219 switch (bits2) {
220220 default: assert(0 && "No such value");
221221 case 0:
222 ShOp = ARM_AM::lsl;
222 ShOp = (imm5 == 0 ? ARM_AM::no_shift : ARM_AM::lsl);
223223 return imm5;
224224 case 1:
225225 ShOp = ARM_AM::lsr;
13881388 unsigned imm5 = getShiftAmtBits(insn);
13891389 ARM_AM::ShiftOpc ShOp = ARM_AM::no_shift;
13901390 unsigned ShAmt = decodeImmShift(bits2, imm5, ShOp);
1391
1392 // PKHBT/PKHTB are special in that we need the decodeImmShift() call to
1393 // decode the shift amount from raw imm5 and bits2, but we DO NOT need
1394 // to encode the ShOp, as it's in the asm string already.
1395 if (Opcode == ARM::t2PKHBT || Opcode == ARM::t2PKHTB)
1396 MI.addOperand(MCOperand::CreateImm(ShAmt));
1397 else
1398 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt)));
1391 MI.addOperand(MCOperand::CreateImm(ARM_AM::getSORegOpc(ShOp, ShAmt)));
13991392 }
14001393 ++OpIdx;
14011394 }
3737 }
3838
3939 ; CHECK: test4
40 ; CHECK: pkhbt r0, r0, r1, lsl #0
40 ; CHECK: pkhbt r0, r0, r1
4141 define i32 @test4(i32 %X, i32 %Y) {
4242 %tmp1 = and i32 %X, 65535 ; [#uses=1]
4343 %tmp3 = and i32 %Y, -65536 ; [#uses=1]
3737 }
3838
3939 ; CHECK: test4
40 ; CHECK: pkhbt r0, r0, r1, lsl #0
40 ; CHECK: pkhbt r0, r0, r1
4141 define i32 @test4(i32 %X, i32 %Y) {
4242 %tmp1 = and i32 %X, 65535 ; [#uses=1]
4343 %tmp3 = and i32 %Y, -65536 ; [#uses=1]
6060 # CHECK: pkhbt r8, r9, r10, lsl #4
6161 0x1a 0x82 0x89 0xe6
6262
63 # CHECK-NOT: pkhbtls pc, r11, r11, lsl #0
64 # CHECK: pkhbtls pc, r11, r11
65 0x1b 0xf0 0x8b 0x96
66
6367 # CHECK: pop {r0, r2, r4, r6, r8, r10}
6468 0x55 0x05 0xbd 0xe8
6569
4040
4141 # CHECK: pkhtb r2, r4, r6, asr #16
4242 0xc4 0xea 0x26 0x42
43
44 # CHECK-NOT: pkhbt r2, r4, r6, lsl #0
45 # CHECK: pkhbt r2, r4, r6
46 0xc4 0xea 0x06 0x02
4347
4448 # CHECK: pop {r2, r4, r6, r8, r10, r12}
4549 0xbd 0xe8 0x54 0x15