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Add XTEST codegen support git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178083 91177308-0d34-0410-b5e6-96231b3b80d8 Michael Liao 7 years ago
6 changed file(s) with 36 addition(s) and 2 deletion(s). Raw diff Collapse all Expand all
25692569 Intrinsic<[], [], []>;
25702570 def int_x86_xabort : GCCBuiltin<"__builtin_ia32_xabort">,
25712571 Intrinsic<[], [llvm_i8_ty], [IntrNoReturn]>;
2572 }
2572 def int_x86_xtest : GCCBuiltin<"__builtin_ia32_xtest">,
2573 Intrinsic<[llvm_i32_ty], [], []>;
2574 }
1092910929 // Return { result, isValid, chain }.
1093010930 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(), Result, isValid,
1093110931 SDValue(Result.getNode(), 2));
10932 }
10933
10934 // XTEST intrinsics.
10935 case Intrinsic::x86_xtest: {
10936 SDVTList VTs = DAG.getVTList(Op->getValueType(0), MVT::Other);
10937 SDValue InTrans = DAG.getNode(X86ISD::XTEST, dl, VTs, Op.getOperand(0));
10938 SDValue SetCC = DAG.getNode(X86ISD::SETCC, dl, MVT::i8,
10939 DAG.getConstant(X86::COND_NE, MVT::i8),
10940 InTrans);
10941 SDValue Ret = DAG.getNode(ISD::ZERO_EXTEND, dl, Op->getValueType(0), SetCC);
10942 return DAG.getNode(ISD::MERGE_VALUES, dl, Op->getVTList(),
10943 Ret, SDValue(InTrans.getNode(), 1));
1093210944 }
1093310945 }
1093410946 }
1277112783 case X86ISD::FMSUBADD: return "X86ISD::FMSUBADD";
1277212784 case X86ISD::PCMPESTRI: return "X86ISD::PCMPESTRI";
1277312785 case X86ISD::PCMPISTRI: return "X86ISD::PCMPISTRI";
12786 case X86ISD::XTEST: return "X86ISD::XTEST";
1277412787 }
1277512788 }
1277612789
358358 // PCMP*STRI
359359 PCMPISTRI,
360360 PCMPESTRI,
361
362 // XTEST - Test if in transactional execution.
363 XTEST,
361364
362365 // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG,
363366 // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG -
603603 def HasBMI2 : Predicate<"Subtarget->hasBMI2()">;
604604 def HasRTM : Predicate<"Subtarget->hasRTM()">;
605605 def HasHLE : Predicate<"Subtarget->hasHLE()">;
606 def HasTSX : Predicate<"Subtarget->hasRTM() || Subtarget->hasHLE()">;
606607 def HasADX : Predicate<"Subtarget->hasADX()">;
607608 def HasPRFCHW : Predicate<"Subtarget->hasPRFCHW()">;
608609 def HasPrefetchW : Predicate<"Subtarget->has3DNow() || Subtarget->hasPRFCHW()">;
1414 //===----------------------------------------------------------------------===//
1515 // TSX instructions
1616
17 def X86xtest: SDNode<"X86ISD::XTEST", SDTypeProfile<1, 0, [SDTCisVT<0, i32>]>,
18 [SDNPHasChain, SDNPSideEffect]>;
19
1720 let usesCustomInserter = 1 in
1821 def XBEGIN : I<0, Pseudo, (outs GR32:$dst), (ins),
1922 "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
2730 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
2831
2932 let Defs = [EFLAGS] in
30 def XTEST : I<0x01, MRM_D6, (outs), (ins), "xtest", []>, TB, Requires<[HasRTM]>;
33 def XTEST : I<0x01, MRM_D6, (outs), (ins),
34 "xtest", [(set EFLAGS, (X86xtest))]>, TB, Requires<[HasTSX]>;
3135
3236 def XABORT : Ii8<0xc6, MRM_F8, (outs), (ins i8imm:$imm),
3337 "xabort\t$imm",
0 ; RUN: llc < %s -march=x86-64 -mattr=+rtm | FileCheck %s
1
2 declare i32 @llvm.x86.xtest() nounwind
3
4 define i32 @test_xtest() nounwind uwtable {
5 entry:
6 %0 = tail call i32 @llvm.x86.xtest() nounwind
7 ret i32 %0
8 ; CHECK: test_xtest
9 ; CHECK: xtest
10 }