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[AArch64] Add command-line option for SB SB (Speculative Barrier) is only mandatory from 8.5 onwards but is optional from Armv8.0-A. This patch adds a command line option to enable SB, as it was previously only possible to enable by selecting -march=armv8.5-a. This patch also moves to FeatureSB the old FeatureSpecRestrict. Reviewers: pbarrio, olista01, t.p.northover, LukeCheeseman Differential Revision: https://reviews.llvm.org/D55921 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@350126 91177308-0d34-0410-b5e6-96231b3b80d8 Diogo N. Sampaio 1 year, 9 months ago
10 changed file(s) with 33 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
7272 AARCH64_ARCH_EXT_NAME("rng", AArch64::AEK_RAND, "+rand", "-rand")
7373 AARCH64_ARCH_EXT_NAME("memtag", AArch64::AEK_MTE, "+mte", "-mte")
7474 AARCH64_ARCH_EXT_NAME("ssbs", AArch64::AEK_SSBS, "+ssbs", "-ssbs")
75 AARCH64_ARCH_EXT_NAME("sb", AArch64::AEK_SB, "+sb", "-sb")
7576 #undef AARCH64_ARCH_EXT_NAME
7677
7778 #ifndef AARCH64_CPU_NAME
4747 AEK_RAND = 1 << 18,
4848 AEK_MTE = 1 << 19,
4949 AEK_SSBS = 1 << 20,
50 AEK_SB = 1 << 21,
5051 };
5152
5253 enum class ArchKind {
305305 def FeatureSpecRestrict : SubtargetFeature<"specrestrict", "HasSpecRestrict",
306306 "true", "Enable architectural speculation restriction" >;
307307
308 def FeatureSB : SubtargetFeature<"sb", "HasSB",
309 "true", "Enable v8.5 Speculation Barrier" >;
310
308311 def FeatureSSBS : SubtargetFeature<"ssbs", "HasSSBS",
309312 "true", "Enable Speculative Store Bypass Safe bit" >;
310
311 def FeatureSpecCtrl : SubtargetFeature<"specctrl", "HasSpecCtrl", "true",
312 "Enable speculation control barrier" >;
313313
314314 def FeaturePredCtrl : SubtargetFeature<"predctrl", "HasPredCtrl", "true",
315315 "Enable execution and data prediction invalidation instructions" >;
351351 def HasV8_5aOps : SubtargetFeature<
352352 "v8.5a", "HasV8_5aOps", "true", "Support ARM v8.5a instructions",
353353 [HasV8_4aOps, FeatureAltFPCmp, FeatureFRInt3264, FeatureSpecRestrict,
354 FeatureSSBS, FeatureSpecCtrl, FeaturePredCtrl, FeatureCacheDeepPersist,
354 FeatureSSBS, FeatureSB, FeaturePredCtrl, FeatureCacheDeepPersist,
355355 FeatureBranchTargetId]
356356 >;
357357
113113 AssemblerPredicate<"FeatureAltFPCmp", "altnzcv">;
114114 def HasFRInt3264 : Predicate<"Subtarget->hasFRInt3264()">,
115115 AssemblerPredicate<"FeatureFRInt3264", "frint3264">;
116 def HasSpecCtrl : Predicate<"Subtarget->hasSpecCtrl()">,
117 AssemblerPredicate<"FeatureSpecCtrl", "specctrl">;
116 def HasSB : Predicate<"Subtarget->hasSB()">,
117 AssemblerPredicate<"FeatureSB", "sb">;
118118 def HasPredCtrl : Predicate<"Subtarget->hasPredCtrl()">,
119119 AssemblerPredicate<"FeaturePredCtrl", "predctrl">;
120120 def HasCCDP : Predicate<"Subtarget->hasCCDP()">,
732732 def SB : SimpleSystemI<0, (ins), "sb", "">, Sched<[]> {
733733 let Inst{20-5} = 0b0001100110000111;
734734 let Unpredictable{11-8} = 0b1111;
735 let Predicates = [HasSpecCtrl];
735 let Predicates = [HasSB];
736736 let hasSideEffects = 1;
737737 }
738738
125125 bool HasAlternativeNZCV = false;
126126 bool HasFRInt3264 = false;
127127 bool HasSpecRestrict = false;
128 bool HasSpecCtrl = false;
129128 bool HasSSBS = false;
129 bool HasSB = false;
130130 bool HasPredCtrl = false;
131131 bool HasCCDP = false;
132132 bool HasBTI = false;
354354 bool hasAlternativeNZCV() const { return HasAlternativeNZCV; }
355355 bool hasFRInt3264() const { return HasFRInt3264; }
356356 bool hasSpecRestrict() const { return HasSpecRestrict; }
357 bool hasSpecCtrl() const { return HasSpecCtrl; }
358357 bool hasSSBS() const { return HasSSBS; }
358 bool hasSB() const { return HasSB; }
359359 bool hasPredCtrl() const { return HasPredCtrl; }
360360 bool hasCCDP() const { return HasCCDP; }
361361 bool hasBTI() const { return HasBTI; }
0 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+sb -o - %s | FileCheck %s
1 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a -o - %s | FileCheck %s
2 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-sb -o - %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 // Flag manipulation
5 sb
6
7 // CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
8
9 // NOSB: instruction requires: sb
10 // NOSB-NEXT: sb
+0
-11
test/MC/AArch64/armv8.5a-specctrl.s less more
None // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+specctrl < %s | FileCheck %s
1 // RUN: llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=+v8.5a < %s | FileCheck %s
2 // RUN: not llvm-mc -triple aarch64-none-linux-gnu -show-encoding -mattr=-specctrl < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 // Flag manipulation
5 sb
6
7 // CHECK: sb // encoding: [0xff,0x30,0x03,0xd5]
8
9 // NOSB: instruction requires: specctrl
10 // NOSB-NEXT: sb
0 # RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+sb -disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-sb -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 # New reg
5 0xff 0x30 0x03 0xd5
6
7 # CHECK: sb
8 # NOSB: msr S0_3_C3_C0_7, xzr
+0
-9
test/MC/Disassembler/AArch64/armv8.5a-specctrl.txt less more
None # RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+specctrl -disassemble < %s | FileCheck %s
1 # RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=+v8.5a -disassemble < %s | FileCheck %s
2 # RUN: llvm-mc -triple=aarch64-none-linux-gnu -mattr=-specctrl -disassemble < %s 2>&1 | FileCheck %s --check-prefix=NOSB
3
4 # New reg
5 0xff 0x30 0x03 0xd5
6
7 # CHECK: sb
8 # NOSB: msr S0_3_C3_C0_7, xzr
987987 {"rcpc", "norcpc", "+rcpc", "-rcpc" },
988988 {"rng", "norng", "+rand", "-rand"},
989989 {"memtag", "nomemtag", "+mte", "-mte"},
990 {"ssbs", "nossbs", "+ssbs", "-ssbs"}};
990 {"ssbs", "nossbs", "+ssbs", "-ssbs"},
991 {"sb", "nosb", "+sb", "-sb"}};
991992
992993 for (unsigned i = 0; i < array_lengthof(ArchExt); i++) {
993994 EXPECT_EQ(StringRef(ArchExt[i][2]),