llvm.org GIT mirror llvm / f84be78
Revert "[misched] Extend scheduler to handle unsupported features" This reverts commit r273551. Patch contained a wrong check for isUnsupported. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@273565 91177308-0d34-0410-b5e6-96231b3b80d8 Simon Dardis 4 years ago
3 changed file(s) with 1 addition(s) and 53 deletion(s). Raw diff Collapse all Expand all
5353 include "llvm/Target/TargetItinerary.td"
5454
5555 class Instruction; // Forward def
56
57 class Predicate; // Forward def
5856
5957 // DAG operator that interprets the DAG args as Instruction defs.
6058 def instrs;
9795 // or there will be no way to catch simple errors in the model
9896 // resulting from changes to the instruction definitions.
9997 bit CompleteModel = 1;
100
101 // A processor may only implement part of published ISA, due to either new ISA
102 // extensions, (e.g. Pentium 4 doesn't have AVX) or implementation
103 // (ARM/MIPS/PowerPC/SPARC soft float cores).
104 //
105 // For a processor which doesn't support some feature(s), the schedule model
106 // can use:
107 //
108 // let UnsupportedFeatures = [HaveA,..,HaveY];
109 //
110 // to skip the checks for scheduling information when building LLVM for
111 // instructions which have any of the listed predicates in their Predicates
112 // field.
113 list UnsupportedFeatures = [];
11498
11599 bit NoModel = 0; // Special tag to indicate missing machine model.
116100 }
118118 // Find ItinRW records for each processor and itinerary class.
119119 // (For per-operand resources mapped to itinerary classes).
120120 collectProcItinRW();
121
122 // Find UnsupportedFeatures records for each processor.
123 // (For per-operand resources mapped to itinerary classes).
124 collectProcUnsupportedFeatures();
125121
126122 // Infer new SchedClasses from SchedVariant.
127123 inferSchedClasses();
832828 }
833829 }
834830
835 // Gather the unsupported features for processor models.
836 void CodeGenSchedModels::collectProcUnsupportedFeatures() {
837 for (CodeGenProcModel &ProcModel : ProcModels) {
838 for (Record *Pred : ProcModel.ModelDef->getValueAsListOfDefs("UnsupportedFeatures")) {
839 ProcModel.UnsupportedFeaturesDefs.push_back(Pred);
840 }
841 }
842 }
843
844831 /// Infer new classes from existing classes. In the process, this may create new
845832 /// SchedWrites from sequences of existing SchedWrites.
846833 void CodeGenSchedModels::inferSchedClasses() {
15521539 for (const CodeGenInstruction *Inst : Target.getInstructionsByEnumValue()) {
15531540 if (Inst->hasNoSchedulingInfo)
15541541 continue;
1555 if (ProcModel.isUnsupported(*Inst))
1556 continue;
15571542 unsigned SCIdx = getSchedClassIdx(*Inst);
15581543 if (!SCIdx) {
15591544 if (Inst->TheDef->isValueUnset("SchedRW") && !HadCompleteModel) {
15891574 << "- Consider setting 'CompleteModel = 0' while developing new models.\n"
15901575 << "- Pseudo instructions can be marked with 'hasNoSchedulingInfo = 1'.\n"
15911576 << "- Instructions should usually have Sched<[...]> as a superclass, "
1592 "you may temporarily use an empty list.\n"
1593 << "- Instructions related to unsupported features can be excluded with "
1594 "list UnsupportedFeatures = [HasA,..,HasY]; in the "
1595 "processor model.\n\n";
1577 "you may temporarily use an empty list.\n\n";
15961578 PrintFatalError("Incomplete schedule model");
15971579 }
15981580 }
17731755 return 1 + (PRPos - ProcResourceDefs.begin());
17741756 }
17751757
1776 bool CodeGenProcModel::isUnsupported(const CodeGenInstruction &Inst) const {
1777 for (const Record *TheDef : UnsupportedFeaturesDefs) {
1778 for (const Record *PredDef : Inst.TheDef->getValueAsListOfDefs("Predicates")) {
1779 if (TheDef->getName() == PredDef->getName())
1780 return true;
1781 }
1782 }
1783 return false;
1784 }
1785
17861758 #ifndef NDEBUG
17871759 void CodeGenProcModel::dump() const {
17881760 dbgs() << Index << ": " << ModelName << " "
188188 // This list is empty if no ItinRW refers to this Processor.
189189 RecVec ItinRWDefs;
190190
191 // List of unsupported feature.
192 // This list is empty if the Processor has no UnsupportedFeatures.
193 RecVec UnsupportedFeaturesDefs;
194
195191 // All read/write resources associated with this processor.
196192 RecVec WriteResDefs;
197193 RecVec ReadAdvanceDefs;
213209 }
214210
215211 unsigned getProcResourceIdx(Record *PRDef) const;
216
217 bool isUnsupported(const CodeGenInstruction &Inst) const;
218212
219213 #ifndef NDEBUG
220214 void dump() const;
407401
408402 void collectProcItinRW();
409403
410 void collectProcUnsupportedFeatures();
411
412404 void inferSchedClasses();
413405
414406 void checkCompleteness();