llvm.org GIT mirror llvm / f7f8459
[ARM] Simplify tests and make checks more rigid. NFC. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@249432 91177308-0d34-0410-b5e6-96231b3b80d8 Chad Rosier 4 years ago
1 changed file(s) with 36 addition(s) and 67 deletion(s). Raw diff Collapse all Expand all
0 ; RUN: llc < %s -mtriple=armv7-apple-ios | FileCheck %s
11
2 @in = global float 0x400921FA00000000, align 4
3
42 ; Test signed conversion.
5 ; CHECK: t0
6 ; CHECK-NOT: vmul
7 define void @t0() nounwind {
8 entry:
9 %tmp = load float, float* @in, align 4
10 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
11 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
12 %mul.i = fmul <2 x float> %vecinit2.i,
3 ; CHECK-LABEL: @t0
4 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #2
5 ; CHECK: bx lr
6 define <2 x i32> @t0(<2 x float> %in) {
7 %mul.i = fmul <2 x float> %in,
138 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
14 tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
15 ret void
9 ret <2 x i32> %vcvt.i
1610 }
1711
18 declare void @foo_int32x2_t(<2 x i32>)
19
2012 ; Test unsigned conversion.
21 ; CHECK: t1
22 ; CHECK-NOT: vmul
23 define void @t1() nounwind {
24 entry:
25 %tmp = load float, float* @in, align 4
26 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
27 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
28 %mul.i = fmul <2 x float> %vecinit2.i,
13 ; CHECK-LABEL: @t1
14 ; CHECK: vcvt.u32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #3
15 ; CHECK: bx lr
16 define <2 x i32> @t1(<2 x float> %in) {
17 %mul.i = fmul <2 x float> %in,
2918 %vcvt.i = fptoui <2 x float> %mul.i to <2 x i32>
30 tail call void @foo_uint32x2_t(<2 x i32> %vcvt.i) nounwind
31 ret void
19 ret <2 x i32> %vcvt.i
3220 }
3321
34 declare void @foo_uint32x2_t(<2 x i32>)
35
3622 ; Test which should not fold due to non-power of 2.
37 ; CHECK: t2
23 ; CHECK-LABEL: @t2
3824 ; CHECK: vmul
39 define void @t2() nounwind {
25 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
26 ; CHECK: bx lr
27 define <2 x i32> @t2(<2 x float> %in) {
4028 entry:
41 %tmp = load float, float* @in, align 4
42 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
43 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
44 %mul.i = fmul <2 x float> %vecinit2.i,
29 %mul.i = fmul <2 x float> %in,
4530 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
46 tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
47 ret void
31 ret <2 x i32> %vcvt.i
4832 }
4933
5034 ; Test which should not fold due to power of 2 out of range.
51 ; CHECK: t3
35 ; CHECK-LABEL: @t3
5236 ; CHECK: vmul
53 define void @t3() nounwind {
54 entry:
55 %tmp = load float, float* @in, align 4
56 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
57 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
58 %mul.i = fmul <2 x float> %vecinit2.i,
37 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}
38 ; CHECK: bx lr
39 define <2 x i32> @t3(<2 x float> %in) {
40 %mul.i = fmul <2 x float> %in,
5941 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
60 tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
61 ret void
42 ret <2 x i32> %vcvt.i
6243 }
6344
6445 ; Test which case where const is max power of 2 (i.e., 2^32).
65 ; CHECK: t4
66 ; CHECK-NOT: vmul
67 define void @t4() nounwind {
68 entry:
69 %tmp = load float, float* @in, align 4
70 %vecinit.i = insertelement <2 x float> undef, float %tmp, i32 0
71 %vecinit2.i = insertelement <2 x float> %vecinit.i, float %tmp, i32 1
72 %mul.i = fmul <2 x float> %vecinit2.i,
46 ; CHECK-LABEL: @t4
47 ; CHECK: vcvt.s32.f32 d{{[0-9]+}}, d{{[0-9]+}}, #32
48 ; CHECK: bx lr
49 define <2 x i32> @t4(<2 x float> %in) {
50 %mul.i = fmul <2 x float> %in,
7351 %vcvt.i = fptosi <2 x float> %mul.i to <2 x i32>
74 tail call void @foo_int32x2_t(<2 x i32> %vcvt.i) nounwind
75 ret void
52 ret <2 x i32> %vcvt.i
7653 }
7754
7855 ; Test quadword.
79 ; CHECK: t5
80 ; CHECK-NOT: vmul
81 define void @t5() nounwind {
82 entry:
83 %tmp = load float, float* @in, align 4
84 %vecinit.i = insertelement <4 x float> undef, float %tmp, i32 0
85 %vecinit2.i = insertelement <4 x float> %vecinit.i, float %tmp, i32 1
86 %vecinit4.i = insertelement <4 x float> %vecinit2.i, float %tmp, i32 2
87 %vecinit6.i = insertelement <4 x float> %vecinit4.i, float %tmp, i32 3
88 %mul.i = fmul <4 x float> %vecinit6.i,
56 ; CHECK-LABEL: @t5
57 ; CHECK: vcvt.s32.f32 q{{[0-9]+}}, q{{[0-9]+}}, #3
58 ; CHECK: bx lr
59 define <4 x i32> @t5(<4 x float> %in) {
60 %mul.i = fmul <4 x float> %in,
8961 %vcvt.i = fptosi <4 x float> %mul.i to <4 x i32>
90 tail call void @foo_int32x4_t(<4 x i32> %vcvt.i) nounwind
91 ret void
62 ret <4 x i32> %vcvt.i
9263 }
93
94 declare void @foo_int32x4_t(<4 x i32>)